VirtualBox

source: vbox/trunk/include/VBox/x86.mac@ 21013

最後變更 在這個檔案從21013是 20742,由 vboxsync 提交於 15 年 前

VMM,++: Increased the stack size on darwin to 16KB since we're switching stack and 16KB is the kernel stack size of xnu. Added support for conditionals to the .h -> .mac conversion sed-script.
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 24.5 KB
行 
1%ifndef ___VBox_x86_h
2%define ___VBox_x86_h
3%ifdef RT_OS_SOLARIS
4%endif
5%define X86_EFL_CF RT_BIT(0)
6%define X86_EFL_PF RT_BIT(2)
7%define X86_EFL_AF RT_BIT(4)
8%define X86_EFL_ZF RT_BIT(6)
9%define X86_EFL_SF RT_BIT(7)
10%define X86_EFL_TF RT_BIT(8)
11%define X86_EFL_IF RT_BIT(9)
12%define X86_EFL_DF RT_BIT(10)
13%define X86_EFL_OF RT_BIT(11)
14%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
15%define X86_EFL_NT RT_BIT(14)
16%define X86_EFL_RF RT_BIT(16)
17%define X86_EFL_VM RT_BIT(17)
18%define X86_EFL_AC RT_BIT(18)
19%define X86_EFL_VIF RT_BIT(19)
20%define X86_EFL_VIP RT_BIT(20)
21%define X86_EFL_ID RT_BIT(21)
22%define X86_EFL_IOPL_SHIFT 12
23%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
24%define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
25%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
26%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
27%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
28%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
29%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
30%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
31%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
32%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
33%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
34%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
35%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
36%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
37%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
38%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
39%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
40%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
41%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
42%define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
43%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
44%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
45%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
46%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
47%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
48%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
49%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
50%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
51%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
52%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
53%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
54%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
55%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
56%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
57%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
58%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
59%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
60%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
61%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
62%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
63%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
64%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
65%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
66%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
67%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
68%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
69%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
70%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
71%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
72%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
73%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
74%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
75%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
76%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
77%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
78%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
79%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
80%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
81%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
82%define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
83%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
84%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
85%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
86%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
87%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
88%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
89%define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
90%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
91%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
92%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
93%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
94%define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
95%define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
96%define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
97%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
98%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
99%define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
100%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
101%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
102%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
103%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
104%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
105%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
106%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
107%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
108%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
109%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
110%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
111%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
112%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
113%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
114%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
115%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
116%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
117%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
118%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
119%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
120%define X86_CR0_PE RT_BIT(0)
121%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
122%define X86_CR0_MP RT_BIT(1)
123%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
124%define X86_CR0_EM RT_BIT(2)
125%define X86_CR0_EMULATE_FPU RT_BIT(2)
126%define X86_CR0_TS RT_BIT(3)
127%define X86_CR0_TASK_SWITCH RT_BIT(3)
128%define X86_CR0_ET RT_BIT(4)
129%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
130%define X86_CR0_NE RT_BIT(5)
131%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
132%define X86_CR0_WP RT_BIT(16)
133%define X86_CR0_WRITE_PROTECT RT_BIT(16)
134%define X86_CR0_AM RT_BIT(18)
135%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
136%define X86_CR0_NW RT_BIT(29)
137%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
138%define X86_CR0_CD RT_BIT(30)
139%define X86_CR0_CACHE_DISABLE RT_BIT(30)
140%define X86_CR0_PG RT_BIT(31)
141%define X86_CR0_PAGING RT_BIT(31)
142%define X86_CR3_PWT RT_BIT(3)
143%define X86_CR3_PCD RT_BIT(4)
144%define X86_CR3_PAGE_MASK (0xfffff000)
145%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
146%define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
147%define X86_CR4_VME RT_BIT(0)
148%define X86_CR4_PVI RT_BIT(1)
149%define X86_CR4_TSD RT_BIT(2)
150%define X86_CR4_DE RT_BIT(3)
151%define X86_CR4_PSE RT_BIT(4)
152%define X86_CR4_PAE RT_BIT(5)
153%define X86_CR4_MCE RT_BIT(6)
154%define X86_CR4_PGE RT_BIT(7)
155%define X86_CR4_PCE RT_BIT(8)
156%define X86_CR4_OSFSXR RT_BIT(9)
157%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
158%define X86_CR4_VMXE RT_BIT(13)
159%define X86_DR6_B0 RT_BIT(0)
160%define X86_DR6_B1 RT_BIT(1)
161%define X86_DR6_B2 RT_BIT(2)
162%define X86_DR6_B3 RT_BIT(3)
163%define X86_DR6_BD RT_BIT(13)
164%define X86_DR6_BS RT_BIT(14)
165%define X86_DR6_BT RT_BIT(15)
166%define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
167%define X86_DR7_L0 RT_BIT(0)
168%define X86_DR7_G0 RT_BIT(1)
169%define X86_DR7_L1 RT_BIT(2)
170%define X86_DR7_G1 RT_BIT(3)
171%define X86_DR7_L2 RT_BIT(4)
172%define X86_DR7_G2 RT_BIT(5)
173%define X86_DR7_L3 RT_BIT(6)
174%define X86_DR7_G3 RT_BIT(7)
175%define X86_DR7_LE RT_BIT(8)
176%define X86_DR7_GE RT_BIT(9)
177%define X86_DR7_GD RT_BIT(13)
178%define X86_DR7_RW0_MASK (3 << 16)
179%define X86_DR7_LEN0_MASK (3 << 18)
180%define X86_DR7_RW1_MASK (3 << 20)
181%define X86_DR7_LEN1_MASK (3 << 22)
182%define X86_DR7_RW2_MASK (3 << 24)
183%define X86_DR7_LEN2_MASK (3 << 26)
184%define X86_DR7_RW3_MASK (3 << 28)
185%define X86_DR7_LEN3_MASK (3 << 30)
186%define X86_DR7_MB1_MASK (RT_BIT(10))
187%define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
188%define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
189%define X86_DR7_RW_EO 0
190%define X86_DR7_RW_WO 1
191%define X86_DR7_RW_IO 2
192%define X86_DR7_RW_RW 3
193%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
194%define X86_DR7_LEN_BYTE 0
195%define X86_DR7_LEN_WORD 1
196%define X86_DR7_LEN_QWORD 2
197%define X86_DR7_LEN_DWORD 3
198%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
199%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3)
200%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
201%define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
202%define X86_DR7_INIT_VAL 0x400
203%define MSR_IA32_TSC 0x10
204%define MSR_IA32_PLATFORM_ID 0x17
205%ifndef MSR_IA32_APICBASE
206%define MSR_IA32_APICBASE 0x1b
207%endif
208%define MSR_IA32_FEATURE_CONTROL 0x3A
209%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
210%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
211%define MSR_IA32_BIOS_UPDT_TRIG 0x79
212%define MSR_IA32_BIOS_SIGN_ID 0x8B
213%define MSR_IA32_MTRR_CAP 0xFE
214%ifndef MSR_IA32_SYSENTER_CS
215%define MSR_IA32_SYSENTER_CS 0x174
216%define MSR_IA32_SYSENTER_ESP 0x175
217%define MSR_IA32_SYSENTER_EIP 0x176
218%endif
219%define MSR_IA32_MCP_CAP 0x179
220%define MSR_IA32_MCP_STATUS 0x17A
221%define MSR_IA32_MCP_CTRL 0x17B
222%define MSR_IA32_CR_PAT 0x277
223%define MSR_IA32_PERFEVTSEL0 0x186
224%define MSR_IA32_PERFEVTSEL1 0x187
225%define MSR_IA32_PERF_STATUS 0x198
226%define MSR_IA32_PERF_CTL 0x199
227%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
228%define MSR_IA32_MC0_CTL 0x400
229%define MSR_IA32_MC0_STATUS 0x401
230%define MSR_IA32_VMX_BASIC_INFO 0x480
231%define MSR_IA32_VMX_PINBASED_CTLS 0x481
232%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
233%define MSR_IA32_VMX_EXIT_CTLS 0x483
234%define MSR_IA32_VMX_ENTRY_CTLS 0x484
235%define MSR_IA32_VMX_MISC 0x485
236%define MSR_IA32_VMX_CR0_FIXED0 0x486
237%define MSR_IA32_VMX_CR0_FIXED1 0x487
238%define MSR_IA32_VMX_CR4_FIXED0 0x488
239%define MSR_IA32_VMX_CR4_FIXED1 0x489
240%define MSR_IA32_VMX_VMCS_ENUM 0x48A
241%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
242%define MSR_IA32_VMX_EPT_CAPS 0x48C
243%define MSR_IA32_APIC_START 0x800
244%define MSR_IA32_APIC_END 0x900
245%define MSR_K6_EFER 0xc0000080
246%define MSR_K6_EFER_SCE RT_BIT(0)
247%define MSR_K6_EFER_LME RT_BIT(8)
248%define MSR_K6_EFER_LMA RT_BIT(10)
249%define MSR_K6_EFER_NXE RT_BIT(11)
250%define MSR_K6_EFER_SVME RT_BIT(12)
251%define MSR_K6_EFER_LMSLE RT_BIT(13)
252%define MSR_K6_EFER_FFXSR RT_BIT(14)
253%define MSR_K6_STAR 0xc0000081
254%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
255%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
256%define MSR_K6_STAR_SEL_MASK 0xffff
257%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
258%define MSR_K6_WHCR 0xc0000082
259%define MSR_K6_UWCCR 0xc0000085
260%define MSR_K6_PSOR 0xc0000087
261%define MSR_K6_PFIR 0xc0000088
262%define MSR_K7_EVNTSEL0 0xc0010000
263%define MSR_K7_EVNTSEL1 0xc0010001
264%define MSR_K7_EVNTSEL2 0xc0010002
265%define MSR_K7_EVNTSEL3 0xc0010003
266%define MSR_K7_PERFCTR0 0xc0010004
267%define MSR_K7_PERFCTR1 0xc0010005
268%define MSR_K7_PERFCTR2 0xc0010006
269%define MSR_K7_PERFCTR3 0xc0010007
270%define MSR_K8_LSTAR 0xc0000082
271%define MSR_K8_CSTAR 0xc0000083
272%define MSR_K8_SF_MASK 0xc0000084
273%define MSR_K8_FS_BASE 0xc0000100
274%define MSR_K8_GS_BASE 0xc0000101
275%define MSR_K8_KERNEL_GS_BASE 0xc0000102
276%define MSR_K8_TSC_AUX 0xc0000103
277%define MSR_K8_SYSCFG 0xc0010010
278%define MSR_K8_HWCR 0xc0010015
279%define MSR_K8_IORRBASE0 0xc0010016
280%define MSR_K8_IORRMASK0 0xc0010017
281%define MSR_K8_IORRBASE1 0xc0010018
282%define MSR_K8_IORRMASK1 0xc0010019
283%define MSR_K8_TOP_MEM1 0xc001001a
284%define MSR_K8_TOP_MEM2 0xc001001d
285%define MSR_K8_VM_CR 0xc0010114
286%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
287%define MSR_K8_IGNNE 0xc0010115
288%define MSR_K8_SMM_CTL 0xc0010116
289%define MSR_K8_VM_HSAVE_PA 0xc0010117
290%define X86_PG_ENTRIES 1024
291%define X86_PG_PAE_ENTRIES 512
292%define X86_PG_PAE_PDPE_ENTRIES 4
293%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
294%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
295%define X86_PAGE_4K_SIZE _4K
296%define X86_PAGE_4K_SHIFT 12
297%define X86_PAGE_4K_OFFSET_MASK 0xfff
298%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
299%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
300%define X86_PAGE_2M_SIZE _2M
301%define X86_PAGE_2M_SHIFT 21
302%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
303%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
304%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
305%define X86_PAGE_4M_SIZE _4M
306%define X86_PAGE_4M_SHIFT 22
307%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
308%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
309%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
310%define X86_PTE_BIT_P 0
311%define X86_PTE_BIT_RW 1
312%define X86_PTE_BIT_US 2
313%define X86_PTE_BIT_PWT 3
314%define X86_PTE_BIT_PCD 4
315%define X86_PTE_BIT_A 5
316%define X86_PTE_BIT_D 6
317%define X86_PTE_BIT_PAT 7
318%define X86_PTE_BIT_G 8
319%define X86_PTE_P RT_BIT(0)
320%define X86_PTE_RW RT_BIT(1)
321%define X86_PTE_US RT_BIT(2)
322%define X86_PTE_PWT RT_BIT(3)
323%define X86_PTE_PCD RT_BIT(4)
324%define X86_PTE_A RT_BIT(5)
325%define X86_PTE_D RT_BIT(6)
326%define X86_PTE_PAT RT_BIT(7)
327%define X86_PTE_G RT_BIT(8)
328%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
329%define X86_PTE_PG_MASK ( 0xfffff000 )
330%if 1
331%define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000 )
332%define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000 )
333%else
334%define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000 )
335%endif
336%define X86_PTE_PAE_NX RT_BIT_64(63)
337%define X86_PT_SHIFT 12
338%define X86_PT_MASK 0x3ff
339%define X86_PT_PAE_SHIFT 12
340%define X86_PT_PAE_MASK 0x1ff
341%define X86_PDE_P RT_BIT(0)
342%define X86_PDE_RW RT_BIT(1)
343%define X86_PDE_US RT_BIT(2)
344%define X86_PDE_PWT RT_BIT(3)
345%define X86_PDE_PCD RT_BIT(4)
346%define X86_PDE_A RT_BIT(5)
347%define X86_PDE_PS RT_BIT(7)
348%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
349%define X86_PDE_PG_MASK ( 0xfffff000 )
350%if 1
351%define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000 )
352%define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000 )
353%else
354%define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000 )
355%endif
356%define X86_PDE_PAE_NX RT_BIT_64(63)
357%define X86_PDE4M_P RT_BIT(0)
358%define X86_PDE4M_RW RT_BIT(1)
359%define X86_PDE4M_US RT_BIT(2)
360%define X86_PDE4M_PWT RT_BIT(3)
361%define X86_PDE4M_PCD RT_BIT(4)
362%define X86_PDE4M_A RT_BIT(5)
363%define X86_PDE4M_D RT_BIT(6)
364%define X86_PDE4M_PS RT_BIT(7)
365%define X86_PDE4M_G RT_BIT(8)
366%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
367%define X86_PDE4M_PAT RT_BIT(12)
368%define X86_PDE4M_PAT_SHIFT (12 - 7)
369%define X86_PDE4M_PG_MASK ( 0xffc00000 )
370%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
371%define X86_PDE4M_PG_HIGH_SHIFT 19
372%define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000 )
373%define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
374%define X86_PD_SHIFT 22
375%define X86_PD_MASK 0x3ff
376%define X86_PD_PAE_SHIFT 21
377%define X86_PD_PAE_MASK 0x1ff
378%define X86_PDPE_P RT_BIT(0)
379%define X86_PDPE_RW RT_BIT(1)
380%define X86_PDPE_US RT_BIT(2)
381%define X86_PDPE_PWT RT_BIT(3)
382%define X86_PDPE_PCD RT_BIT(4)
383%define X86_PDPE_A RT_BIT(5)
384%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
385%if 1
386%define X86_PDPE_PG_MASK ( 0x0000fffffffff000 )
387%define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000 )
388%else
389%define X86_PDPE_PG_MASK ( 0x000ffffffffff000 )
390%endif
391%define X86_PDPE_NX RT_BIT_64(63)
392%define X86_PDPT_SHIFT 30
393%define X86_PDPT_MASK_PAE 0x3
394%define X86_PDPT_MASK_AMD64 0x1ff
395%define X86_PML4E_P RT_BIT(0)
396%define X86_PML4E_RW RT_BIT(1)
397%define X86_PML4E_US RT_BIT(2)
398%define X86_PML4E_PWT RT_BIT(3)
399%define X86_PML4E_PCD RT_BIT(4)
400%define X86_PML4E_A RT_BIT(5)
401%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
402%if 1
403%define X86_PML4E_PG_MASK ( 0x0000fffffffff000 )
404%define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000 )
405%else
406%define X86_PML4E_PG_MASK ( 0x000ffffffffff000 )
407%endif
408%define X86_PML4E_NX RT_BIT_64(63)
409%define X86_PML4_SHIFT 39
410%define X86_PML4_MASK 0x1ff
411%if HC_ARCH_BITS == 64
412%else
413%endif
414%define X86DESC64_BASE(desc) \
415%define X86_SEL_TYPE_CODE 8
416%define X86_SEL_TYPE_MEMORY RT_BIT(4)
417%define X86_SEL_TYPE_ACCESSED 1
418%define X86_SEL_TYPE_DOWN 4
419%define X86_SEL_TYPE_CONF 4
420%define X86_SEL_TYPE_WRITE 2
421%define X86_SEL_TYPE_READ 2
422%define X86_SEL_TYPE_RO 0
423%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
424%define X86_SEL_TYPE_RW 2
425%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
426%define X86_SEL_TYPE_RO_DOWN 4
427%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
428%define X86_SEL_TYPE_RW_DOWN 6
429%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
430%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
431%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
432%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
433%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
434%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
435%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
436%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
437%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
438%define X86_SEL_TYPE_SYS_UNDEFINED 0
439%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
440%define X86_SEL_TYPE_SYS_LDT 2
441%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
442%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
443%define X86_SEL_TYPE_SYS_TASK_GATE 5
444%define X86_SEL_TYPE_SYS_286_INT_GATE 6
445%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
446%define X86_SEL_TYPE_SYS_UNDEFINED2 8
447%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
448%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
449%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
450%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
451%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
452%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
453%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
454%define AMD64_SEL_TYPE_SYS_LDT 2
455%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
456%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
457%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
458%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
459%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
460%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
461%define X86_DESC_S RT_BIT(12)
462%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
463%define X86_DESC_P RT_BIT(15)
464%define X86_DESC_AVL RT_BIT(20)
465%define X86_DESC_DB RT_BIT(22)
466%define X86_DESC_G RT_BIT(23)
467%define X86_SEL_SHIFT 3
468%define AMD64_SEL_SHIFT 4
469%if HC_ARCH_BITS == 64
470%define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
471%else
472%define X86_SEL_SHIFT_HC X86_SEL_SHIFT
473%endif
474%define X86_SEL_MASK 0xfff8
475%define X86_SEL_LDT 0x0004
476%define X86_SEL_RPL 0x0003
477%define X86_TRAP_ERR_EXTERNAL 1
478%define X86_TRAP_ERR_IDT 2
479%define X86_TRAP_ERR_TI 4
480%define X86_TRAP_ERR_SEL_MASK 0xfff8
481%define X86_TRAP_ERR_SEL_SHIFT 3
482%define X86_TRAP_PF_P RT_BIT(0)
483%define X86_TRAP_PF_RW RT_BIT(1)
484%define X86_TRAP_PF_US RT_BIT(2)
485%define X86_TRAP_PF_RSVD RT_BIT(3)
486%define X86_TRAP_PF_ID RT_BIT(4)
487%endif
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