VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 66599

最後變更 在這個檔案從66599是 66599,由 vboxsync 提交於 8 年 前

x86.h,bs2: X86_XCPT_MAX -> X86_XCPT_LAST; Corrected X86_XCPT_SX value.
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 48.1 KB
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1%ifndef ___iprt_x86_h
2%define ___iprt_x86_h
3%ifndef VBOX_FOR_DTRACE_LIB
4%else
5%endif
6%ifdef RT_OS_SOLARIS
7%endif
8%ifndef VBOX_FOR_DTRACE_LIB
9%endif
10%ifndef VBOX_FOR_DTRACE_LIB
11%endif
12%ifndef VBOX_FOR_DTRACE_LIB
13%endif
14%define X86_EFL_CF RT_BIT_32(0)
15%define X86_EFL_CF_BIT 0
16%define X86_EFL_1 RT_BIT_32(1)
17%define X86_EFL_PF RT_BIT_32(2)
18%define X86_EFL_AF RT_BIT_32(4)
19%define X86_EFL_AF_BIT 4
20%define X86_EFL_ZF RT_BIT_32(6)
21%define X86_EFL_ZF_BIT 6
22%define X86_EFL_SF RT_BIT_32(7)
23%define X86_EFL_SF_BIT 7
24%define X86_EFL_TF RT_BIT_32(8)
25%define X86_EFL_IF RT_BIT_32(9)
26%define X86_EFL_DF RT_BIT_32(10)
27%define X86_EFL_OF RT_BIT_32(11)
28%define X86_EFL_OF_BIT 11
29%define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
30%define X86_EFL_NT RT_BIT_32(14)
31%define X86_EFL_RF RT_BIT_32(16)
32%define X86_EFL_VM RT_BIT_32(17)
33%define X86_EFL_AC RT_BIT_32(18)
34%define X86_EFL_VIF RT_BIT_32(19)
35%define X86_EFL_VIP RT_BIT_32(20)
36%define X86_EFL_ID RT_BIT_32(21)
37%define X86_EFL_LIVE_MASK 0x003f7fd5
38%define X86_EFL_RA1_MASK RT_BIT_32(1)
39%define X86_EFL_IOPL_SHIFT 12
40%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
41%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
42 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
43%define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
44 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
45%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
46%ifndef VBOX_FOR_DTRACE_LIB
47%else
48%endif
49%ifndef VBOX_FOR_DTRACE_LIB
50%else
51%endif
52%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
53%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
54%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
55%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
56%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
57%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
58%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
59%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
60%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
61%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
62%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
63%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
64%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
65%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
66%define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
67%define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
68%define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
69%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
70%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
71%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
72%define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
73%define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
74%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
75%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
76%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
77%define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
78%define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
79%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
80%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
81%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
82%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
83%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
84%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
85%define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
86%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
87%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
88%define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
89%define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
90%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
91%define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
92%define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
93%define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
94%define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
95%define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
96%define X86_CPUID_FEATURE_EDX_PSE_BIT 3
97%define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
98%define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
99%define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
100%define X86_CPUID_FEATURE_EDX_PAE_BIT 6
101%define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
102%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
103%define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
104%define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
105%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
106%define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
107%define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
108%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
109%define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
110%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
111%define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
112%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
113%define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
114%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
115%define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
116%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
117%define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
118%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
119%define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
120%define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
121%define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
122%define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
123%define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
124%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
125%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
126%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
127%define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
128%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
129%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
130%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
131%define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
132%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
133%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
134%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
135%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
136%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
137%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
138%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
139%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
140%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
141%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
142%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
143%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
144%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
145%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
146%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
147%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
148%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
149%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
150%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
151%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
152%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
153%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
154%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
155%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
156%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
157%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
158%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
159%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
160%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
161%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
162%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
163%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
164%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
165%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
166%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
167%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
168%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
169%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
170%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
171%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
172%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
173%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
174%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
175%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
176%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
177%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
178%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
179%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
180%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
181%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
182%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
183%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
184%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
185%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
186%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
187%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
188%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
189%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
190%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
191%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
192%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
193%define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
194%define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
195%define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
196%define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
197%define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
198%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
199%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
200%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
201%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
202%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
203%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
204%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
205%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
206%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
207%define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
208%define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
209%define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
210%define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
211%define X86_CR0_PE RT_BIT_32(0)
212%define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
213%define X86_CR0_MP RT_BIT_32(1)
214%define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
215%define X86_CR0_EM RT_BIT_32(2)
216%define X86_CR0_EMULATE_FPU RT_BIT_32(2)
217%define X86_CR0_TS RT_BIT_32(3)
218%define X86_CR0_TASK_SWITCH RT_BIT_32(3)
219%define X86_CR0_ET RT_BIT_32(4)
220%define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
221%define X86_CR0_NE RT_BIT_32(5)
222%define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
223%define X86_CR0_WP RT_BIT_32(16)
224%define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
225%define X86_CR0_AM RT_BIT_32(18)
226%define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
227%define X86_CR0_NW RT_BIT_32(29)
228%define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
229%define X86_CR0_CD RT_BIT_32(30)
230%define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
231%define X86_CR0_PG RT_BIT_32(31)
232%define X86_CR0_PAGING RT_BIT_32(31)
233%define X86_CR3_PWT RT_BIT_32(3)
234%define X86_CR3_PCD RT_BIT_32(4)
235%define X86_CR3_PAGE_MASK (0xfffff000)
236%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
237%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
238%define X86_CR4_VME RT_BIT_32(0)
239%define X86_CR4_PVI RT_BIT_32(1)
240%define X86_CR4_TSD RT_BIT_32(2)
241%define X86_CR4_DE RT_BIT_32(3)
242%define X86_CR4_PSE RT_BIT_32(4)
243%define X86_CR4_PAE RT_BIT_32(5)
244%define X86_CR4_MCE RT_BIT_32(6)
245%define X86_CR4_PGE RT_BIT_32(7)
246%define X86_CR4_PCE RT_BIT_32(8)
247%define X86_CR4_OSFXSR RT_BIT_32(9)
248%define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
249%define X86_CR4_VMXE RT_BIT_32(13)
250%define X86_CR4_SMXE RT_BIT_32(14)
251%define X86_CR4_PCIDE RT_BIT_32(17)
252%define X86_CR4_OSXSAVE RT_BIT_32(18)
253%define X86_CR4_SMEP RT_BIT_32(20)
254%define X86_CR4_SMAP RT_BIT_32(21)
255%define X86_CR4_PKE RT_BIT_32(22)
256%define X86_DR6_B0 RT_BIT_32(0)
257%define X86_DR6_B1 RT_BIT_32(1)
258%define X86_DR6_B2 RT_BIT_32(2)
259%define X86_DR6_B3 RT_BIT_32(3)
260%define X86_DR6_B_MASK 0x0000000f
261%define X86_DR6_BD RT_BIT_32(13)
262%define X86_DR6_BS RT_BIT_32(14)
263%define X86_DR6_BT RT_BIT_32(15)
264%define X86_DR6_INIT_VAL 0xFFFF0FF0
265%define X86_DR6_RA1_MASK 0xffff0ff0
266%define X86_DR6_RAZ_MASK RT_BIT_64(12)
267%define X86_DR6_MBZ_MASK 0xffffffff00000000
268%define X86_DR6_B(iBp) RT_BIT_64(iBp)
269%define X86_DR7_L0 RT_BIT_32(0)
270%define X86_DR7_G0 RT_BIT_32(1)
271%define X86_DR7_L1 RT_BIT_32(2)
272%define X86_DR7_G1 RT_BIT_32(3)
273%define X86_DR7_L2 RT_BIT_32(4)
274%define X86_DR7_G2 RT_BIT_32(5)
275%define X86_DR7_L3 RT_BIT_32(6)
276%define X86_DR7_G3 RT_BIT_32(7)
277%define X86_DR7_LE RT_BIT_32(8)
278%define X86_DR7_GE RT_BIT_32(9)
279%define X86_DR7_LE_ALL 0x0000000000000055
280%define X86_DR7_GE_ALL 0x00000000000000aa
281%define X86_DR7_ICE_IR RT_BIT_32(12)
282%define X86_DR7_GD RT_BIT_32(13)
283%define X86_DR7_ICE_TR1 RT_BIT_32(14)
284%define X86_DR7_ICE_TR2 RT_BIT_32(15)
285%define X86_DR7_RW0_MASK (3 << 16)
286%define X86_DR7_LEN0_MASK (3 << 18)
287%define X86_DR7_RW1_MASK (3 << 20)
288%define X86_DR7_LEN1_MASK (3 << 22)
289%define X86_DR7_RW2_MASK (3 << 24)
290%define X86_DR7_LEN2_MASK (3 << 26)
291%define X86_DR7_RW3_MASK (3 << 28)
292%define X86_DR7_LEN3_MASK (3 << 30)
293%define X86_DR7_RA1_MASK RT_BIT_32(10)
294%define X86_DR7_RAZ_MASK 0x0000d800
295%define X86_DR7_MBZ_MASK 0xffffffff00000000
296%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
297%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
298%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
299%define X86_DR7_RW_EO 0
300%define X86_DR7_RW_WO 1
301%define X86_DR7_RW_IO 2
302%define X86_DR7_RW_RW 3
303%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
304%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
305%define X86_DR7_RW_ALL_MASKS 0x33330000
306%ifndef VBOX_FOR_DTRACE_LIB
307 %define X86_DR7_ANY_RW_IO(uDR7) \
308 ( ( 0x22220000 & (uDR7) )
309%endif
310%define X86_DR7_LEN_BYTE 0
311%define X86_DR7_LEN_WORD 1
312%define X86_DR7_LEN_QWORD 2
313%define X86_DR7_LEN_DWORD 3
314%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
315%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
316%define X86_DR7_ENABLED_MASK 0x000000ff
317%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
318%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
319%define X86_DR7_INIT_VAL 0x400
320%define MSR_P5_MC_ADDR 0x00000000
321%define MSR_P5_MC_TYPE 0x00000001
322%define MSR_IA32_TSC 0x10
323%define MSR_IA32_CESR 0x00000011
324%define MSR_IA32_CTR0 0x00000012
325%define MSR_IA32_CTR1 0x00000013
326%define MSR_IA32_PLATFORM_ID 0x17
327%ifndef MSR_IA32_APICBASE
328 %define MSR_IA32_APICBASE 0x1b
329 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
330 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
331 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
332 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
333 %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
334 %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
335%endif
336%define MSR_CORE_THREAD_COUNT 0x35
337%define MSR_IA32_FEATURE_CONTROL 0x3A
338%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
339%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
340%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
341%define MSR_IA32_TSC_ADJUST 0x3B
342%define MSR_IA32_BIOS_UPDT_TRIG 0x79
343%define MSR_IA32_BIOS_SIGN_ID 0x8B
344%define MSR_IA32_SMM_MONITOR_CTL 0x9B
345%define MSR_IA32_PMC0 0xC1
346%define MSR_IA32_PMC1 0xC2
347%define MSR_IA32_PMC2 0xC3
348%define MSR_IA32_PMC3 0xC4
349%define MSR_IA32_PLATFORM_INFO 0xCE
350%define MSR_IA32_FSB_CLOCK_STS 0xCD
351%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
352%define MSR_IA32_MPERF 0xE7
353%define MSR_IA32_APERF 0xE8
354%define MSR_IA32_MTRR_CAP 0xFE
355%define MSR_BBL_CR_CTL3 0x11e
356%ifndef MSR_IA32_SYSENTER_CS
357%define MSR_IA32_SYSENTER_CS 0x174
358%define MSR_IA32_SYSENTER_ESP 0x175
359%define MSR_IA32_SYSENTER_EIP 0x176
360%endif
361%define MSR_IA32_MCG_CAP 0x179
362%define MSR_IA32_MCG_STATUS 0x17A
363%define MSR_IA32_MCG_CTRL 0x17B
364%define MSR_IA32_CR_PAT 0x277
365%define MSR_IA32_PERFEVTSEL0 0x186
366%define MSR_IA32_PERFEVTSEL1 0x187
367%define MSR_FLEX_RATIO 0x194
368%define MSR_IA32_PERF_STATUS 0x198
369%define MSR_IA32_PERF_CTL 0x199
370%define MSR_IA32_THERM_STATUS 0x19c
371%define MSR_IA32_MISC_ENABLE 0x1A0
372%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
373%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
374%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
375%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
376%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
377%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
378%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
379%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
380%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
381%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
382%define MSR_IA32_DEBUGCTL 0x000001d9
383%define MSR_P4_LASTBRANCH_TOS 0x000001da
384%define MSR_P4_LASTBRANCH_0 0x000001db
385%define MSR_P4_LASTBRANCH_1 0x000001dc
386%define MSR_P4_LASTBRANCH_2 0x000001dd
387%define MSR_P4_LASTBRANCH_3 0x000001de
388%define IA32_MTRR_PHYSBASE0 0x200
389%define IA32_MTRR_PHYSMASK0 0x201
390%define IA32_MTRR_PHYSBASE1 0x202
391%define IA32_MTRR_PHYSMASK1 0x203
392%define IA32_MTRR_PHYSBASE2 0x204
393%define IA32_MTRR_PHYSMASK2 0x205
394%define IA32_MTRR_PHYSBASE3 0x206
395%define IA32_MTRR_PHYSMASK3 0x207
396%define IA32_MTRR_PHYSBASE4 0x208
397%define IA32_MTRR_PHYSMASK4 0x209
398%define IA32_MTRR_PHYSBASE5 0x20a
399%define IA32_MTRR_PHYSMASK5 0x20b
400%define IA32_MTRR_PHYSBASE6 0x20c
401%define IA32_MTRR_PHYSMASK6 0x20d
402%define IA32_MTRR_PHYSBASE7 0x20e
403%define IA32_MTRR_PHYSMASK7 0x20f
404%define IA32_MTRR_PHYSBASE8 0x210
405%define IA32_MTRR_PHYSMASK8 0x211
406%define IA32_MTRR_PHYSBASE9 0x212
407%define IA32_MTRR_PHYSMASK9 0x213
408%define IA32_MTRR_FIX64K_00000 0x250
409%define IA32_MTRR_FIX16K_80000 0x258
410%define IA32_MTRR_FIX16K_A0000 0x259
411%define IA32_MTRR_FIX4K_C0000 0x268
412%define IA32_MTRR_FIX4K_C8000 0x269
413%define IA32_MTRR_FIX4K_D0000 0x26a
414%define IA32_MTRR_FIX4K_D8000 0x26b
415%define IA32_MTRR_FIX4K_E0000 0x26c
416%define IA32_MTRR_FIX4K_E8000 0x26d
417%define IA32_MTRR_FIX4K_F0000 0x26e
418%define IA32_MTRR_FIX4K_F8000 0x26f
419%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
420%define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
421%define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
422%define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
423%define MSR_IA32_PEBS_ENABLE 0x3F1
424%define MSR_IA32_MC0_CTL 0x400
425%define MSR_IA32_MC0_STATUS 0x401
426%define MSR_IA32_VMX_BASIC_INFO 0x480
427%define MSR_IA32_VMX_PINBASED_CTLS 0x481
428%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
429%define MSR_IA32_VMX_EXIT_CTLS 0x483
430%define MSR_IA32_VMX_ENTRY_CTLS 0x484
431%define MSR_IA32_VMX_MISC 0x485
432%define MSR_IA32_VMX_CR0_FIXED0 0x486
433%define MSR_IA32_VMX_CR0_FIXED1 0x487
434%define MSR_IA32_VMX_CR4_FIXED0 0x488
435%define MSR_IA32_VMX_CR4_FIXED1 0x489
436%define MSR_IA32_VMX_VMCS_ENUM 0x48A
437%define MSR_IA32_VMX_VMFUNC 0x491
438%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
439%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
440%define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
441%define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
442%define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
443%define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
444%define MSR_IA32_DS_AREA 0x600
445%define MSR_RAPL_POWER_UNIT 0x606
446%define MSR_IA32_X2APIC_START 0x800
447%define MSR_IA32_X2APIC_ID 0x802
448%define MSR_IA32_X2APIC_VERSION 0x803
449%define MSR_IA32_X2APIC_TPR 0x808
450%define MSR_IA32_X2APIC_PPR 0x80A
451%define MSR_IA32_X2APIC_EOI 0x80B
452%define MSR_IA32_X2APIC_LDR 0x80D
453%define MSR_IA32_X2APIC_SVR 0x80F
454%define MSR_IA32_X2APIC_ISR0 0x810
455%define MSR_IA32_X2APIC_ISR1 0x811
456%define MSR_IA32_X2APIC_ISR2 0x812
457%define MSR_IA32_X2APIC_ISR3 0x813
458%define MSR_IA32_X2APIC_ISR4 0x814
459%define MSR_IA32_X2APIC_ISR5 0x815
460%define MSR_IA32_X2APIC_ISR6 0x816
461%define MSR_IA32_X2APIC_ISR7 0x817
462%define MSR_IA32_X2APIC_TMR0 0x818
463%define MSR_IA32_X2APIC_TMR1 0x819
464%define MSR_IA32_X2APIC_TMR2 0x81A
465%define MSR_IA32_X2APIC_TMR3 0x81B
466%define MSR_IA32_X2APIC_TMR4 0x81C
467%define MSR_IA32_X2APIC_TMR5 0x81D
468%define MSR_IA32_X2APIC_TMR6 0x81E
469%define MSR_IA32_X2APIC_TMR7 0x81F
470%define MSR_IA32_X2APIC_IRR0 0x820
471%define MSR_IA32_X2APIC_IRR1 0x821
472%define MSR_IA32_X2APIC_IRR2 0x822
473%define MSR_IA32_X2APIC_IRR3 0x823
474%define MSR_IA32_X2APIC_IRR4 0x824
475%define MSR_IA32_X2APIC_IRR5 0x825
476%define MSR_IA32_X2APIC_IRR6 0x826
477%define MSR_IA32_X2APIC_IRR7 0x827
478%define MSR_IA32_X2APIC_ESR 0x828
479%define MSR_IA32_X2APIC_LVT_CMCI 0x82F
480%define MSR_IA32_X2APIC_ICR 0x830
481%define MSR_IA32_X2APIC_LVT_TIMER 0x832
482%define MSR_IA32_X2APIC_LVT_THERMAL 0x833
483%define MSR_IA32_X2APIC_LVT_PERF 0x834
484%define MSR_IA32_X2APIC_LVT_LINT0 0x835
485%define MSR_IA32_X2APIC_LVT_LINT1 0x836
486%define MSR_IA32_X2APIC_LVT_ERROR 0x837
487%define MSR_IA32_X2APIC_TIMER_ICR 0x838
488%define MSR_IA32_X2APIC_TIMER_CCR 0x839
489%define MSR_IA32_X2APIC_TIMER_DCR 0x83E
490%define MSR_IA32_X2APIC_SELF_IPI 0x83F
491%define MSR_IA32_X2APIC_END 0xBFF
492%define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
493%define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
494%define MSR_K6_EFER 0xc0000080
495%define MSR_K6_EFER_SCE RT_BIT_32(0)
496%define MSR_K6_EFER_LME RT_BIT_32(8)
497%define MSR_K6_EFER_LMA RT_BIT_32(10)
498%define MSR_K6_EFER_NXE RT_BIT_32(11)
499%define MSR_K6_EFER_BIT_NXE 11
500%define MSR_K6_EFER_SVME RT_BIT_32(12)
501%define MSR_K6_EFER_LMSLE RT_BIT_32(13)
502%define MSR_K6_EFER_FFXSR RT_BIT_32(14)
503%define MSR_K6_EFER_TCE RT_BIT_32(15)
504%define MSR_K6_STAR 0xc0000081
505%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
506%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
507%define MSR_K6_STAR_SEL_MASK 0xffff
508%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
509%define MSR_K6_WHCR 0xc0000082
510%define MSR_K6_UWCCR 0xc0000085
511%define MSR_K6_PSOR 0xc0000087
512%define MSR_K6_PFIR 0xc0000088
513%define MSR_K7_EVNTSEL0 0xc0010000
514%define MSR_K7_EVNTSEL1 0xc0010001
515%define MSR_K7_EVNTSEL2 0xc0010002
516%define MSR_K7_EVNTSEL3 0xc0010003
517%define MSR_K7_PERFCTR0 0xc0010004
518%define MSR_K7_PERFCTR1 0xc0010005
519%define MSR_K7_PERFCTR2 0xc0010006
520%define MSR_K7_PERFCTR3 0xc0010007
521%define MSR_K8_LSTAR 0xc0000082
522%define MSR_K8_CSTAR 0xc0000083
523%define MSR_K8_SF_MASK 0xc0000084
524%define MSR_K8_FS_BASE 0xc0000100
525%define MSR_K8_GS_BASE 0xc0000101
526%define MSR_K8_KERNEL_GS_BASE 0xc0000102
527%define MSR_K8_TSC_AUX 0xc0000103
528%define MSR_K8_SYSCFG 0xc0010010
529%define MSR_K8_HWCR 0xc0010015
530%define MSR_K8_IORRBASE0 0xc0010016
531%define MSR_K8_IORRMASK0 0xc0010017
532%define MSR_K8_IORRBASE1 0xc0010018
533%define MSR_K8_IORRMASK1 0xc0010019
534%define MSR_K8_TOP_MEM1 0xc001001a
535%define MSR_K8_TOP_MEM2 0xc001001d
536%define MSR_K8_NB_CFG 0xc001001f
537%define MSR_K8_INT_PENDING 0xc0010055
538%define MSR_K8_VM_CR 0xc0010114
539%define MSR_K8_VM_CR_DPD RT_BIT_32(0)
540%define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
541%define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
542%define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
543%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
544%define MSR_K8_IGNNE 0xc0010115
545%define MSR_K8_SMM_CTL 0xc0010116
546%define MSR_K8_VM_HSAVE_PA 0xc0010117
547%define X86_PG_ENTRIES 1024
548%define X86_PG_PAE_ENTRIES 512
549%define X86_PG_PAE_PDPE_ENTRIES 4
550%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
551%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
552%define X86_PAGE_SIZE X86_PAGE_4K_SIZE
553%define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
554%define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
555%define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
556%define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
557%define X86_PAGE_4K_SIZE _4K
558%define X86_PAGE_4K_SHIFT 12
559%define X86_PAGE_4K_OFFSET_MASK 0xfff
560%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
561%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
562%define X86_PAGE_2M_SIZE _2M
563%define X86_PAGE_2M_SHIFT 21
564%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
565%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
566%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
567%define X86_PAGE_4M_SIZE _4M
568%define X86_PAGE_4M_SHIFT 22
569%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
570%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
571%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
572%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
573%define X86_PTE_BIT_P 0
574%define X86_PTE_BIT_RW 1
575%define X86_PTE_BIT_US 2
576%define X86_PTE_BIT_PWT 3
577%define X86_PTE_BIT_PCD 4
578%define X86_PTE_BIT_A 5
579%define X86_PTE_BIT_D 6
580%define X86_PTE_BIT_PAT 7
581%define X86_PTE_BIT_G 8
582%define X86_PTE_PAE_BIT_NX 63
583%define X86_PTE_P RT_BIT_32(0)
584%define X86_PTE_RW RT_BIT_32(1)
585%define X86_PTE_US RT_BIT_32(2)
586%define X86_PTE_PWT RT_BIT_32(3)
587%define X86_PTE_PCD RT_BIT_32(4)
588%define X86_PTE_A RT_BIT_32(5)
589%define X86_PTE_D RT_BIT_32(6)
590%define X86_PTE_PAT RT_BIT_32(7)
591%define X86_PTE_G RT_BIT_32(8)
592%define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
593%define X86_PTE_PG_MASK ( 0xfffff000 )
594%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
595%define X86_PTE_PAE_NX RT_BIT_64(63)
596%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
597%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
598%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
599%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
600%ifndef VBOX_FOR_DTRACE_LIB
601%endif
602%ifndef VBOX_FOR_DTRACE_LIB
603%endif
604%ifndef VBOX_FOR_DTRACE_LIB
605%endif
606%ifndef VBOX_FOR_DTRACE_LIB
607%endif
608%ifndef VBOX_FOR_DTRACE_LIB
609%endif
610%define X86_PT_SHIFT 12
611%define X86_PT_MASK 0x3ff
612%ifndef VBOX_FOR_DTRACE_LIB
613%endif
614%define X86_PT_PAE_SHIFT 12
615%define X86_PT_PAE_MASK 0x1ff
616%define X86_PDE_P RT_BIT_32(0)
617%define X86_PDE_RW RT_BIT_32(1)
618%define X86_PDE_US RT_BIT_32(2)
619%define X86_PDE_PWT RT_BIT_32(3)
620%define X86_PDE_PCD RT_BIT_32(4)
621%define X86_PDE_A RT_BIT_32(5)
622%define X86_PDE_PS RT_BIT_32(7)
623%define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
624%define X86_PDE_PG_MASK ( 0xfffff000 )
625%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
626%define X86_PDE_PAE_NX RT_BIT_64(63)
627%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
628%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
629%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
630%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
631%ifndef VBOX_FOR_DTRACE_LIB
632%endif
633%ifndef VBOX_FOR_DTRACE_LIB
634%endif
635%define X86_PDE4M_P RT_BIT_32(0)
636%define X86_PDE4M_RW RT_BIT_32(1)
637%define X86_PDE4M_US RT_BIT_32(2)
638%define X86_PDE4M_PWT RT_BIT_32(3)
639%define X86_PDE4M_PCD RT_BIT_32(4)
640%define X86_PDE4M_A RT_BIT_32(5)
641%define X86_PDE4M_D RT_BIT_32(6)
642%define X86_PDE4M_PS RT_BIT_32(7)
643%define X86_PDE4M_G RT_BIT_32(8)
644%define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
645%define X86_PDE4M_PAT RT_BIT_32(12)
646%define X86_PDE4M_PAT_SHIFT (12 - 7)
647%define X86_PDE4M_PG_MASK ( 0xffc00000 )
648%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
649%define X86_PDE4M_PG_HIGH_SHIFT 19
650%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
651%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
652%define X86_PDE2M_PAE_NX RT_BIT_64(63)
653%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
654%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
655%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
656%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
657%ifndef VBOX_FOR_DTRACE_LIB
658%endif
659%ifndef VBOX_FOR_DTRACE_LIB
660%endif
661%ifndef VBOX_FOR_DTRACE_LIB
662%endif
663%ifndef VBOX_FOR_DTRACE_LIB
664%endif
665%ifndef VBOX_FOR_DTRACE_LIB
666%endif
667%define X86_PD_SHIFT 22
668%define X86_PD_MASK 0x3ff
669%ifndef VBOX_FOR_DTRACE_LIB
670%endif
671%define X86_PD_PAE_SHIFT 21
672%define X86_PD_PAE_MASK 0x1ff
673%define X86_PDPE_P RT_BIT_32(0)
674%define X86_PDPE_RW RT_BIT_32(1)
675%define X86_PDPE_US RT_BIT_32(2)
676%define X86_PDPE_PWT RT_BIT_32(3)
677%define X86_PDPE_PCD RT_BIT_32(4)
678%define X86_PDPE_A RT_BIT_32(5)
679%define X86_PDPE_LM_PS RT_BIT_32(7)
680%define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
681%define X86_PDPE_PG_MASK 0x000ffffffffff000
682%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
683%define X86_PDPE_LM_NX RT_BIT_64(63)
684%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
685%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
686%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
687%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
688%ifndef VBOX_FOR_DTRACE_LIB
689%endif
690%ifndef VBOX_FOR_DTRACE_LIB
691%endif
692%ifndef VBOX_FOR_DTRACE_LIB
693%endif
694%ifndef VBOX_FOR_DTRACE_LIB
695%endif
696%ifndef VBOX_FOR_DTRACE_LIB
697%endif
698%define X86_PDPT_SHIFT 30
699%define X86_PDPT_MASK_PAE 0x3
700%define X86_PDPT_MASK_AMD64 0x1ff
701%define X86_PML4E_P RT_BIT_32(0)
702%define X86_PML4E_RW RT_BIT_32(1)
703%define X86_PML4E_US RT_BIT_32(2)
704%define X86_PML4E_PWT RT_BIT_32(3)
705%define X86_PML4E_PCD RT_BIT_32(4)
706%define X86_PML4E_A RT_BIT_32(5)
707%define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
708%define X86_PML4E_PG_MASK 0x000ffffffffff000
709%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
710%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
711%define X86_PML4E_NX RT_BIT_64(63)
712%ifndef VBOX_FOR_DTRACE_LIB
713%endif
714%ifndef VBOX_FOR_DTRACE_LIB
715%endif
716%ifndef VBOX_FOR_DTRACE_LIB
717%endif
718%define X86_PML4_SHIFT 39
719%define X86_PML4_MASK 0x1ff
720%ifndef VBOX_FOR_DTRACE_LIB
721%endif
722%ifndef VBOX_FOR_DTRACE_LIB
723%endif
724%ifndef VBOX_FOR_DTRACE_LIB
725%endif
726%ifndef VBOX_FOR_DTRACE_LIB
727%endif
728%ifndef VBOX_FOR_DTRACE_LIB
729%endif
730%define X86_OFF_FXSTATE_RSVD 0x1d0
731%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
732%ifndef VBOX_FOR_DTRACE_LIB
733%endif
734%define X86_FSW_IE RT_BIT_32(0)
735%define X86_FSW_DE RT_BIT_32(1)
736%define X86_FSW_ZE RT_BIT_32(2)
737%define X86_FSW_OE RT_BIT_32(3)
738%define X86_FSW_UE RT_BIT_32(4)
739%define X86_FSW_PE RT_BIT_32(5)
740%define X86_FSW_SF RT_BIT_32(6)
741%define X86_FSW_ES RT_BIT_32(7)
742%define X86_FSW_XCPT_MASK 0x007f
743%define X86_FSW_XCPT_ES_MASK 0x00ff
744%define X86_FSW_C0 RT_BIT_32(8)
745%define X86_FSW_C1 RT_BIT_32(9)
746%define X86_FSW_C2 RT_BIT_32(10)
747%define X86_FSW_TOP_MASK 0x3800
748%define X86_FSW_TOP_SHIFT 11
749%define X86_FSW_TOP_SMASK 0x0007
750%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
751%define X86_FSW_C3 RT_BIT_32(14)
752%define X86_FSW_C_MASK 0x4700
753%define X86_FSW_B RT_BIT_32(15)
754%define X86_FCW_IM RT_BIT_32(0)
755%define X86_FCW_DM RT_BIT_32(1)
756%define X86_FCW_ZM RT_BIT_32(2)
757%define X86_FCW_OM RT_BIT_32(3)
758%define X86_FCW_UM RT_BIT_32(4)
759%define X86_FCW_PM RT_BIT_32(5)
760%define X86_FCW_MASK_ALL 0x007f
761%define X86_FCW_XCPT_MASK 0x003f
762%define X86_FCW_PC_MASK 0x0300
763%define X86_FCW_PC_24 0x0000
764%define X86_FCW_PC_RSVD 0x0100
765%define X86_FCW_PC_53 0x0200
766%define X86_FCW_PC_64 0x0300
767%define X86_FCW_RC_MASK 0x0c00
768%define X86_FCW_RC_NEAREST 0x0000
769%define X86_FCW_RC_DOWN 0x0400
770%define X86_FCW_RC_UP 0x0800
771%define X86_FCW_RC_ZERO 0x0c00
772%define X86_FCW_ZERO_MASK 0xf080
773%define X86_MXSCR_IE RT_BIT_32(0)
774%define X86_MXSCR_DE RT_BIT_32(1)
775%define X86_MXSCR_ZE RT_BIT_32(2)
776%define X86_MXSCR_OE RT_BIT_32(3)
777%define X86_MXSCR_UE RT_BIT_32(4)
778%define X86_MXSCR_PE RT_BIT_32(5)
779%define X86_MXSCR_DAZ RT_BIT_32(6)
780%define X86_MXSCR_IM RT_BIT_32(7)
781%define X86_MXSCR_DM RT_BIT_32(8)
782%define X86_MXSCR_ZM RT_BIT_32(9)
783%define X86_MXSCR_OM RT_BIT_32(10)
784%define X86_MXSCR_UM RT_BIT_32(11)
785%define X86_MXSCR_PM RT_BIT_32(12)
786%define X86_MXSCR_RC_MASK 0x6000
787%define X86_MXSCR_RC_NEAREST 0x0000
788%define X86_MXSCR_RC_DOWN 0x2000
789%define X86_MXSCR_RC_UP 0x4000
790%define X86_MXSCR_RC_ZERO 0x6000
791%define X86_MXSCR_FZ RT_BIT_32(15)
792%define X86_MXSCR_MM RT_BIT_32(17)
793%ifndef VBOX_FOR_DTRACE_LIB
794%endif
795%ifndef VBOX_FOR_DTRACE_LIB
796%endif
797%ifndef VBOX_FOR_DTRACE_LIB
798%endif
799%ifndef VBOX_FOR_DTRACE_LIB
800%endif
801%ifndef VBOX_FOR_DTRACE_LIB
802%endif
803%ifndef VBOX_FOR_DTRACE_LIB
804%endif
805%ifndef VBOX_FOR_DTRACE_LIB
806%endif
807%ifndef VBOX_FOR_DTRACE_LIB
808%endif
809%ifndef VBOX_FOR_DTRACE_LIB
810%endif
811%define XSAVE_C_X87_BIT 0
812%define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
813%define XSAVE_C_SSE_BIT 1
814%define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
815%define XSAVE_C_YMM_BIT 2
816%define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
817%define XSAVE_C_BNDREGS_BIT 3
818%define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
819%define XSAVE_C_BNDCSR_BIT 4
820%define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
821%define XSAVE_C_OPMASK_BIT 5
822%define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
823%define XSAVE_C_ZMM_HI256_BIT 6
824%define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
825%define XSAVE_C_ZMM_16HI_BIT 7
826%define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
827%define XSAVE_C_PKRU_BIT 9
828%define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
829%define XSAVE_C_LWP_BIT 62
830%define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
831%ifndef VBOX_FOR_DTRACE_LIB
832%endif
833%define X86DESCATTR_TYPE 0x0000000f
834%define X86DESCATTR_DT 0x00000010
835%define X86DESCATTR_DPL 0x00000060
836%define X86DESCATTR_DPL_SHIFT 5
837%define X86DESCATTR_P 0x00000080
838%define X86DESCATTR_LIMIT_HIGH 0x00000f00
839%define X86DESCATTR_AVL 0x00001000
840%define X86DESCATTR_L 0x00002000
841%define X86DESCATTR_D 0x00004000
842%define X86DESCATTR_G 0x00008000
843%define X86DESCATTR_UNUSABLE 0x00010000
844%ifndef VBOX_FOR_DTRACE_LIB
845%endif
846%ifndef VBOX_FOR_DTRACE_LIB
847%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
848%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
849%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
850%define X86DESCGENERIC_BIT_OFF_TYPE (40)
851%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
852%define X86DESCGENERIC_BIT_OFF_DPL (45)
853%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
854%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
855%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
856%define X86DESCGENERIC_BIT_OFF_LONG (53)
857%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
858%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
859%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
860%define X86LAR_F_TYPE 0x0f00
861%define X86LAR_F_DT 0x1000
862%define X86LAR_F_DPL 0x6000
863%define X86LAR_F_DPL_SHIFT 13
864%define X86LAR_F_P 0x8000
865%define X86LAR_F_AVL 0x00100000
866%define X86LAR_F_L 0x00200000
867%define X86LAR_F_D 0x00400000
868%define X86LAR_F_G 0x00800000
869%endif
870%ifndef VBOX_FOR_DTRACE_LIB
871%endif
872%ifndef VBOX_FOR_DTRACE_LIB
873%endif
874%ifndef VBOX_FOR_DTRACE_LIB
875%endif
876%ifndef VBOX_FOR_DTRACE_LIB
877%endif
878%ifndef VBOX_FOR_DTRACE_LIB
879%endif
880%if HC_ARCH_BITS == 64
881%else
882%endif
883%if HC_ARCH_BITS == 64
884%else
885%endif
886%if HC_ARCH_BITS == 64
887%else
888%endif
889%define X86_SEL_TYPE_CODE 8
890%define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
891%define X86_SEL_TYPE_ACCESSED 1
892%define X86_SEL_TYPE_DOWN 4
893%define X86_SEL_TYPE_CONF 4
894%define X86_SEL_TYPE_WRITE 2
895%define X86_SEL_TYPE_READ 2
896%define X86_SEL_TYPE_READ_BIT 1
897%define X86_SEL_TYPE_RO 0
898%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
899%define X86_SEL_TYPE_RW 2
900%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
901%define X86_SEL_TYPE_RO_DOWN 4
902%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
903%define X86_SEL_TYPE_RW_DOWN 6
904%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
905%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
906%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
907%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
908%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
909%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
910%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
911%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
912%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
913%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
914%define X86_SEL_TYPE_SYS_UNDEFINED 0
915%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
916%define X86_SEL_TYPE_SYS_LDT 2
917%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
918%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
919%define X86_SEL_TYPE_SYS_TASK_GATE 5
920%define X86_SEL_TYPE_SYS_286_INT_GATE 6
921%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
922%define X86_SEL_TYPE_SYS_UNDEFINED2 8
923%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
924%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
925%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
926%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
927%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
928%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
929%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
930%define AMD64_SEL_TYPE_SYS_LDT 2
931%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
932%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
933%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
934%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
935%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
936%define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
937%define X86_DESC_S RT_BIT_32(12)
938%define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
939%define X86_DESC_P RT_BIT_32(15)
940%define X86_DESC_AVL RT_BIT_32(20)
941%define X86_DESC_DB RT_BIT_32(22)
942%define X86_DESC_G RT_BIT_32(23)
943%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
944%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
945%ifndef VBOX_FOR_DTRACE_LIB
946%endif
947%ifndef VBOX_FOR_DTRACE_LIB
948%endif
949%ifndef VBOX_FOR_DTRACE_LIB
950%endif
951%define X86_SEL_SHIFT 3
952%define X86_SEL_MASK 0xfff8
953%define X86_SEL_MASK_OFF_RPL 0xfffc
954%define X86_SEL_LDT 0x0004
955%define X86_SEL_RPL 0x0003
956%define X86_SEL_RPL_LDT 0x0007
957%define X86_XCPT_LAST 0x1f
958%define X86_TRAP_ERR_EXTERNAL 1
959%define X86_TRAP_ERR_IDT 2
960%define X86_TRAP_ERR_TI 4
961%define X86_TRAP_ERR_SEL_MASK 0xfff8
962%define X86_TRAP_ERR_SEL_SHIFT 3
963%define X86_TRAP_PF_P RT_BIT_32(0)
964%define X86_TRAP_PF_RW RT_BIT_32(1)
965%define X86_TRAP_PF_US RT_BIT_32(2)
966%define X86_TRAP_PF_RSVD RT_BIT_32(3)
967%define X86_TRAP_PF_ID RT_BIT_32(4)
968%define X86_TRAP_PF_PK RT_BIT_32(5)
969%ifndef VBOX_FOR_DTRACE_LIB
970%else
971%endif
972%ifndef VBOX_FOR_DTRACE_LIB
973%else
974%endif
975%define X86_MODRM_RM_MASK 0x07
976%define X86_MODRM_REG_MASK 0x38
977%define X86_MODRM_REG_SMASK 0x07
978%define X86_MODRM_REG_SHIFT 3
979%define X86_MODRM_MOD_MASK 0xc0
980%define X86_MODRM_MOD_SMASK 0x03
981%define X86_MODRM_MOD_SHIFT 6
982%ifndef VBOX_FOR_DTRACE_LIB
983 %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
984%endif
985%define X86_SIB_BASE_MASK 0x07
986%define X86_SIB_INDEX_MASK 0x38
987%define X86_SIB_INDEX_SMASK 0x07
988%define X86_SIB_INDEX_SHIFT 3
989%define X86_SIB_SCALE_MASK 0xc0
990%define X86_SIB_SCALE_SMASK 0x03
991%define X86_SIB_SCALE_SHIFT 6
992%ifndef VBOX_FOR_DTRACE_LIB
993%endif
994%define X86_GREG_xAX 0
995%define X86_GREG_xCX 1
996%define X86_GREG_xDX 2
997%define X86_GREG_xBX 3
998%define X86_GREG_xSP 4
999%define X86_GREG_xBP 5
1000%define X86_GREG_xSI 6
1001%define X86_GREG_xDI 7
1002%define X86_GREG_x8 8
1003%define X86_GREG_x9 9
1004%define X86_GREG_x10 10
1005%define X86_GREG_x11 11
1006%define X86_GREG_x12 12
1007%define X86_GREG_x13 13
1008%define X86_GREG_x14 14
1009%define X86_GREG_x15 15
1010%define X86_SREG_ES 0
1011%define X86_SREG_CS 1
1012%define X86_SREG_SS 2
1013%define X86_SREG_DS 3
1014%define X86_SREG_FS 4
1015%define X86_SREG_GS 5
1016%define X86_SREG_COUNT 6
1017%define X86_OP_PRF_CS 0x2e
1018%define X86_OP_PRF_SS 0x36
1019%define X86_OP_PRF_DS 0x3e
1020%define X86_OP_PRF_ES 0x26
1021%define X86_OP_PRF_FS 0x64
1022%define X86_OP_PRF_GS 0x65
1023%define X86_OP_PRF_SIZE_OP 0x66
1024%define X86_OP_PRF_SIZE_ADDR 0x67
1025%define X86_OP_PRF_LOCK 0xf0
1026%define X86_OP_PRF_REPZ 0xf3
1027%define X86_OP_PRF_REPNZ 0xf2
1028%define X86_OP_REX_B 0x41
1029%define X86_OP_REX_X 0x42
1030%define X86_OP_REX_R 0x44
1031%define X86_OP_REX_W 0x48
1032%endif
1033%include "iprt/x86extra.mac"
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