| 1 | /*
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| 2 | * Copyright (C) 2013 Red Hat
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| 3 | * Author: Rob Clark <[email protected]>
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| 4 | *
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 6 | * copy of this software and associated documentation files (the "Software"),
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| 7 | * to deal in the Software without restriction, including without limitation
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the
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| 10 | * Software is furnished to do so, subject to the following conditions:
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| 11 | *
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| 12 | * The above copyright notice and this permission notice (including the next
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| 13 | * paragraph) shall be included in all copies or substantial portions of the
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| 14 | * Software.
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| 15 | *
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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| 22 | * SOFTWARE.
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| 23 | */
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| 24 |
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| 25 | #ifndef __MSM_DRM_H__
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| 26 | #define __MSM_DRM_H__
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| 27 |
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| 28 | #include "drm.h"
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| 29 |
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| 30 | #if defined(__cplusplus)
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| 31 | extern "C" {
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| 32 | #endif
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| 33 |
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| 34 | /* Please note that modifications to all structs defined here are
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| 35 | * subject to backwards-compatibility constraints:
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| 36 | * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
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| 37 | * user/kernel compatibility
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| 38 | * 2) Keep fields aligned to their size
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| 39 | * 3) Because of how drm_ioctl() works, we can add new fields at
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| 40 | * the end of an ioctl if some care is taken: drm_ioctl() will
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| 41 | * zero out the new fields at the tail of the ioctl, so a zero
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| 42 | * value should have a backwards compatible meaning. And for
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| 43 | * output params, userspace won't see the newly added output
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| 44 | * fields.. so that has to be somehow ok.
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| 45 | */
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| 46 |
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| 47 | #define MSM_PIPE_NONE 0x00
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| 48 | #define MSM_PIPE_2D0 0x01
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| 49 | #define MSM_PIPE_2D1 0x02
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| 50 | #define MSM_PIPE_3D0 0x10
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| 51 |
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| 52 | /* The pipe-id just uses the lower bits, so can be OR'd with flags in
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| 53 | * the upper 16 bits (which could be extended further, if needed, maybe
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| 54 | * we extend/overload the pipe-id some day to deal with multiple rings,
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| 55 | * but even then I don't think we need the full lower 16 bits).
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| 56 | */
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| 57 | #define MSM_PIPE_ID_MASK 0xffff
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| 58 | #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
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| 59 | #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
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| 60 |
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| 61 | /* timeouts are specified in clock-monotonic absolute times (to simplify
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| 62 | * restarting interrupted ioctls). The following struct is logically the
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| 63 | * same as 'struct timespec' but 32/64b ABI safe.
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| 64 | */
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| 65 | struct drm_msm_timespec {
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| 66 | __s64 tv_sec; /* seconds */
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| 67 | __s64 tv_nsec; /* nanoseconds */
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| 68 | };
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| 69 |
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| 70 | #define MSM_PARAM_GPU_ID 0x01
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| 71 | #define MSM_PARAM_GMEM_SIZE 0x02
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| 72 | #define MSM_PARAM_CHIP_ID 0x03
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| 73 | #define MSM_PARAM_MAX_FREQ 0x04
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| 74 | #define MSM_PARAM_TIMESTAMP 0x05
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| 75 | #define MSM_PARAM_GMEM_BASE 0x06
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| 76 | #define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */
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| 77 | #define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */
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| 78 | #define MSM_PARAM_FAULTS 0x09
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| 79 | #define MSM_PARAM_SUSPENDS 0x0a
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| 80 |
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| 81 | /* For backwards compat. The original support for preemption was based on
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| 82 | * a single ring per priority level so # of priority levels equals the #
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| 83 | * of rings. With drm/scheduler providing additional levels of priority,
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| 84 | * the number of priorities is greater than the # of rings. The param is
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| 85 | * renamed to better reflect this.
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| 86 | */
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| 87 | #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
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| 88 |
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| 89 | struct drm_msm_param {
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| 90 | __u32 pipe; /* in, MSM_PIPE_x */
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| 91 | __u32 param; /* in, MSM_PARAM_x */
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| 92 | __u64 value; /* out (get_param) or in (set_param) */
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| 93 | };
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| 94 |
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| 95 | /*
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| 96 | * GEM buffers:
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| 97 | */
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| 98 |
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| 99 | #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
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| 100 | #define MSM_BO_GPU_READONLY 0x00000002
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| 101 | #define MSM_BO_CACHE_MASK 0x000f0000
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| 102 | /* cache modes */
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| 103 | #define MSM_BO_CACHED 0x00010000
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| 104 | #define MSM_BO_WC 0x00020000
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| 105 | #define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
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| 106 | #define MSM_BO_CACHED_COHERENT 0x080000
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| 107 |
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| 108 | #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
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| 109 | MSM_BO_GPU_READONLY | \
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| 110 | MSM_BO_CACHE_MASK)
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| 111 |
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| 112 | struct drm_msm_gem_new {
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| 113 | __u64 size; /* in */
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| 114 | __u32 flags; /* in, mask of MSM_BO_x */
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| 115 | __u32 handle; /* out */
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| 116 | };
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| 117 |
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| 118 | /* Get or set GEM buffer info. The requested value can be passed
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| 119 | * directly in 'value', or for data larger than 64b 'value' is a
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| 120 | * pointer to userspace buffer, with 'len' specifying the number of
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| 121 | * bytes copied into that buffer. For info returned by pointer,
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| 122 | * calling the GEM_INFO ioctl with null 'value' will return the
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| 123 | * required buffer size in 'len'
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| 124 | */
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| 125 | #define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
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| 126 | #define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
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| 127 | #define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
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| 128 | #define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
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| 129 |
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| 130 | struct drm_msm_gem_info {
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| 131 | __u32 handle; /* in */
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| 132 | __u32 info; /* in - one of MSM_INFO_* */
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| 133 | __u64 value; /* in or out */
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| 134 | __u32 len; /* in or out */
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| 135 | __u32 pad;
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| 136 | };
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| 137 |
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| 138 | #define MSM_PREP_READ 0x01
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| 139 | #define MSM_PREP_WRITE 0x02
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| 140 | #define MSM_PREP_NOSYNC 0x04
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| 141 |
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| 142 | #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
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| 143 |
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| 144 | struct drm_msm_gem_cpu_prep {
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| 145 | __u32 handle; /* in */
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| 146 | __u32 op; /* in, mask of MSM_PREP_x */
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| 147 | struct drm_msm_timespec timeout; /* in */
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| 148 | };
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| 149 |
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| 150 | struct drm_msm_gem_cpu_fini {
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| 151 | __u32 handle; /* in */
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| 152 | };
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| 153 |
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| 154 | /*
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| 155 | * Cmdstream Submission:
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| 156 | */
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| 157 |
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| 158 | /* The value written into the cmdstream is logically:
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| 159 | *
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| 160 | * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
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| 161 | *
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| 162 | * When we have GPU's w/ >32bit ptrs, it should be possible to deal
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| 163 | * with this by emit'ing two reloc entries with appropriate shift
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| 164 | * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
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| 165 | *
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| 166 | * NOTE that reloc's must be sorted by order of increasing submit_offset,
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| 167 | * otherwise EINVAL.
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| 168 | */
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| 169 | struct drm_msm_gem_submit_reloc {
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| 170 | __u32 submit_offset; /* in, offset from submit_bo */
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| 171 | __u32 or; /* in, value OR'd with result */
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| 172 | __s32 shift; /* in, amount of left shift (can be negative) */
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| 173 | __u32 reloc_idx; /* in, index of reloc_bo buffer */
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| 174 | __u64 reloc_offset; /* in, offset from start of reloc_bo */
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| 175 | };
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| 176 |
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| 177 | /* submit-types:
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| 178 | * BUF - this cmd buffer is executed normally.
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| 179 | * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
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| 180 | * processed normally, but the kernel does not setup an IB to
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| 181 | * this buffer in the first-level ringbuffer
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| 182 | * CTX_RESTORE_BUF - only executed if there has been a GPU context
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| 183 | * switch since the last SUBMIT ioctl
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| 184 | */
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| 185 | #define MSM_SUBMIT_CMD_BUF 0x0001
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| 186 | #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
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| 187 | #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
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| 188 | struct drm_msm_gem_submit_cmd {
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| 189 | __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
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| 190 | __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
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| 191 | __u32 submit_offset; /* in, offset into submit_bo */
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| 192 | __u32 size; /* in, cmdstream size */
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| 193 | __u32 pad;
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| 194 | __u32 nr_relocs; /* in, number of submit_reloc's */
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| 195 | __u64 relocs; /* in, ptr to array of submit_reloc's */
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| 196 | };
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| 197 |
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| 198 | /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
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| 199 | * cmdstream buffer(s) themselves or reloc entries) has one (and only
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| 200 | * one) entry in the submit->bos[] table.
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| 201 | *
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| 202 | * As a optimization, the current buffer (gpu virtual address) can be
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| 203 | * passed back through the 'presumed' field. If on a subsequent reloc,
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| 204 | * userspace passes back a 'presumed' address that is still valid,
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| 205 | * then patching the cmdstream for this entry is skipped. This can
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| 206 | * avoid kernel needing to map/access the cmdstream bo in the common
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| 207 | * case.
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| 208 | */
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| 209 | #define MSM_SUBMIT_BO_READ 0x0001
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| 210 | #define MSM_SUBMIT_BO_WRITE 0x0002
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| 211 | #define MSM_SUBMIT_BO_DUMP 0x0004
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| 212 |
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| 213 | #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
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| 214 | MSM_SUBMIT_BO_WRITE | \
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| 215 | MSM_SUBMIT_BO_DUMP)
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| 216 |
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| 217 | struct drm_msm_gem_submit_bo {
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| 218 | __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
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| 219 | __u32 handle; /* in, GEM handle */
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| 220 | __u64 presumed; /* in/out, presumed buffer address */
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| 221 | };
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| 222 |
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| 223 | /* Valid submit ioctl flags: */
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| 224 | #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
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| 225 | #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
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| 226 | #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
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| 227 | #define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
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| 228 | #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
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| 229 | #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
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| 230 | #define MSM_SUBMIT_FLAGS ( \
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| 231 | MSM_SUBMIT_NO_IMPLICIT | \
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| 232 | MSM_SUBMIT_FENCE_FD_IN | \
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| 233 | MSM_SUBMIT_FENCE_FD_OUT | \
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| 234 | MSM_SUBMIT_SUDO | \
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| 235 | MSM_SUBMIT_SYNCOBJ_IN | \
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| 236 | MSM_SUBMIT_SYNCOBJ_OUT | \
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| 237 | 0)
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| 238 |
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| 239 | #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
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| 240 | #define MSM_SUBMIT_SYNCOBJ_FLAGS ( \
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| 241 | MSM_SUBMIT_SYNCOBJ_RESET | \
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| 242 | 0)
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| 243 |
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| 244 | struct drm_msm_gem_submit_syncobj {
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| 245 | __u32 handle; /* in, syncobj handle. */
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| 246 | __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
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| 247 | __u64 point; /* in, timepoint for timeline syncobjs. */
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| 248 | };
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| 249 |
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| 250 | /* Each cmdstream submit consists of a table of buffers involved, and
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| 251 | * one or more cmdstream buffers. This allows for conditional execution
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| 252 | * (context-restore), and IB buffers needed for per tile/bin draw cmds.
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| 253 | */
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| 254 | struct drm_msm_gem_submit {
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| 255 | __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
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| 256 | __u32 fence; /* out */
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| 257 | __u32 nr_bos; /* in, number of submit_bo's */
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| 258 | __u32 nr_cmds; /* in, number of submit_cmd's */
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| 259 | __u64 bos; /* in, ptr to array of submit_bo's */
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| 260 | __u64 cmds; /* in, ptr to array of submit_cmd's */
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| 261 | __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
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| 262 | __u32 queueid; /* in, submitqueue id */
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| 263 | __u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
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| 264 | __u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
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| 265 | __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
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| 266 | __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
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| 267 | __u32 syncobj_stride; /* in, stride of syncobj arrays. */
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| 268 | __u32 pad; /*in, reserved for future use, always 0. */
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| 269 |
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| 270 | };
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| 271 |
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| 272 | /* The normal way to synchronize with the GPU is just to CPU_PREP on
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| 273 | * a buffer if you need to access it from the CPU (other cmdstream
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| 274 | * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
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| 275 | * handle the required synchronization under the hood). This ioctl
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| 276 | * mainly just exists as a way to implement the gallium pipe_fence
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| 277 | * APIs without requiring a dummy bo to synchronize on.
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| 278 | */
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| 279 | struct drm_msm_wait_fence {
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| 280 | __u32 fence; /* in */
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| 281 | __u32 pad;
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| 282 | struct drm_msm_timespec timeout; /* in */
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| 283 | __u32 queueid; /* in, submitqueue id */
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| 284 | };
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| 285 |
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| 286 | /* madvise provides a way to tell the kernel in case a buffers contents
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| 287 | * can be discarded under memory pressure, which is useful for userspace
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| 288 | * bo cache where we want to optimistically hold on to buffer allocate
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| 289 | * and potential mmap, but allow the pages to be discarded under memory
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| 290 | * pressure.
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| 291 | *
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| 292 | * Typical usage would involve madvise(DONTNEED) when buffer enters BO
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| 293 | * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
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| 294 | * In the WILLNEED case, 'retained' indicates to userspace whether the
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| 295 | * backing pages still exist.
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| 296 | */
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| 297 | #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
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| 298 | #define MSM_MADV_DONTNEED 1 /* backing pages not needed */
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| 299 | #define __MSM_MADV_PURGED 2 /* internal state */
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| 300 |
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| 301 | struct drm_msm_gem_madvise {
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| 302 | __u32 handle; /* in, GEM handle */
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| 303 | __u32 madv; /* in, MSM_MADV_x */
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| 304 | __u32 retained; /* out, whether backing store still exists */
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| 305 | };
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| 306 |
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| 307 | /*
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| 308 | * Draw queues allow the user to set specific submission parameter. Command
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| 309 | * submissions specify a specific submitqueue to use. ID 0 is reserved for
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| 310 | * backwards compatibility as a "default" submitqueue
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| 311 | */
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| 312 |
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| 313 | #define MSM_SUBMITQUEUE_FLAGS (0)
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| 314 |
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| 315 | /*
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| 316 | * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
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| 317 | * a lower numeric value is higher priority.
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| 318 | */
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| 319 | struct drm_msm_submitqueue {
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| 320 | __u32 flags; /* in, MSM_SUBMITQUEUE_x */
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| 321 | __u32 prio; /* in, Priority level */
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| 322 | __u32 id; /* out, identifier */
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| 323 | };
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| 324 |
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| 325 | #define MSM_SUBMITQUEUE_PARAM_FAULTS 0
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| 326 |
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| 327 | struct drm_msm_submitqueue_query {
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| 328 | __u64 data;
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| 329 | __u32 id;
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| 330 | __u32 param;
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| 331 | __u32 len;
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| 332 | __u32 pad;
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| 333 | };
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| 334 |
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| 335 | #define DRM_MSM_GET_PARAM 0x00
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| 336 | /* placeholder:
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| 337 | #define DRM_MSM_SET_PARAM 0x01
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| 338 | */
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| 339 | #define DRM_MSM_GEM_NEW 0x02
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| 340 | #define DRM_MSM_GEM_INFO 0x03
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| 341 | #define DRM_MSM_GEM_CPU_PREP 0x04
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| 342 | #define DRM_MSM_GEM_CPU_FINI 0x05
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| 343 | #define DRM_MSM_GEM_SUBMIT 0x06
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| 344 | #define DRM_MSM_WAIT_FENCE 0x07
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| 345 | #define DRM_MSM_GEM_MADVISE 0x08
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| 346 | /* placeholder:
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| 347 | #define DRM_MSM_GEM_SVM_NEW 0x09
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| 348 | */
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| 349 | #define DRM_MSM_SUBMITQUEUE_NEW 0x0A
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| 350 | #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
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| 351 | #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
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| 352 |
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| 353 | #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
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| 354 | #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
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| 355 | #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
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| 356 | #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
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| 357 | #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
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| 358 | #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
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| 359 | #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
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| 360 | #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
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| 361 | #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
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| 362 | #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
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| 363 | #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
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| 364 |
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| 365 | #if defined(__cplusplus)
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| 366 | }
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| 367 | #endif
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| 368 |
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| 369 | #endif /* __MSM_DRM_H__ */
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