| 1 | /*
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| 2 | * Copyright © 2014-2018 Broadcom
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice (including the next
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| 12 | * paragraph) shall be included in all copies or substantial portions of the
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| 13 | * Software.
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| 14 | *
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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| 21 | * IN THE SOFTWARE.
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| 22 | */
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| 23 |
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| 24 | #ifndef _V3D_DRM_H_
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| 25 | #define _V3D_DRM_H_
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| 26 |
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| 27 | #include "drm.h"
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| 28 |
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| 29 | #if defined(__cplusplus)
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| 30 | extern "C" {
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| 31 | #endif
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| 32 |
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| 33 | #define DRM_V3D_SUBMIT_CL 0x00
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| 34 | #define DRM_V3D_WAIT_BO 0x01
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| 35 | #define DRM_V3D_CREATE_BO 0x02
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| 36 | #define DRM_V3D_MMAP_BO 0x03
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| 37 | #define DRM_V3D_GET_PARAM 0x04
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| 38 | #define DRM_V3D_GET_BO_OFFSET 0x05
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| 39 | #define DRM_V3D_SUBMIT_TFU 0x06
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| 40 | #define DRM_V3D_SUBMIT_CSD 0x07
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| 41 | #define DRM_V3D_PERFMON_CREATE 0x08
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| 42 | #define DRM_V3D_PERFMON_DESTROY 0x09
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| 43 | #define DRM_V3D_PERFMON_GET_VALUES 0x0a
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| 44 |
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| 45 | #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
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| 46 | #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
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| 47 | #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
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| 48 | #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
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| 49 | #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
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| 50 | #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
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| 51 | #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
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| 52 | #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
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| 53 | #define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
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| 54 | struct drm_v3d_perfmon_create)
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| 55 | #define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
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| 56 | struct drm_v3d_perfmon_destroy)
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| 57 | #define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
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| 58 | struct drm_v3d_perfmon_get_values)
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| 59 |
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| 60 | #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
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| 61 |
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| 62 | /**
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| 63 | * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
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| 64 | * engine.
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| 65 | *
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| 66 | * This asks the kernel to have the GPU execute an optional binner
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| 67 | * command list, and a render command list.
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| 68 | *
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| 69 | * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
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| 70 | * each CL executes. The VCD cache should be flushed (if necessary)
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| 71 | * by the submitted CLs. The TLB writes are guaranteed to have been
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| 72 | * flushed by the time the render done IRQ happens, which is the
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| 73 | * trigger for out_sync. Any dirtying of cachelines by the job (only
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| 74 | * possible using TMU writes) must be flushed by the caller using the
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| 75 | * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
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| 76 | */
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| 77 | struct drm_v3d_submit_cl {
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| 78 | /* Pointer to the binner command list.
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| 79 | *
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| 80 | * This is the first set of commands executed, which runs the
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| 81 | * coordinate shader to determine where primitives land on the screen,
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| 82 | * then writes out the state updates and draw calls necessary per tile
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| 83 | * to the tile allocation BO.
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| 84 | *
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| 85 | * This BCL will block on any previous BCL submitted on the
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| 86 | * same FD, but not on any RCL or BCLs submitted by other
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| 87 | * clients -- that is left up to the submitter to control
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| 88 | * using in_sync_bcl if necessary.
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| 89 | */
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| 90 | __u32 bcl_start;
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| 91 |
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| 92 | /** End address of the BCL (first byte after the BCL) */
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| 93 | __u32 bcl_end;
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| 94 |
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| 95 | /* Offset of the render command list.
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| 96 | *
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| 97 | * This is the second set of commands executed, which will either
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| 98 | * execute the tiles that have been set up by the BCL, or a fixed set
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| 99 | * of tiles (in the case of RCL-only blits).
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| 100 | *
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| 101 | * This RCL will block on this submit's BCL, and any previous
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| 102 | * RCL submitted on the same FD, but not on any RCL or BCLs
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| 103 | * submitted by other clients -- that is left up to the
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| 104 | * submitter to control using in_sync_rcl if necessary.
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| 105 | */
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| 106 | __u32 rcl_start;
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| 107 |
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| 108 | /** End address of the RCL (first byte after the RCL) */
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| 109 | __u32 rcl_end;
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| 110 |
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| 111 | /** An optional sync object to wait on before starting the BCL. */
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| 112 | __u32 in_sync_bcl;
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| 113 | /** An optional sync object to wait on before starting the RCL. */
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| 114 | __u32 in_sync_rcl;
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| 115 | /** An optional sync object to place the completion fence in. */
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| 116 | __u32 out_sync;
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| 117 |
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| 118 | /* Offset of the tile alloc memory
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| 119 | *
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| 120 | * This is optional on V3D 3.3 (where the CL can set the value) but
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| 121 | * required on V3D 4.1.
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| 122 | */
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| 123 | __u32 qma;
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| 124 |
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| 125 | /** Size of the tile alloc memory. */
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| 126 | __u32 qms;
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| 127 |
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| 128 | /** Offset of the tile state data array. */
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| 129 | __u32 qts;
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| 130 |
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| 131 | /* Pointer to a u32 array of the BOs that are referenced by the job.
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| 132 | */
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| 133 | __u64 bo_handles;
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| 134 |
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| 135 | /* Number of BO handles passed in (size is that times 4). */
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| 136 | __u32 bo_handle_count;
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| 137 |
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| 138 | __u32 flags;
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| 139 |
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| 140 | /* ID of the perfmon to attach to this job. 0 means no perfmon. */
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| 141 | __u32 perfmon_id;
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| 142 |
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| 143 | __u32 pad;
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| 144 | };
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| 145 |
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| 146 | /**
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| 147 | * struct drm_v3d_wait_bo - ioctl argument for waiting for
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| 148 | * completion of the last DRM_V3D_SUBMIT_CL on a BO.
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| 149 | *
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| 150 | * This is useful for cases where multiple processes might be
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| 151 | * rendering to a BO and you want to wait for all rendering to be
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| 152 | * completed.
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| 153 | */
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| 154 | struct drm_v3d_wait_bo {
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| 155 | __u32 handle;
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| 156 | __u32 pad;
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| 157 | __u64 timeout_ns;
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| 158 | };
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| 159 |
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| 160 | /**
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| 161 | * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
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| 162 | *
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| 163 | * There are currently no values for the flags argument, but it may be
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| 164 | * used in a future extension.
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| 165 | */
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| 166 | struct drm_v3d_create_bo {
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| 167 | __u32 size;
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| 168 | __u32 flags;
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| 169 | /** Returned GEM handle for the BO. */
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| 170 | __u32 handle;
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| 171 | /**
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| 172 | * Returned offset for the BO in the V3D address space. This offset
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| 173 | * is private to the DRM fd and is valid for the lifetime of the GEM
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| 174 | * handle.
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| 175 | *
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| 176 | * This offset value will always be nonzero, since various HW
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| 177 | * units treat 0 specially.
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| 178 | */
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| 179 | __u32 offset;
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| 180 | };
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| 181 |
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| 182 | /**
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| 183 | * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
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| 184 | *
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| 185 | * This doesn't actually perform an mmap. Instead, it returns the
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| 186 | * offset you need to use in an mmap on the DRM device node. This
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| 187 | * means that tools like valgrind end up knowing about the mapped
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| 188 | * memory.
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| 189 | *
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| 190 | * There are currently no values for the flags argument, but it may be
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| 191 | * used in a future extension.
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| 192 | */
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| 193 | struct drm_v3d_mmap_bo {
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| 194 | /** Handle for the object being mapped. */
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| 195 | __u32 handle;
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| 196 | __u32 flags;
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| 197 | /** offset into the drm node to use for subsequent mmap call. */
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| 198 | __u64 offset;
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| 199 | };
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| 200 |
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| 201 | enum drm_v3d_param {
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| 202 | DRM_V3D_PARAM_V3D_UIFCFG,
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| 203 | DRM_V3D_PARAM_V3D_HUB_IDENT1,
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| 204 | DRM_V3D_PARAM_V3D_HUB_IDENT2,
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| 205 | DRM_V3D_PARAM_V3D_HUB_IDENT3,
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| 206 | DRM_V3D_PARAM_V3D_CORE0_IDENT0,
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| 207 | DRM_V3D_PARAM_V3D_CORE0_IDENT1,
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| 208 | DRM_V3D_PARAM_V3D_CORE0_IDENT2,
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| 209 | DRM_V3D_PARAM_SUPPORTS_TFU,
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| 210 | DRM_V3D_PARAM_SUPPORTS_CSD,
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| 211 | DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
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| 212 | DRM_V3D_PARAM_SUPPORTS_PERFMON,
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| 213 | };
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| 214 |
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| 215 | struct drm_v3d_get_param {
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| 216 | __u32 param;
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| 217 | __u32 pad;
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| 218 | __u64 value;
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| 219 | };
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| 220 |
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| 221 | /**
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| 222 | * Returns the offset for the BO in the V3D address space for this DRM fd.
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| 223 | * This is the same value returned by drm_v3d_create_bo, if that was called
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| 224 | * from this DRM fd.
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| 225 | */
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| 226 | struct drm_v3d_get_bo_offset {
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| 227 | __u32 handle;
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| 228 | __u32 offset;
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| 229 | };
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| 230 |
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| 231 | struct drm_v3d_submit_tfu {
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| 232 | __u32 icfg;
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| 233 | __u32 iia;
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| 234 | __u32 iis;
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| 235 | __u32 ica;
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| 236 | __u32 iua;
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| 237 | __u32 ioa;
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| 238 | __u32 ios;
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| 239 | __u32 coef[4];
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| 240 | /* First handle is the output BO, following are other inputs.
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| 241 | * 0 for unused.
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| 242 | */
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| 243 | __u32 bo_handles[4];
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| 244 | /* sync object to block on before running the TFU job. Each TFU
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| 245 | * job will execute in the order submitted to its FD. Synchronization
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| 246 | * against rendering jobs requires using sync objects.
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| 247 | */
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| 248 | __u32 in_sync;
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| 249 | /* Sync object to signal when the TFU job is done. */
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| 250 | __u32 out_sync;
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| 251 | };
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| 252 |
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| 253 | /* Submits a compute shader for dispatch. This job will block on any
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| 254 | * previous compute shaders submitted on this fd, and any other
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| 255 | * synchronization must be performed with in_sync/out_sync.
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| 256 | */
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| 257 | struct drm_v3d_submit_csd {
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| 258 | __u32 cfg[7];
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| 259 | __u32 coef[4];
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| 260 |
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| 261 | /* Pointer to a u32 array of the BOs that are referenced by the job.
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| 262 | */
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| 263 | __u64 bo_handles;
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| 264 |
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| 265 | /* Number of BO handles passed in (size is that times 4). */
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| 266 | __u32 bo_handle_count;
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| 267 |
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| 268 | /* sync object to block on before running the CSD job. Each
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| 269 | * CSD job will execute in the order submitted to its FD.
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| 270 | * Synchronization against rendering/TFU jobs or CSD from
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| 271 | * other fds requires using sync objects.
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| 272 | */
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| 273 | __u32 in_sync;
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| 274 | /* Sync object to signal when the CSD job is done. */
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| 275 | __u32 out_sync;
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| 276 |
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| 277 | /* ID of the perfmon to attach to this job. 0 means no perfmon. */
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| 278 | __u32 perfmon_id;
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| 279 | };
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| 280 |
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| 281 | enum {
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| 282 | V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
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| 283 | V3D_PERFCNT_FEP_VALID_PRIMS,
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| 284 | V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
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| 285 | V3D_PERFCNT_FEP_VALID_QUADS,
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| 286 | V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
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| 287 | V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
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| 288 | V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
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| 289 | V3D_PERFCNT_TLB_QUADS_ZERO_COV,
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| 290 | V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
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| 291 | V3D_PERFCNT_TLB_QUADS_WRITTEN,
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| 292 | V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
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| 293 | V3D_PERFCNT_PTB_PRIM_CLIP,
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| 294 | V3D_PERFCNT_PTB_PRIM_REV,
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| 295 | V3D_PERFCNT_QPU_IDLE_CYCLES,
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| 296 | V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
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| 297 | V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
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| 298 | V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
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| 299 | V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
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| 300 | V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
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| 301 | V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
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| 302 | V3D_PERFCNT_QPU_IC_HIT,
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| 303 | V3D_PERFCNT_QPU_IC_MISS,
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| 304 | V3D_PERFCNT_QPU_UC_HIT,
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| 305 | V3D_PERFCNT_QPU_UC_MISS,
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| 306 | V3D_PERFCNT_TMU_TCACHE_ACCESS,
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| 307 | V3D_PERFCNT_TMU_TCACHE_MISS,
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| 308 | V3D_PERFCNT_VPM_VDW_STALL,
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| 309 | V3D_PERFCNT_VPM_VCD_STALL,
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| 310 | V3D_PERFCNT_BIN_ACTIVE,
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| 311 | V3D_PERFCNT_RDR_ACTIVE,
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| 312 | V3D_PERFCNT_L2T_HITS,
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| 313 | V3D_PERFCNT_L2T_MISSES,
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| 314 | V3D_PERFCNT_CYCLE_COUNT,
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| 315 | V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
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| 316 | V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
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| 317 | V3D_PERFCNT_PTB_PRIMS_BINNED,
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| 318 | V3D_PERFCNT_AXI_WRITES_WATCH_0,
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| 319 | V3D_PERFCNT_AXI_READS_WATCH_0,
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| 320 | V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
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| 321 | V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
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| 322 | V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
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| 323 | V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
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| 324 | V3D_PERFCNT_AXI_WRITES_WATCH_1,
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| 325 | V3D_PERFCNT_AXI_READS_WATCH_1,
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| 326 | V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
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| 327 | V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
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| 328 | V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
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| 329 | V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
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| 330 | V3D_PERFCNT_TLB_PARTIAL_QUADS,
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| 331 | V3D_PERFCNT_TMU_CONFIG_ACCESSES,
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| 332 | V3D_PERFCNT_L2T_NO_ID_STALL,
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| 333 | V3D_PERFCNT_L2T_COM_QUE_STALL,
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| 334 | V3D_PERFCNT_L2T_TMU_WRITES,
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| 335 | V3D_PERFCNT_TMU_ACTIVE_CYCLES,
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| 336 | V3D_PERFCNT_TMU_STALLED_CYCLES,
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| 337 | V3D_PERFCNT_CLE_ACTIVE,
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| 338 | V3D_PERFCNT_L2T_TMU_READS,
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| 339 | V3D_PERFCNT_L2T_CLE_READS,
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| 340 | V3D_PERFCNT_L2T_VCD_READS,
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| 341 | V3D_PERFCNT_L2T_TMUCFG_READS,
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| 342 | V3D_PERFCNT_L2T_SLC0_READS,
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| 343 | V3D_PERFCNT_L2T_SLC1_READS,
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| 344 | V3D_PERFCNT_L2T_SLC2_READS,
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| 345 | V3D_PERFCNT_L2T_TMU_W_MISSES,
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| 346 | V3D_PERFCNT_L2T_TMU_R_MISSES,
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| 347 | V3D_PERFCNT_L2T_CLE_MISSES,
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| 348 | V3D_PERFCNT_L2T_VCD_MISSES,
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| 349 | V3D_PERFCNT_L2T_TMUCFG_MISSES,
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| 350 | V3D_PERFCNT_L2T_SLC0_MISSES,
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| 351 | V3D_PERFCNT_L2T_SLC1_MISSES,
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| 352 | V3D_PERFCNT_L2T_SLC2_MISSES,
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| 353 | V3D_PERFCNT_CORE_MEM_WRITES,
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| 354 | V3D_PERFCNT_L2T_MEM_WRITES,
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| 355 | V3D_PERFCNT_PTB_MEM_WRITES,
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| 356 | V3D_PERFCNT_TLB_MEM_WRITES,
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| 357 | V3D_PERFCNT_CORE_MEM_READS,
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| 358 | V3D_PERFCNT_L2T_MEM_READS,
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| 359 | V3D_PERFCNT_PTB_MEM_READS,
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| 360 | V3D_PERFCNT_PSE_MEM_READS,
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| 361 | V3D_PERFCNT_TLB_MEM_READS,
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| 362 | V3D_PERFCNT_GMP_MEM_READS,
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| 363 | V3D_PERFCNT_PTB_W_MEM_WORDS,
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| 364 | V3D_PERFCNT_TLB_W_MEM_WORDS,
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| 365 | V3D_PERFCNT_PSE_R_MEM_WORDS,
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| 366 | V3D_PERFCNT_TLB_R_MEM_WORDS,
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| 367 | V3D_PERFCNT_TMU_MRU_HITS,
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| 368 | V3D_PERFCNT_COMPUTE_ACTIVE,
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| 369 | V3D_PERFCNT_NUM,
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| 370 | };
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| 371 |
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| 372 | #define DRM_V3D_MAX_PERF_COUNTERS 32
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| 373 |
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| 374 | struct drm_v3d_perfmon_create {
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| 375 | __u32 id;
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| 376 | __u32 ncounters;
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| 377 | __u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
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| 378 | };
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| 379 |
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| 380 | struct drm_v3d_perfmon_destroy {
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| 381 | __u32 id;
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| 382 | };
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| 383 |
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| 384 | /*
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| 385 | * Returns the values of the performance counters tracked by this
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| 386 | * perfmon (as an array of ncounters u64 values).
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| 387 | *
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| 388 | * No implicit synchronization is performed, so the user has to
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| 389 | * guarantee that any jobs using this perfmon have already been
|
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| 390 | * completed (probably by blocking on the seqno returned by the
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| 391 | * last exec that used the perfmon).
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| 392 | */
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| 393 | struct drm_v3d_perfmon_get_values {
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| 394 | __u32 id;
|
|---|
| 395 | __u32 pad;
|
|---|
| 396 | __u64 values_ptr;
|
|---|
| 397 | };
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|---|
| 398 |
|
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| 399 | #if defined(__cplusplus)
|
|---|
| 400 | }
|
|---|
| 401 | #endif
|
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| 402 |
|
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| 403 | #endif /* _V3D_DRM_H_ */
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