drm.h@ 17233

最後變更在這個檔案從17233是 17232,由 vboxsync 提交於 16 年前
Additions/x11/x11include: added header files needed for DRI support in vboxvideo
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1	/**
2	* \file drm.h
3	* Header for the Direct Rendering Manager
4	*
5	* \author Rickard E. (Rik) Faith <[email protected]>
6	*
7	* \par Acknowledgments:
8	* Dec 1999, Richard Henderson <[email protected]>, move to generic \c cmpxchg.
9	*/
10
11	/*
12	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14	* All rights reserved.
15	*
16	* Permission is hereby granted, free of charge, to any person obtaining a
17	* copy of this software and associated documentation files (the "Software"),
18	* to deal in the Software without restriction, including without limitation
19	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
20	* and/or sell copies of the Software, and to permit persons to whom the
21	* Software is furnished to do so, subject to the following conditions:
22	*
23	* The above copyright notice and this permission notice (including the next
24	* paragraph) shall be included in all copies or substantial portions of the
25	* Software.
26	*
27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33	* OTHER DEALINGS IN THE SOFTWARE.
34	*/
35
36	/**
37	* \mainpage
38	*
39	* The Direct Rendering Manager (DRM) is a device-independent kernel-level
40	* device driver that provides support for the XFree86 Direct Rendering
41	* Infrastructure (DRI).
42	*
43	* The DRM supports the Direct Rendering Infrastructure (DRI) in four major
44	* ways:
45	* -# The DRM provides synchronized access to the graphics hardware via
46	* the use of an optimized two-tiered lock.
47	* -# The DRM enforces the DRI security policy for access to the graphics
48	* hardware by only allowing authenticated X11 clients access to
49	* restricted regions of memory.
50	* -# The DRM provides a generic DMA engine, complete with multiple
51	* queues and the ability to detect the need for an OpenGL context
52	* switch.
53	* -# The DRM is extensible via the use of small device-specific modules
54	* that rely extensively on the API exported by the DRM module.
55	*
56	*/
57
58	#ifndef _DRM_H_
59	#define _DRM_H_
60
61	#ifndef __user
62	#define __user
63	#endif
64
65	#ifdef __GNUC__
66	# define DEPRECATED __attribute__ ((deprecated))
67	#else
68	# define DEPRECATED
69	#endif
70
71	#if defined(__linux__)
72	#include <asm/ioctl.h> /* For _IO* macros */
73	#define DRM_IOCTL_NR(n) _IOC_NR(n)
74	#define DRM_IOC_VOID _IOC_NONE
75	#define DRM_IOC_READ _IOC_READ
76	#define DRM_IOC_WRITE _IOC_WRITE
77	#define DRM_IOC_READWRITE _IOC_READ\|_IOC_WRITE
78	#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
79	#elif defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__) \|\| defined(__NetBSD__) \|\| defined(__OpenBSD__) \|\| defined(__DragonFly__)
80	#if (defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
81	/* Prevent name collision when including sys/ioccom.h */
82	#undef ioctl
83	#include <sys/ioccom.h>
84	#define ioctl(a,b,c) xf86ioctl(a,b,c)
85	#else
86	#include <sys/ioccom.h>
87	#endif /* __FreeBSD__ && xf86ioctl */
88	#define DRM_IOCTL_NR(n) ((n) & 0xff)
89	#define DRM_IOC_VOID IOC_VOID
90	#define DRM_IOC_READ IOC_OUT
91	#define DRM_IOC_WRITE IOC_IN
92	#define DRM_IOC_READWRITE IOC_INOUT
93	#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
94	#endif
95
96	#define XFREE86_VERSION(major,minor,patch,snap) \
97	((major << 16) \| (minor << 8) \| patch)
98
99	#ifndef CONFIG_XFREE86_VERSION
100	#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
101	#endif
102
103	#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
104	#define DRM_PROC_DEVICES "/proc/devices"
105	#define DRM_PROC_MISC "/proc/misc"
106	#define DRM_PROC_DRM "/proc/drm"
107	#define DRM_DEV_DRM "/dev/drm"
108	#define DRM_DEV_MODE (S_IRUSR\|S_IWUSR\|S_IRGRP\|S_IWGRP)
109	#define DRM_DEV_UID 0
110	#define DRM_DEV_GID 0
111	#endif
112
113	#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
114	#ifdef __OpenBSD__
115	#define DRM_MAJOR 81
116	#endif
117	#if defined(__linux__) \|\| defined(__NetBSD__)
118	#define DRM_MAJOR 226
119	#endif
120	#define DRM_MAX_MINOR 15
121	#endif
122	#define DRM_NAME "drm" /*< Name in kernel, /dev, and /proc /
123	#define DRM_MIN_ORDER 5 /*< At least 2^5 bytes = 32 bytes /
124	#define DRM_MAX_ORDER 22 /*< Up to 2^22 bytes = 4MB /
125	#define DRM_RAM_PERCENT 10 /*< How much system ram can we lock? /
126
127	#define _DRM_LOCK_HELD 0x80000000U /*< Hardware lock is held /
128	#define _DRM_LOCK_CONT 0x40000000U /*< Hardware lock is contended /
129	#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
130	#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
131	#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD\|_DRM_LOCK_CONT))
132
133	#if defined(__linux__)
134	#if defined(__KERNEL__)
135	typedef __u64 drm_u64_t;
136	#else
137	typedef unsigned long long drm_u64_t;
138	#endif
139
140	typedef unsigned int drm_handle_t;
141	#else
142	#include <sys/types.h>
143	typedef u_int64_t drm_u64_t;
144	typedef unsigned long drm_handle_t; /*< To mapped regions /
145	#endif
146	typedef unsigned int drm_context_t; /*< GLXContext handle /
147	typedef unsigned int drm_drawable_t;
148	typedef unsigned int drm_magic_t; /*< Magic for authentication /
149
150	/**
151	* Cliprect.
152	*
153	* \warning If you change this structure, make sure you change
154	* XF86DRIClipRectRec in the server as well
155	*
156	* \note KW: Actually it's illegal to change either for
157	* backwards-compatibility reasons.
158	*/
159	typedef struct drm_clip_rect {
160	unsigned short x1;
161	unsigned short y1;
162	unsigned short x2;
163	unsigned short y2;
164	} drm_clip_rect_t;
165
166	/**
167	* Drawable information.
168	*/
169	typedef struct drm_drawable_info {
170	unsigned int num_rects;
171	drm_clip_rect_t *rects;
172	} drm_drawable_info_t;
173
174	/**
175	* Texture region,
176	*/
177	typedef struct drm_tex_region {
178	unsigned char next;
179	unsigned char prev;
180	unsigned char in_use;
181	unsigned char padding;
182	unsigned int age;
183	} drm_tex_region_t;
184
185	/**
186	* Hardware lock.
187	*
188	* The lock structure is a simple cache-line aligned integer. To avoid
189	* processor bus contention on a multiprocessor system, there should not be any
190	* other data stored in the same cache line.
191	*/
192	typedef struct drm_hw_lock {
193	__volatile__ unsigned int lock; /*< lock variable /
194	char padding[60]; /*< Pad to cache line /
195	} drm_hw_lock_t;
196
197	/* This is beyond ugly, and only works on GCC. However, it allows me to use
198	* drm.h in places (i.e., in the X-server) where I can't use size_t. The real
199	* fix is to use uint32_t instead of size_t, but that fix will break existing
200	* LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That will
201	* eventually happen, though. I chose 'unsigned long' to be the fallback type
202	* because that works on all the platforms I know about. Hopefully, the
203	* real fix will happen before that bites us.
204	*/
205
206	#ifdef __SIZE_TYPE__
207	# define DRM_SIZE_T __SIZE_TYPE__
208	#else
209	# warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
210	# define DRM_SIZE_T unsigned long
211	#endif
212
213	/**
214	* DRM_IOCTL_VERSION ioctl argument type.
215	*
216	* \sa drmGetVersion().
217	*/
218	typedef struct drm_version {
219	int version_major; /*< Major version /
220	int version_minor; /*< Minor version /
221	int version_patchlevel; /*< Patch level /
222	DRM_SIZE_T name_len; /*< Length of name buffer /
223	char __user name; /< Name of driver /
224	DRM_SIZE_T date_len; /*< Length of date buffer /
225	char __user date; /< User-space buffer to hold date /
226	DRM_SIZE_T desc_len; /*< Length of desc buffer /
227	char __user desc; /< User-space buffer to hold desc /
228	} drm_version_t;
229
230	/**
231	* DRM_IOCTL_GET_UNIQUE ioctl argument type.
232	*
233	* \sa drmGetBusid() and drmSetBusId().
234	*/
235	typedef struct drm_unique {
236	DRM_SIZE_T unique_len; /*< Length of unique /
237	char __user unique; /< Unique name for driver instantiation /
238	} drm_unique_t;
239
240	#undef DRM_SIZE_T
241
242	typedef struct drm_list {
243	int count; /*< Length of user-space structures /
244	drm_version_t __user *version;
245	} drm_list_t;
246
247	typedef struct drm_block {
248	int unused;
249	} drm_block_t;
250
251	/**
252	* DRM_IOCTL_CONTROL ioctl argument type.
253	*
254	* \sa drmCtlInstHandler() and drmCtlUninstHandler().
255	*/
256	typedef struct drm_control {
257	enum {
258	DRM_ADD_COMMAND,
259	DRM_RM_COMMAND,
260	DRM_INST_HANDLER,
261	DRM_UNINST_HANDLER
262	} func;
263	int irq;
264	} drm_control_t;
265
266	/**
267	* Type of memory to map.
268	*/
269	typedef enum drm_map_type {
270	_DRM_FRAME_BUFFER = 0, /*< WC (no caching), no core dump /
271	_DRM_REGISTERS = 1, /*< no caching, no core dump /
272	_DRM_SHM = 2, /*< shared, cached /
273	_DRM_AGP = 3, /*< AGP/GART /
274	_DRM_SCATTER_GATHER = 4, /*< Scatter/gather memory for PCI DMA /
275	_DRM_CONSISTENT = 5, /*< Consistent memory for PCI DMA /
276	_DRM_TTM = 6
277	} drm_map_type_t;
278
279	/**
280	* Memory mapping flags.
281	*/
282	typedef enum drm_map_flags {
283	_DRM_RESTRICTED = 0x01, /*< Cannot be mapped to user-virtual /
284	_DRM_READ_ONLY = 0x02,
285	_DRM_LOCKED = 0x04, /*< shared, cached, locked /
286	_DRM_KERNEL = 0x08, /*< kernel requires access /
287	_DRM_WRITE_COMBINING = 0x10, /*< use write-combining if available /
288	_DRM_CONTAINS_LOCK = 0x20, /*< SHM page that contains lock /
289	_DRM_REMOVABLE = 0x40 /*< Removable mapping /
290	} drm_map_flags_t;
291
292	typedef struct drm_ctx_priv_map {
293	unsigned int ctx_id; /*< Context requesting private mapping /
294	void handle; /< Handle of map /
295	} drm_ctx_priv_map_t;
296
297	/**
298	* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
299	* argument type.
300	*
301	* \sa drmAddMap().
302	*/
303	typedef struct drm_map {
304	unsigned long offset; /*< Requested physical address (0 for SAREA)/
305	unsigned long size; /*< Requested physical size (bytes) /
306	drm_map_type_t type; /*< Type of memory to map /
307	drm_map_flags_t flags; /*< Flags /
308	void handle; /< User-space: "Handle" to pass to mmap() /
309	/*< Kernel-space: kernel-virtual address /
310	int mtrr; /*< MTRR slot used /
311	/* Private data */
312	} drm_map_t;
313
314	/**
315	* DRM_IOCTL_GET_CLIENT ioctl argument type.
316	*/
317	typedef struct drm_client {
318	int idx; /*< Which client desired? /
319	int auth; /*< Is client authenticated? /
320	unsigned long pid; /*< Process ID /
321	unsigned long uid; /*< User ID /
322	unsigned long magic; /*< Magic /
323	unsigned long iocs; /*< Ioctl count /
324	} drm_client_t;
325
326	typedef enum {
327	_DRM_STAT_LOCK,
328	_DRM_STAT_OPENS,
329	_DRM_STAT_CLOSES,
330	_DRM_STAT_IOCTLS,
331	_DRM_STAT_LOCKS,
332	_DRM_STAT_UNLOCKS,
333	_DRM_STAT_VALUE, /*< Generic value /
334	_DRM_STAT_BYTE, /*< Generic byte counter (1024bytes/K) /
335	_DRM_STAT_COUNT, /*< Generic non-byte counter (1000/k) /
336
337	_DRM_STAT_IRQ, /*< IRQ /
338	_DRM_STAT_PRIMARY, /*< Primary DMA bytes /
339	_DRM_STAT_SECONDARY, /*< Secondary DMA bytes /
340	_DRM_STAT_DMA, /*< DMA /
341	_DRM_STAT_SPECIAL, /*< Special DMA (e.g., priority or polled) /
342	_DRM_STAT_MISSED /*< Missed DMA opportunity /
343	/* Add to the END of the list */
344	} drm_stat_type_t;
345
346	/**
347	* DRM_IOCTL_GET_STATS ioctl argument type.
348	*/
349	typedef struct drm_stats {
350	unsigned long count;
351	struct {
352	unsigned long value;
353	drm_stat_type_t type;
354	} data[15];
355	} drm_stats_t;
356
357	/**
358	* Hardware locking flags.
359	*/
360	typedef enum drm_lock_flags {
361	_DRM_LOCK_READY = 0x01, /*< Wait until hardware is ready for DMA /
362	_DRM_LOCK_QUIESCENT = 0x02, /*< Wait until hardware quiescent /
363	_DRM_LOCK_FLUSH = 0x04, /*< Flush this context's DMA queue first /
364	_DRM_LOCK_FLUSH_ALL = 0x08, /*< Flush all DMA queues first /
365	/* These HALT flags aren't supported yet
366	-- they will be used to support the
367	full-screen DGA-like mode. */
368	_DRM_HALT_ALL_QUEUES = 0x10, /*< Halt all current and future queues /
369	_DRM_HALT_CUR_QUEUES = 0x20 /*< Halt all current queues /
370	} drm_lock_flags_t;
371
372	/**
373	* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
374	*
375	* \sa drmGetLock() and drmUnlock().
376	*/
377	typedef struct drm_lock {
378	int context;
379	drm_lock_flags_t flags;
380	} drm_lock_t;
381
382	/**
383	* DMA flags
384	*
385	* \warning
386	* These values \e must match xf86drm.h.
387	*
388	* \sa drm_dma.
389	*/
390	typedef enum drm_dma_flags {
391	/* Flags for DMA buffer dispatch */
392	_DRM_DMA_BLOCK = 0x01, /**<
393	* Block until buffer dispatched.
394	*
395	* \note The buffer may not yet have
396	* been processed by the hardware --
397	* getting a hardware lock with the
398	* hardware quiescent will ensure
399	* that the buffer has been
400	* processed.
401	*/
402	_DRM_DMA_WHILE_LOCKED = 0x02, /*< Dispatch while lock held /
403	_DRM_DMA_PRIORITY = 0x04, /*< High priority dispatch /
404
405	/* Flags for DMA buffer request */
406	_DRM_DMA_WAIT = 0x10, /*< Wait for free buffers /
407	_DRM_DMA_SMALLER_OK = 0x20, /*< Smaller-than-requested buffers OK /
408	_DRM_DMA_LARGER_OK = 0x40 /*< Larger-than-requested buffers OK /
409	} drm_dma_flags_t;
410
411	/**
412	* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
413	*
414	* \sa drmAddBufs().
415	*/
416	typedef struct drm_buf_desc {
417	int count; /*< Number of buffers of this size /
418	int size; /*< Size in bytes /
419	int low_mark; /*< Low water mark /
420	int high_mark; /*< High water mark /
421	enum {
422	_DRM_PAGE_ALIGN = 0x01, /*< Align on page boundaries for DMA /
423	_DRM_AGP_BUFFER = 0x02, /*< Buffer is in AGP space /
424	_DRM_SG_BUFFER = 0x04, /*< Scatter/gather memory buffer /
425	_DRM_FB_BUFFER = 0x08, /*< Buffer is in frame buffer /
426	_DRM_PCI_BUFFER_RO = 0x10 /*< Map PCI DMA buffer read-only /
427	} flags;
428	unsigned long agp_start; /**<
429	* Start address of where the AGP buffers are
430	* in the AGP aperture
431	*/
432	} drm_buf_desc_t;
433
434	/**
435	* DRM_IOCTL_INFO_BUFS ioctl argument type.
436	*/
437	typedef struct drm_buf_info {
438	int count; /*< Number of buffers described in list /
439	drm_buf_desc_t __user list; /< List of buffer descriptions /
440	} drm_buf_info_t;
441
442	/**
443	* DRM_IOCTL_FREE_BUFS ioctl argument type.
444	*/
445	typedef struct drm_buf_free {
446	int count;
447	int __user *list;
448	} drm_buf_free_t;
449
450	/**
451	* Buffer information
452	*
453	* \sa drm_buf_map.
454	*/
455	typedef struct drm_buf_pub {
456	int idx; /*< Index into the master buffer list /
457	int total; /*< Buffer size /
458	int used; /*< Amount of buffer in use (for DMA) /
459	void __user address; /< Address of buffer /
460	} drm_buf_pub_t;
461
462	/**
463	* DRM_IOCTL_MAP_BUFS ioctl argument type.
464	*/
465	typedef struct drm_buf_map {
466	int count; /*< Length of the buffer list /
467	#if defined(__cplusplus)
468	void __user *c_virtual;
469	#else
470	void __user virtual; /< Mmap'd area in user-virtual /
471	#endif
472	drm_buf_pub_t __user list; /< Buffer information /
473	} drm_buf_map_t;
474
475	/**
476	* DRM_IOCTL_DMA ioctl argument type.
477	*
478	* Indices here refer to the offset into the buffer list in drm_buf_get.
479	*
480	* \sa drmDMA().
481	*/
482	typedef struct drm_dma {
483	int context; /*< Context handle /
484	int send_count; /*< Number of buffers to send /
485	int __user send_indices; /< List of handles to buffers /
486	int __user send_sizes; /< Lengths of data to send /
487	drm_dma_flags_t flags; /*< Flags /
488	int request_count; /*< Number of buffers requested /
489	int request_size; /*< Desired size for buffers /
490	int __user request_indices; /< Buffer information /
491	int __user *request_sizes;
492	int granted_count; /*< Number of buffers granted /
493	} drm_dma_t;
494
495	typedef enum {
496	_DRM_CONTEXT_PRESERVED = 0x01,
497	_DRM_CONTEXT_2DONLY = 0x02
498	} drm_ctx_flags_t;
499
500	/**
501	* DRM_IOCTL_ADD_CTX ioctl argument type.
502	*
503	* \sa drmCreateContext() and drmDestroyContext().
504	*/
505	typedef struct drm_ctx {
506	drm_context_t handle;
507	drm_ctx_flags_t flags;
508	} drm_ctx_t;
509
510	/**
511	* DRM_IOCTL_RES_CTX ioctl argument type.
512	*/
513	typedef struct drm_ctx_res {
514	int count;
515	drm_ctx_t __user *contexts;
516	} drm_ctx_res_t;
517
518	/**
519	* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
520	*/
521	typedef struct drm_draw {
522	drm_drawable_t handle;
523	} drm_draw_t;
524
525	/**
526	* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
527	*/
528	typedef enum {
529	DRM_DRAWABLE_CLIPRECTS,
530	} drm_drawable_info_type_t;
531
532	typedef struct drm_update_draw {
533	drm_drawable_t handle;
534	unsigned int type;
535	unsigned int num;
536	unsigned long long data;
537	} drm_update_draw_t;
538
539	/**
540	* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
541	*/
542	typedef struct drm_auth {
543	drm_magic_t magic;
544	} drm_auth_t;
545
546	/**
547	* DRM_IOCTL_IRQ_BUSID ioctl argument type.
548	*
549	* \sa drmGetInterruptFromBusID().
550	*/
551	typedef struct drm_irq_busid {
552	int irq; /*< IRQ number /
553	int busnum; /*< bus number /
554	int devnum; /*< device number /
555	int funcnum; /*< function number /
556	} drm_irq_busid_t;
557
558	typedef enum {
559	_DRM_VBLANK_ABSOLUTE = 0x0, /*< Wait for specific vblank sequence number /
560	_DRM_VBLANK_RELATIVE = 0x1, /*< Wait for given number of vblanks /
561	_DRM_VBLANK_NEXTONMISS = 0x10000000, /*< If missed, wait for next vblank /
562	_DRM_VBLANK_SECONDARY = 0x20000000, /*< Secondary display controller /
563	_DRM_VBLANK_SIGNAL = 0x40000000 /*< Send signal instead of blocking /
564	} drm_vblank_seq_type_t;
565
566	#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE \| _DRM_VBLANK_RELATIVE)
567	#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL \| _DRM_VBLANK_SECONDARY \| \
568	_DRM_VBLANK_NEXTONMISS)
569
570	struct drm_wait_vblank_request {
571	drm_vblank_seq_type_t type;
572	unsigned int sequence;
573	unsigned long signal;
574	};
575
576	struct drm_wait_vblank_reply {
577	drm_vblank_seq_type_t type;
578	unsigned int sequence;
579	long tval_sec;
580	long tval_usec;
581	};
582
583	/**
584	* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
585	*
586	* \sa drmWaitVBlank().
587	*/
588	typedef union drm_wait_vblank {
589	struct drm_wait_vblank_request request;
590	struct drm_wait_vblank_reply reply;
591	} drm_wait_vblank_t;
592
593	/**
594	* DRM_IOCTL_AGP_ENABLE ioctl argument type.
595	*
596	* \sa drmAgpEnable().
597	*/
598	typedef struct drm_agp_mode {
599	unsigned long mode; /*< AGP mode /
600	} drm_agp_mode_t;
601
602	/**
603	* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
604	*
605	* \sa drmAgpAlloc() and drmAgpFree().
606	*/
607	typedef struct drm_agp_buffer {
608	unsigned long size; /*< In bytes -- will round to page boundary /
609	unsigned long handle; /*< Used for binding / unbinding /
610	unsigned long type; /*< Type of memory to allocate /
611	unsigned long physical; /*< Physical used by i810 /
612	} drm_agp_buffer_t;
613
614	/**
615	* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
616	*
617	* \sa drmAgpBind() and drmAgpUnbind().
618	*/
619	typedef struct drm_agp_binding {
620	unsigned long handle; /*< From drm_agp_buffer /
621	unsigned long offset; /*< In bytes -- will round to page boundary /
622	} drm_agp_binding_t;
623
624	/**
625	* DRM_IOCTL_AGP_INFO ioctl argument type.
626	*
627	* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
628	* drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
629	* drmAgpVendorId() and drmAgpDeviceId().
630	*/
631	typedef struct drm_agp_info {
632	int agp_version_major;
633	int agp_version_minor;
634	unsigned long mode;
635	unsigned long aperture_base; /*< physical address /
636	unsigned long aperture_size; /*< bytes /
637	unsigned long memory_allowed; /*< bytes /
638	unsigned long memory_used;
639
640	/** \name PCI information */
641	/@{ /
642	unsigned short id_vendor;
643	unsigned short id_device;
644	/@} /
645	} drm_agp_info_t;
646
647	/**
648	* DRM_IOCTL_SG_ALLOC ioctl argument type.
649	*/
650	typedef struct drm_scatter_gather {
651	unsigned long size; /*< In bytes -- will round to page boundary /
652	unsigned long handle; /*< Used for mapping / unmapping /
653	} drm_scatter_gather_t;
654
655	/**
656	* DRM_IOCTL_SET_VERSION ioctl argument type.
657	*/
658	typedef struct drm_set_version {
659	int drm_di_major;
660	int drm_di_minor;
661	int drm_dd_major;
662	int drm_dd_minor;
663	} drm_set_version_t;
664
665
666	#define DRM_FENCE_FLAG_EMIT 0x00000001
667	#define DRM_FENCE_FLAG_SHAREABLE 0x00000002
668	#define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
669	#define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
670
671	/* Reserved for driver use */
672	#define DRM_FENCE_MASK_DRIVER 0xFF000000
673
674	#define DRM_FENCE_TYPE_EXE 0x00000001
675
676	typedef struct drm_fence_arg {
677	unsigned handle;
678	int class;
679	unsigned type;
680	unsigned flags;
681	unsigned signaled;
682	unsigned expand_pad[4]; /Future expansion /
683	enum {
684	drm_fence_create,
685	drm_fence_destroy,
686	drm_fence_reference,
687	drm_fence_unreference,
688	drm_fence_signaled,
689	drm_fence_flush,
690	drm_fence_wait,
691	drm_fence_emit,
692	drm_fence_buffers
693	} op;
694	} drm_fence_arg_t;
695
696	/* Buffer permissions, referring to how the GPU uses the buffers.
697	these translate to fence types used for the buffers.
698	Typically a texture buffer is read, A destination buffer is write and
699	a command (batch-) buffer is exe. Can be or-ed together. */
700
701	#define DRM_BO_FLAG_READ 0x00000001
702	#define DRM_BO_FLAG_WRITE 0x00000002
703	#define DRM_BO_FLAG_EXE 0x00000004
704
705	/*
706	* Status flags. Can be read to determine the actual state of a buffer.
707	*/
708
709	/*
710	* Cannot evict this buffer. Not even with force. This type of buffer should
711	* only be available for root, and must be manually removed before buffer
712	* manager shutdown or swapout.
713	*/
714	#define DRM_BO_FLAG_NO_EVICT 0x00000010
715	/* Always keep a system memory shadow to a vram buffer */
716	#define DRM_BO_FLAG_SHADOW_VRAM 0x00000020
717	/* The buffer is shareable with other processes */
718	#define DRM_BO_FLAG_SHAREABLE 0x00000040
719	/* The buffer is currently cached */
720	#define DRM_BO_FLAG_CACHED 0x00000080
721	/* Make sure that every time this buffer is validated, it ends up on the same
722	* location. The buffer will also not be evicted when claiming space for
723	* other buffers. Basically a pinned buffer but it may be thrown out as
724	* part of buffer manager shutdown or swapout. Not supported yet.*/
725	#define DRM_BO_FLAG_NO_MOVE 0x00000100
726
727	/* Make sure the buffer is in cached memory when mapped for reading */
728	#define DRM_BO_FLAG_READ_CACHED 0x00080000
729	/* When there is a choice between VRAM and TT, prefer VRAM.
730	The default behaviour is to prefer TT. */
731	#define DRM_BO_FLAG_PREFER_VRAM 0x00040000
732	/* Bind this buffer cached if the hardware supports it. */
733	#define DRM_BO_FLAG_BIND_CACHED 0x0002000
734
735	/* System Memory */
736	#define DRM_BO_FLAG_MEM_LOCAL 0x01000000
737	/* Translation table memory */
738	#define DRM_BO_FLAG_MEM_TT 0x02000000
739	/* Vram memory */
740	#define DRM_BO_FLAG_MEM_VRAM 0x04000000
741	/* Unmappable Vram memory */
742	#define DRM_BO_FLAG_MEM_VRAM_NM 0x08000000
743	/* Memory flag mask */
744	#define DRM_BO_MASK_MEM 0xFF000000
745
746	/* When creating a buffer, Avoid system storage even if allowed */
747	#define DRM_BO_HINT_AVOID_LOCAL 0x00000001
748	/* Don't block on validate and map */
749	#define DRM_BO_HINT_DONT_BLOCK 0x00000002
750	/* Don't place this buffer on the unfenced list.*/
751	#define DRM_BO_HINT_DONT_FENCE 0x00000004
752	#define DRM_BO_HINT_WAIT_LAZY 0x00000008
753	#define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
754
755
756	/* Driver specific flags. Could be for example rendering engine */
757	#define DRM_BO_MASK_DRIVER 0x00F00000
758
759	typedef enum {
760	drm_bo_type_dc,
761	drm_bo_type_user,
762	drm_bo_type_fake
763	}drm_bo_type_t;
764
765
766	typedef struct drm_bo_arg_request {
767	unsigned handle; /* User space handle */
768	unsigned mask;
769	unsigned hint;
770	drm_u64_t size;
771	drm_bo_type_t type;
772	unsigned arg_handle;
773	drm_u64_t buffer_start;
774	unsigned page_alignment;
775	unsigned expand_pad[4]; /Future expansion /
776	enum {
777	drm_bo_create,
778	drm_bo_validate,
779	drm_bo_map,
780	drm_bo_unmap,
781	drm_bo_fence,
782	drm_bo_destroy,
783	drm_bo_reference,
784	drm_bo_unreference,
785	drm_bo_info,
786	drm_bo_wait_idle,
787	drm_bo_ref_fence
788	} op;
789	} drm_bo_arg_request_t;
790
791
792	/*
793	* Reply flags
794	*/
795
796	#define DRM_BO_REP_BUSY 0x00000001
797
798	typedef struct drm_bo_arg_reply {
799	int ret;
800	unsigned handle;
801	unsigned flags;
802	drm_u64_t size;
803	drm_u64_t offset;
804	drm_u64_t arg_handle;
805	unsigned mask;
806	drm_u64_t buffer_start;
807	unsigned fence_flags;
808	unsigned rep_flags;
809	unsigned page_alignment;
810	unsigned expand_pad[4]; /Future expansion /
811	}drm_bo_arg_reply_t;
812
813
814	typedef struct drm_bo_arg{
815	int handled;
816	drm_u64_t next;
817	union {
818	drm_bo_arg_request_t req;
819	drm_bo_arg_reply_t rep;
820	} d;
821	} drm_bo_arg_t;
822
823	#define DRM_BO_MEM_LOCAL 0
824	#define DRM_BO_MEM_TT 1
825	#define DRM_BO_MEM_VRAM 2
826	#define DRM_BO_MEM_VRAM_NM 3
827	#define DRM_BO_MEM_TYPES 2 /* For now. */
828
829	typedef union drm_mm_init_arg{
830	struct {
831	enum {
832	mm_init,
833	mm_takedown,
834	mm_query,
835	mm_lock,
836	mm_unlock
837	} op;
838	drm_u64_t p_offset;
839	drm_u64_t p_size;
840	unsigned mem_type;
841	unsigned expand_pad[8]; /Future expansion /
842	} req;
843	struct {
844	drm_handle_t mm_sarea;
845	unsigned expand_pad[8]; /Future expansion /
846	} rep;
847	} drm_mm_init_arg_t;
848
849	/**
850	* \name Ioctls Definitions
851	*/
852	/@{/
853
854	#define DRM_IOCTL_BASE 'd'
855	#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
856	#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
857	#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
858	#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
859
860	#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
861	#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
862	#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
863	#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
864	#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
865	#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
866	#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
867	#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
868
869	#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
870	#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
871	#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
872	#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
873	#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
874	#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
875	#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
876	#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
877	#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
878	#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
879	#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
880
881	#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
882
883	#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
884	#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
885
886	#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
887	#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
888	#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
889	#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
890	#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
891	#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
892	#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
893	#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
894	#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
895	#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
896	#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
897	#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
898	#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
899
900	#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
901	#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
902	#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
903	#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
904	#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
905	#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
906	#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
907	#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
908
909	#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
910	#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
911
912	#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
913
914	#define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t)
915	#define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t)
916	#define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t)
917
918	#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t)
919
920	/@}/
921
922	/**
923	* Device specific ioctls should only be in their respective headers
924	* The device specific ioctl range is from 0x40 to 0x99.
925	* Generic IOCTLS restart at 0xA0.
926	*
927	* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
928	* drmCommandReadWrite().
929	*/
930	#define DRM_COMMAND_BASE 0x40
931	#define DRM_COMMAND_END 0xA0
932
933	#endif

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source: vbox/trunk/src/VBox/Additions/x11/x11include/libdrm-2.3.0/drm.h@ 17233

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