| 1 | /*
|
|---|
| 2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
|
|---|
| 3 | * All Rights Reserved.
|
|---|
| 4 | *
|
|---|
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a
|
|---|
| 6 | * copy of this software and associated documentation files (the
|
|---|
| 7 | * "Software"), to deal in the Software without restriction, including
|
|---|
| 8 | * without limitation the rights to use, copy, modify, merge, publish,
|
|---|
| 9 | * distribute, sub license, and/or sell copies of the Software, and to
|
|---|
| 10 | * permit persons to whom the Software is furnished to do so, subject to
|
|---|
| 11 | * the following conditions:
|
|---|
| 12 | *
|
|---|
| 13 | * The above copyright notice and this permission notice (including the
|
|---|
| 14 | * next paragraph) shall be included in all copies or substantial portions
|
|---|
| 15 | * of the Software.
|
|---|
| 16 | *
|
|---|
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
|---|
| 18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|---|
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
|
|---|
| 20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
|
|---|
| 21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
|---|
| 22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
|---|
| 23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|---|
| 24 | *
|
|---|
| 25 | */
|
|---|
| 26 |
|
|---|
| 27 | #ifndef _I915_DRM_H_
|
|---|
| 28 | #define _I915_DRM_H_
|
|---|
| 29 |
|
|---|
| 30 | /* Please note that modifications to all structs defined here are
|
|---|
| 31 | * subject to backwards-compatibility constraints.
|
|---|
| 32 | */
|
|---|
| 33 |
|
|---|
| 34 | #include "drm.h"
|
|---|
| 35 |
|
|---|
| 36 | /* Each region is a minimum of 16k, and there are at most 255 of them.
|
|---|
| 37 | */
|
|---|
| 38 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
|
|---|
| 39 | * of chars for next/prev indices */
|
|---|
| 40 | #define I915_LOG_MIN_TEX_REGION_SIZE 14
|
|---|
| 41 |
|
|---|
| 42 | typedef struct _drm_i915_init {
|
|---|
| 43 | enum {
|
|---|
| 44 | I915_INIT_DMA = 0x01,
|
|---|
| 45 | I915_CLEANUP_DMA = 0x02,
|
|---|
| 46 | I915_RESUME_DMA = 0x03
|
|---|
| 47 | } func;
|
|---|
| 48 | unsigned int mmio_offset;
|
|---|
| 49 | int sarea_priv_offset;
|
|---|
| 50 | unsigned int ring_start;
|
|---|
| 51 | unsigned int ring_end;
|
|---|
| 52 | unsigned int ring_size;
|
|---|
| 53 | unsigned int front_offset;
|
|---|
| 54 | unsigned int back_offset;
|
|---|
| 55 | unsigned int depth_offset;
|
|---|
| 56 | unsigned int w;
|
|---|
| 57 | unsigned int h;
|
|---|
| 58 | unsigned int pitch;
|
|---|
| 59 | unsigned int pitch_bits;
|
|---|
| 60 | unsigned int back_pitch;
|
|---|
| 61 | unsigned int depth_pitch;
|
|---|
| 62 | unsigned int cpp;
|
|---|
| 63 | unsigned int chipset;
|
|---|
| 64 | } drm_i915_init_t;
|
|---|
| 65 |
|
|---|
| 66 | typedef struct _drm_i915_sarea {
|
|---|
| 67 | drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
|
|---|
| 68 | int last_upload; /* last time texture was uploaded */
|
|---|
| 69 | int last_enqueue; /* last time a buffer was enqueued */
|
|---|
| 70 | int last_dispatch; /* age of the most recently dispatched buffer */
|
|---|
| 71 | int ctxOwner; /* last context to upload state */
|
|---|
| 72 | int texAge;
|
|---|
| 73 | int pf_enabled; /* is pageflipping allowed? */
|
|---|
| 74 | int pf_active;
|
|---|
| 75 | int pf_current_page; /* which buffer is being displayed? */
|
|---|
| 76 | int perf_boxes; /* performance boxes to be displayed */
|
|---|
| 77 | int width, height; /* screen size in pixels */
|
|---|
| 78 |
|
|---|
| 79 | drm_handle_t front_handle;
|
|---|
| 80 | int front_offset;
|
|---|
| 81 | int front_size;
|
|---|
| 82 |
|
|---|
| 83 | drm_handle_t back_handle;
|
|---|
| 84 | int back_offset;
|
|---|
| 85 | int back_size;
|
|---|
| 86 |
|
|---|
| 87 | drm_handle_t depth_handle;
|
|---|
| 88 | int depth_offset;
|
|---|
| 89 | int depth_size;
|
|---|
| 90 |
|
|---|
| 91 | drm_handle_t tex_handle;
|
|---|
| 92 | int tex_offset;
|
|---|
| 93 | int tex_size;
|
|---|
| 94 | int log_tex_granularity;
|
|---|
| 95 | int pitch;
|
|---|
| 96 | int rotation; /* 0, 90, 180 or 270 */
|
|---|
| 97 | int rotated_offset;
|
|---|
| 98 | int rotated_size;
|
|---|
| 99 | int rotated_pitch;
|
|---|
| 100 | int virtualX, virtualY;
|
|---|
| 101 |
|
|---|
| 102 | unsigned int front_tiled;
|
|---|
| 103 | unsigned int back_tiled;
|
|---|
| 104 | unsigned int depth_tiled;
|
|---|
| 105 | unsigned int rotated_tiled;
|
|---|
| 106 | unsigned int rotated2_tiled;
|
|---|
| 107 |
|
|---|
| 108 | int pipeA_x;
|
|---|
| 109 | int pipeA_y;
|
|---|
| 110 | int pipeA_w;
|
|---|
| 111 | int pipeA_h;
|
|---|
| 112 | int pipeB_x;
|
|---|
| 113 | int pipeB_y;
|
|---|
| 114 | int pipeB_w;
|
|---|
| 115 | int pipeB_h;
|
|---|
| 116 | } drm_i915_sarea_t;
|
|---|
| 117 |
|
|---|
| 118 | /* Driver specific fence types and classes.
|
|---|
| 119 | */
|
|---|
| 120 |
|
|---|
| 121 | /* The only fence class we support */
|
|---|
| 122 | #define DRM_I915_FENCE_CLASS_ACCEL 0
|
|---|
| 123 | /* Fence type that guarantees read-write flush */
|
|---|
| 124 | #define DRM_I915_FENCE_TYPE_RW 2
|
|---|
| 125 | /* MI_FLUSH programmed just before the fence */
|
|---|
| 126 | #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
|
|---|
| 127 |
|
|---|
| 128 | /* Flags for perf_boxes
|
|---|
| 129 | */
|
|---|
| 130 | #define I915_BOX_RING_EMPTY 0x1
|
|---|
| 131 | #define I915_BOX_FLIP 0x2
|
|---|
| 132 | #define I915_BOX_WAIT 0x4
|
|---|
| 133 | #define I915_BOX_TEXTURE_LOAD 0x8
|
|---|
| 134 | #define I915_BOX_LOST_CONTEXT 0x10
|
|---|
| 135 |
|
|---|
| 136 | /* I915 specific ioctls
|
|---|
| 137 | * The device specific ioctl range is 0x40 to 0x79.
|
|---|
| 138 | */
|
|---|
| 139 | #define DRM_I915_INIT 0x00
|
|---|
| 140 | #define DRM_I915_FLUSH 0x01
|
|---|
| 141 | #define DRM_I915_FLIP 0x02
|
|---|
| 142 | #define DRM_I915_BATCHBUFFER 0x03
|
|---|
| 143 | #define DRM_I915_IRQ_EMIT 0x04
|
|---|
| 144 | #define DRM_I915_IRQ_WAIT 0x05
|
|---|
| 145 | #define DRM_I915_GETPARAM 0x06
|
|---|
| 146 | #define DRM_I915_SETPARAM 0x07
|
|---|
| 147 | #define DRM_I915_ALLOC 0x08
|
|---|
| 148 | #define DRM_I915_FREE 0x09
|
|---|
| 149 | #define DRM_I915_INIT_HEAP 0x0a
|
|---|
| 150 | #define DRM_I915_CMDBUFFER 0x0b
|
|---|
| 151 | #define DRM_I915_DESTROY_HEAP 0x0c
|
|---|
| 152 | #define DRM_I915_SET_VBLANK_PIPE 0x0d
|
|---|
| 153 | #define DRM_I915_GET_VBLANK_PIPE 0x0e
|
|---|
| 154 | #define DRM_I915_VBLANK_SWAP 0x0f
|
|---|
| 155 |
|
|---|
| 156 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
|
|---|
| 157 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
|
|---|
| 158 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
|
|---|
| 159 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
|
|---|
| 160 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
|
|---|
| 161 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
|
|---|
| 162 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
|
|---|
| 163 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
|
|---|
| 164 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
|
|---|
| 165 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
|
|---|
| 166 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
|
|---|
| 167 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
|
|---|
| 168 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
|
|---|
| 169 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
|
|---|
| 170 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
|
|---|
| 171 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
|
|---|
| 172 |
|
|---|
| 173 |
|
|---|
| 174 | /* Allow drivers to submit batchbuffers directly to hardware, relying
|
|---|
| 175 | * on the security mechanisms provided by hardware.
|
|---|
| 176 | */
|
|---|
| 177 | typedef struct _drm_i915_batchbuffer {
|
|---|
| 178 | int start; /* agp offset */
|
|---|
| 179 | int used; /* nr bytes in use */
|
|---|
| 180 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
|
|---|
| 181 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
|
|---|
| 182 | int num_cliprects; /* mulitpass with multiple cliprects? */
|
|---|
| 183 | drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
|
|---|
| 184 | } drm_i915_batchbuffer_t;
|
|---|
| 185 |
|
|---|
| 186 | /* As above, but pass a pointer to userspace buffer which can be
|
|---|
| 187 | * validated by the kernel prior to sending to hardware.
|
|---|
| 188 | */
|
|---|
| 189 | typedef struct _drm_i915_cmdbuffer {
|
|---|
| 190 | char __user *buf; /* pointer to userspace command buffer */
|
|---|
| 191 | int sz; /* nr bytes in buf */
|
|---|
| 192 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
|
|---|
| 193 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
|
|---|
| 194 | int num_cliprects; /* mulitpass with multiple cliprects? */
|
|---|
| 195 | drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
|
|---|
| 196 | } drm_i915_cmdbuffer_t;
|
|---|
| 197 |
|
|---|
| 198 | /* Userspace can request & wait on irq's:
|
|---|
| 199 | */
|
|---|
| 200 | typedef struct drm_i915_irq_emit {
|
|---|
| 201 | int __user *irq_seq;
|
|---|
| 202 | } drm_i915_irq_emit_t;
|
|---|
| 203 |
|
|---|
| 204 | typedef struct drm_i915_irq_wait {
|
|---|
| 205 | int irq_seq;
|
|---|
| 206 | } drm_i915_irq_wait_t;
|
|---|
| 207 |
|
|---|
| 208 | /* Ioctl to query kernel params:
|
|---|
| 209 | */
|
|---|
| 210 | #define I915_PARAM_IRQ_ACTIVE 1
|
|---|
| 211 | #define I915_PARAM_ALLOW_BATCHBUFFER 2
|
|---|
| 212 | #define I915_PARAM_LAST_DISPATCH 3
|
|---|
| 213 |
|
|---|
| 214 | typedef struct drm_i915_getparam {
|
|---|
| 215 | int param;
|
|---|
| 216 | int __user *value;
|
|---|
| 217 | } drm_i915_getparam_t;
|
|---|
| 218 |
|
|---|
| 219 | /* Ioctl to set kernel params:
|
|---|
| 220 | */
|
|---|
| 221 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
|
|---|
| 222 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
|
|---|
| 223 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
|
|---|
| 224 |
|
|---|
| 225 | typedef struct drm_i915_setparam {
|
|---|
| 226 | int param;
|
|---|
| 227 | int value;
|
|---|
| 228 | } drm_i915_setparam_t;
|
|---|
| 229 |
|
|---|
| 230 | /* A memory manager for regions of shared memory:
|
|---|
| 231 | */
|
|---|
| 232 | #define I915_MEM_REGION_AGP 1
|
|---|
| 233 |
|
|---|
| 234 | typedef struct drm_i915_mem_alloc {
|
|---|
| 235 | int region;
|
|---|
| 236 | int alignment;
|
|---|
| 237 | int size;
|
|---|
| 238 | int __user *region_offset; /* offset from start of fb or agp */
|
|---|
| 239 | } drm_i915_mem_alloc_t;
|
|---|
| 240 |
|
|---|
| 241 | typedef struct drm_i915_mem_free {
|
|---|
| 242 | int region;
|
|---|
| 243 | int region_offset;
|
|---|
| 244 | } drm_i915_mem_free_t;
|
|---|
| 245 |
|
|---|
| 246 | typedef struct drm_i915_mem_init_heap {
|
|---|
| 247 | int region;
|
|---|
| 248 | int size;
|
|---|
| 249 | int start;
|
|---|
| 250 | } drm_i915_mem_init_heap_t;
|
|---|
| 251 |
|
|---|
| 252 | /* Allow memory manager to be torn down and re-initialized (eg on
|
|---|
| 253 | * rotate):
|
|---|
| 254 | */
|
|---|
| 255 | typedef struct drm_i915_mem_destroy_heap {
|
|---|
| 256 | int region;
|
|---|
| 257 | } drm_i915_mem_destroy_heap_t;
|
|---|
| 258 |
|
|---|
| 259 | /* Allow X server to configure which pipes to monitor for vblank signals
|
|---|
| 260 | */
|
|---|
| 261 | #define DRM_I915_VBLANK_PIPE_A 1
|
|---|
| 262 | #define DRM_I915_VBLANK_PIPE_B 2
|
|---|
| 263 |
|
|---|
| 264 | typedef struct drm_i915_vblank_pipe {
|
|---|
| 265 | int pipe;
|
|---|
| 266 | } drm_i915_vblank_pipe_t;
|
|---|
| 267 |
|
|---|
| 268 | /* Schedule buffer swap at given vertical blank:
|
|---|
| 269 | */
|
|---|
| 270 | typedef struct drm_i915_vblank_swap {
|
|---|
| 271 | drm_drawable_t drawable;
|
|---|
| 272 | drm_vblank_seq_type_t seqtype;
|
|---|
| 273 | unsigned int sequence;
|
|---|
| 274 | } drm_i915_vblank_swap_t;
|
|---|
| 275 |
|
|---|
| 276 | #endif /* _I915_DRM_H_ */
|
|---|
