| 1 | /*
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| 2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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| 3 | * All Rights Reserved.
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| 4 | *
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 6 | * copy of this software and associated documentation files (the
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| 7 | * "Software"), to deal in the Software without restriction, including
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| 8 | * without limitation the rights to use, copy, modify, merge, publish,
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to
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| 10 | * permit persons to whom the Software is furnished to do so, subject to
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| 11 | * the following conditions:
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| 12 | *
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| 13 | * The above copyright notice and this permission notice (including the
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| 14 | * next paragraph) shall be included in all copies or substantial portions
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| 15 | * of the Software.
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| 16 | *
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| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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| 18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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| 20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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| 21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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| 22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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| 23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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| 24 | *
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| 25 | */
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| 26 |
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| 27 | #ifndef _I915_DRM_H_
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| 28 | #define _I915_DRM_H_
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| 29 |
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| 30 | /* Please note that modifications to all structs defined here are
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| 31 | * subject to backwards-compatibility constraints.
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| 32 | */
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| 33 |
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| 34 | #include "drm.h"
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| 35 |
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| 36 | /* Each region is a minimum of 16k, and there are at most 255 of them.
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| 37 | */
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| 38 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
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| 39 | * of chars for next/prev indices */
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| 40 | #define I915_LOG_MIN_TEX_REGION_SIZE 14
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| 41 |
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| 42 | typedef struct _drm_i915_init {
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| 43 | enum {
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| 44 | I915_INIT_DMA = 0x01,
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| 45 | I915_CLEANUP_DMA = 0x02,
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| 46 | I915_RESUME_DMA = 0x03,
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| 47 |
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| 48 | /* Since this struct isn't versioned, just used a new
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| 49 | * 'func' code to indicate the presence of dri2 sarea
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| 50 | * info. */
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| 51 | I915_INIT_DMA2 = 0x04
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| 52 | } func;
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| 53 | unsigned int mmio_offset;
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| 54 | int sarea_priv_offset;
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| 55 | unsigned int ring_start;
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| 56 | unsigned int ring_end;
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| 57 | unsigned int ring_size;
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| 58 | unsigned int front_offset;
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| 59 | unsigned int back_offset;
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| 60 | unsigned int depth_offset;
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| 61 | unsigned int w;
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| 62 | unsigned int h;
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| 63 | unsigned int pitch;
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| 64 | unsigned int pitch_bits;
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| 65 | unsigned int back_pitch;
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| 66 | unsigned int depth_pitch;
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| 67 | unsigned int cpp;
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| 68 | unsigned int chipset;
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| 69 | unsigned int sarea_handle;
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| 70 | } drm_i915_init_t;
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| 71 |
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| 72 | typedef struct drm_i915_sarea {
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| 73 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
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| 74 | int last_upload; /* last time texture was uploaded */
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| 75 | int last_enqueue; /* last time a buffer was enqueued */
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| 76 | int last_dispatch; /* age of the most recently dispatched buffer */
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| 77 | int ctxOwner; /* last context to upload state */
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| 78 | int texAge;
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| 79 | int pf_enabled; /* is pageflipping allowed? */
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| 80 | int pf_active;
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| 81 | int pf_current_page; /* which buffer is being displayed? */
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| 82 | int perf_boxes; /* performance boxes to be displayed */
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| 83 | int width, height; /* screen size in pixels */
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| 84 |
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| 85 | drm_handle_t front_handle;
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| 86 | int front_offset;
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| 87 | int front_size;
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| 88 |
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| 89 | drm_handle_t back_handle;
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| 90 | int back_offset;
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| 91 | int back_size;
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| 92 |
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| 93 | drm_handle_t depth_handle;
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| 94 | int depth_offset;
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| 95 | int depth_size;
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| 96 |
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| 97 | drm_handle_t tex_handle;
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| 98 | int tex_offset;
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| 99 | int tex_size;
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| 100 | int log_tex_granularity;
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| 101 | int pitch;
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| 102 | int rotation; /* 0, 90, 180 or 270 */
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| 103 | int rotated_offset;
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| 104 | int rotated_size;
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| 105 | int rotated_pitch;
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| 106 | int virtualX, virtualY;
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| 107 |
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| 108 | unsigned int front_tiled;
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| 109 | unsigned int back_tiled;
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| 110 | unsigned int depth_tiled;
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| 111 | unsigned int rotated_tiled;
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| 112 | unsigned int rotated2_tiled;
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| 113 |
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| 114 | int planeA_x;
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| 115 | int planeA_y;
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| 116 | int planeA_w;
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| 117 | int planeA_h;
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| 118 | int planeB_x;
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| 119 | int planeB_y;
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| 120 | int planeB_w;
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| 121 | int planeB_h;
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| 122 |
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| 123 | /* Triple buffering */
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| 124 | drm_handle_t third_handle;
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| 125 | int third_offset;
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| 126 | int third_size;
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| 127 | unsigned int third_tiled;
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| 128 |
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| 129 | /* buffer object handles for the static buffers. May change
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| 130 | * over the lifetime of the client, though it doesn't in our current
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| 131 | * implementation.
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| 132 | */
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| 133 | unsigned int front_bo_handle;
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| 134 | unsigned int back_bo_handle;
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| 135 | unsigned int third_bo_handle;
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| 136 | unsigned int depth_bo_handle;
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| 137 | } drm_i915_sarea_t;
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| 138 |
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| 139 | /* Driver specific fence types and classes.
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| 140 | */
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| 141 | /* Flags for perf_boxes
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| 142 | */
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| 143 | #define I915_BOX_RING_EMPTY 0x1
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| 144 | #define I915_BOX_FLIP 0x2
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| 145 | #define I915_BOX_WAIT 0x4
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| 146 | #define I915_BOX_TEXTURE_LOAD 0x8
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| 147 | #define I915_BOX_LOST_CONTEXT 0x10
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| 148 |
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| 149 | /* I915 specific ioctls
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| 150 | * The device specific ioctl range is 0x40 to 0x79.
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| 151 | */
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| 152 | #define DRM_I915_INIT 0x00
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| 153 | #define DRM_I915_FLUSH 0x01
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| 154 | #define DRM_I915_FLIP 0x02
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| 155 | #define DRM_I915_BATCHBUFFER 0x03
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| 156 | #define DRM_I915_IRQ_EMIT 0x04
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| 157 | #define DRM_I915_IRQ_WAIT 0x05
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| 158 | #define DRM_I915_GETPARAM 0x06
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| 159 | #define DRM_I915_SETPARAM 0x07
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| 160 | #define DRM_I915_ALLOC 0x08
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| 161 | #define DRM_I915_FREE 0x09
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| 162 | #define DRM_I915_INIT_HEAP 0x0a
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| 163 | #define DRM_I915_CMDBUFFER 0x0b
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| 164 | #define DRM_I915_DESTROY_HEAP 0x0c
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| 165 | #define DRM_I915_SET_VBLANK_PIPE 0x0d
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| 166 | #define DRM_I915_GET_VBLANK_PIPE 0x0e
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| 167 | #define DRM_I915_VBLANK_SWAP 0x0f
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| 168 | #define DRM_I915_MMIO 0x10
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| 169 | #define DRM_I915_HWS_ADDR 0x11
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| 170 |
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| 171 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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| 172 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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| 173 | #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
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| 174 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
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| 175 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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| 176 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
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| 177 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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| 178 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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| 179 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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| 180 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
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| 181 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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| 182 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
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| 183 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
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| 184 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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| 185 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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| 186 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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| 187 | #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
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| 188 |
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| 189 | /* Asynchronous page flipping:
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| 190 | */
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| 191 | typedef struct drm_i915_flip {
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| 192 | /*
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| 193 | * This is really talking about planes, and we could rename it
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| 194 | * except for the fact that some of the duplicated i915_drm.h files
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| 195 | * out there check for HAVE_I915_FLIP and so might pick up this
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| 196 | * version.
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| 197 | */
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| 198 | int pipes;
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| 199 | } drm_i915_flip_t;
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| 200 |
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| 201 | /* Allow drivers to submit batchbuffers directly to hardware, relying
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| 202 | * on the security mechanisms provided by hardware.
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| 203 | */
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| 204 | typedef struct drm_i915_batchbuffer {
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| 205 | int start; /* agp offset */
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| 206 | int used; /* nr bytes in use */
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| 207 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
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| 208 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
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| 209 | int num_cliprects; /* mulitpass with multiple cliprects? */
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| 210 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
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| 211 | } drm_i915_batchbuffer_t;
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| 212 |
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| 213 | /* As above, but pass a pointer to userspace buffer which can be
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| 214 | * validated by the kernel prior to sending to hardware.
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| 215 | */
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| 216 | typedef struct _drm_i915_cmdbuffer {
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| 217 | char __user *buf; /* pointer to userspace command buffer */
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| 218 | int sz; /* nr bytes in buf */
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| 219 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
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| 220 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
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| 221 | int num_cliprects; /* mulitpass with multiple cliprects? */
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| 222 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
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| 223 | } drm_i915_cmdbuffer_t;
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| 224 |
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| 225 | /* Userspace can request & wait on irq's:
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| 226 | */
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| 227 | typedef struct drm_i915_irq_emit {
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| 228 | int __user *irq_seq;
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| 229 | } drm_i915_irq_emit_t;
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| 230 |
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| 231 | typedef struct drm_i915_irq_wait {
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| 232 | int irq_seq;
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| 233 | } drm_i915_irq_wait_t;
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| 234 |
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| 235 | /* Ioctl to query kernel params:
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| 236 | */
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| 237 | #define I915_PARAM_IRQ_ACTIVE 1
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| 238 | #define I915_PARAM_ALLOW_BATCHBUFFER 2
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| 239 | #define I915_PARAM_LAST_DISPATCH 3
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| 240 | #define I915_PARAM_CHIPSET_ID 4
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| 241 |
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| 242 | typedef struct drm_i915_getparam {
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| 243 | int param;
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| 244 | int __user *value;
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| 245 | } drm_i915_getparam_t;
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| 246 |
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| 247 | /* Ioctl to set kernel params:
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| 248 | */
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| 249 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
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| 250 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
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| 251 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
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| 252 |
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| 253 | typedef struct drm_i915_setparam {
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| 254 | int param;
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| 255 | int value;
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| 256 | } drm_i915_setparam_t;
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| 257 |
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| 258 | /* A memory manager for regions of shared memory:
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| 259 | */
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| 260 | #define I915_MEM_REGION_AGP 1
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| 261 |
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| 262 | typedef struct drm_i915_mem_alloc {
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| 263 | int region;
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| 264 | int alignment;
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| 265 | int size;
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| 266 | int __user *region_offset; /* offset from start of fb or agp */
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| 267 | } drm_i915_mem_alloc_t;
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| 268 |
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| 269 | typedef struct drm_i915_mem_free {
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| 270 | int region;
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| 271 | int region_offset;
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| 272 | } drm_i915_mem_free_t;
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| 273 |
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| 274 | typedef struct drm_i915_mem_init_heap {
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| 275 | int region;
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| 276 | int size;
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| 277 | int start;
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| 278 | } drm_i915_mem_init_heap_t;
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| 279 |
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| 280 | /* Allow memory manager to be torn down and re-initialized (eg on
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| 281 | * rotate):
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| 282 | */
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| 283 | typedef struct drm_i915_mem_destroy_heap {
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| 284 | int region;
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| 285 | } drm_i915_mem_destroy_heap_t;
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| 286 |
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| 287 | /* Allow X server to configure which pipes to monitor for vblank signals
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| 288 | */
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| 289 | #define DRM_I915_VBLANK_PIPE_A 1
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| 290 | #define DRM_I915_VBLANK_PIPE_B 2
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| 291 |
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| 292 | typedef struct drm_i915_vblank_pipe {
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| 293 | int pipe;
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| 294 | } drm_i915_vblank_pipe_t;
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| 295 |
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| 296 | /* Schedule buffer swap at given vertical blank:
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| 297 | */
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| 298 | typedef struct drm_i915_vblank_swap {
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| 299 | drm_drawable_t drawable;
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| 300 | enum drm_vblank_seq_type seqtype;
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| 301 | unsigned int sequence;
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| 302 | } drm_i915_vblank_swap_t;
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| 303 |
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| 304 | #define I915_MMIO_READ 0
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| 305 | #define I915_MMIO_WRITE 1
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| 306 |
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| 307 | #define I915_MMIO_MAY_READ 0x1
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| 308 | #define I915_MMIO_MAY_WRITE 0x2
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| 309 |
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| 310 | #define MMIO_REGS_IA_PRIMATIVES_COUNT 0
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| 311 | #define MMIO_REGS_IA_VERTICES_COUNT 1
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| 312 | #define MMIO_REGS_VS_INVOCATION_COUNT 2
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| 313 | #define MMIO_REGS_GS_PRIMITIVES_COUNT 3
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| 314 | #define MMIO_REGS_GS_INVOCATION_COUNT 4
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| 315 | #define MMIO_REGS_CL_PRIMITIVES_COUNT 5
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| 316 | #define MMIO_REGS_CL_INVOCATION_COUNT 6
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| 317 | #define MMIO_REGS_PS_INVOCATION_COUNT 7
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| 318 | #define MMIO_REGS_PS_DEPTH_COUNT 8
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| 319 |
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| 320 | typedef struct drm_i915_mmio_entry {
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| 321 | unsigned int flag;
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| 322 | unsigned int offset;
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| 323 | unsigned int size;
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| 324 | } drm_i915_mmio_entry_t;
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| 325 |
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| 326 | typedef struct drm_i915_mmio {
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| 327 | unsigned int read_write:1;
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| 328 | unsigned int reg:31;
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| 329 | void __user *data;
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| 330 | } drm_i915_mmio_t;
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| 331 |
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| 332 | typedef struct drm_i915_hws_addr {
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| 333 | uint64_t addr;
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| 334 | } drm_i915_hws_addr_t;
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| 335 |
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| 336 | #endif /* _I915_DRM_H_ */
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