| 1 | /*
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| 2 | * Copyright 2005 Stephane Marchesin.
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| 3 | * All Rights Reserved.
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| 4 | *
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 6 | * copy of this software and associated documentation files (the "Software"),
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| 7 | * to deal in the Software without restriction, including without limitation
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the
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| 10 | * Software is furnished to do so, subject to the following conditions:
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| 11 | *
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| 12 | * The above copyright notice and this permission notice (including the next
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| 13 | * paragraph) shall be included in all copies or substantial portions of the
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| 14 | * Software.
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| 15 | *
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 22 | * OTHER DEALINGS IN THE SOFTWARE.
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| 23 | */
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| 24 |
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| 25 | #ifndef __NOUVEAU_DRM_H__
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| 26 | #define __NOUVEAU_DRM_H__
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| 27 |
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| 28 | #define NOUVEAU_DRM_HEADER_PATCHLEVEL 15
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| 29 |
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| 30 | struct drm_nouveau_channel_alloc {
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| 31 | uint32_t fb_ctxdma_handle;
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| 32 | uint32_t tt_ctxdma_handle;
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| 33 |
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| 34 | int channel;
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| 35 |
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| 36 | /* Notifier memory */
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| 37 | uint32_t notifier_handle;
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| 38 |
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| 39 | /* DRM-enforced subchannel assignments */
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| 40 | struct {
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| 41 | uint32_t handle;
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| 42 | uint32_t grclass;
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| 43 | } subchan[8];
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| 44 | uint32_t nr_subchan;
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| 45 | };
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| 46 |
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| 47 | struct drm_nouveau_channel_free {
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| 48 | int channel;
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| 49 | };
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| 50 |
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| 51 | struct drm_nouveau_grobj_alloc {
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| 52 | int channel;
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| 53 | uint32_t handle;
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| 54 | int class;
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| 55 | };
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| 56 |
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| 57 | struct drm_nouveau_notifierobj_alloc {
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| 58 | uint32_t channel;
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| 59 | uint32_t handle;
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| 60 | uint32_t size;
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| 61 | uint32_t offset;
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| 62 | };
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| 63 |
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| 64 | struct drm_nouveau_gpuobj_free {
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| 65 | int channel;
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| 66 | uint32_t handle;
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| 67 | };
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| 68 |
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| 69 | /* FIXME : maybe unify {GET,SET}PARAMs */
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| 70 | #define NOUVEAU_GETPARAM_PCI_VENDOR 3
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| 71 | #define NOUVEAU_GETPARAM_PCI_DEVICE 4
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| 72 | #define NOUVEAU_GETPARAM_BUS_TYPE 5
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| 73 | #define NOUVEAU_GETPARAM_FB_PHYSICAL 6
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| 74 | #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
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| 75 | #define NOUVEAU_GETPARAM_FB_SIZE 8
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| 76 | #define NOUVEAU_GETPARAM_AGP_SIZE 9
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| 77 | #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
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| 78 | #define NOUVEAU_GETPARAM_CHIPSET_ID 11
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| 79 | #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
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| 80 | struct drm_nouveau_getparam {
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| 81 | uint64_t param;
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| 82 | uint64_t value;
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| 83 | };
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| 84 |
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| 85 | struct drm_nouveau_setparam {
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| 86 | uint64_t param;
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| 87 | uint64_t value;
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| 88 | };
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| 89 |
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| 90 | #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
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| 91 | #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
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| 92 | #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
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| 93 | #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
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| 94 |
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| 95 | struct drm_nouveau_gem_info {
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| 96 | uint32_t handle;
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| 97 | uint32_t domain;
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| 98 | uint64_t size;
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| 99 | uint64_t offset;
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| 100 | uint64_t map_handle;
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| 101 | uint32_t tile_mode;
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| 102 | uint32_t tile_flags;
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| 103 | };
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| 104 |
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| 105 | struct drm_nouveau_gem_new {
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| 106 | struct drm_nouveau_gem_info info;
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| 107 | uint32_t channel_hint;
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| 108 | uint32_t align;
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| 109 | };
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| 110 |
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| 111 | struct drm_nouveau_gem_pushbuf_bo {
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| 112 | uint64_t user_priv;
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| 113 | uint32_t handle;
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| 114 | uint32_t read_domains;
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| 115 | uint32_t write_domains;
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| 116 | uint32_t valid_domains;
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| 117 | uint32_t presumed_ok;
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| 118 | uint32_t presumed_domain;
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| 119 | uint64_t presumed_offset;
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| 120 | };
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| 121 |
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| 122 | #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
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| 123 | #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
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| 124 | #define NOUVEAU_GEM_RELOC_OR (1 << 2)
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| 125 | struct drm_nouveau_gem_pushbuf_reloc {
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| 126 | uint32_t bo_index;
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| 127 | uint32_t reloc_index;
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| 128 | uint32_t flags;
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| 129 | uint32_t data;
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| 130 | uint32_t vor;
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| 131 | uint32_t tor;
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| 132 | };
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| 133 |
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| 134 | #define NOUVEAU_GEM_MAX_BUFFERS 1024
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| 135 | #define NOUVEAU_GEM_MAX_RELOCS 1024
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| 136 |
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| 137 | struct drm_nouveau_gem_pushbuf {
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| 138 | uint32_t channel;
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| 139 | uint32_t nr_dwords;
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| 140 | uint32_t nr_buffers;
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| 141 | uint32_t nr_relocs;
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| 142 | uint64_t dwords;
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| 143 | uint64_t buffers;
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| 144 | uint64_t relocs;
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| 145 | };
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| 146 |
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| 147 | struct drm_nouveau_gem_pushbuf_call {
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| 148 | uint32_t channel;
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| 149 | uint32_t handle;
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| 150 | uint32_t offset;
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| 151 | uint32_t nr_buffers;
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| 152 | uint32_t nr_relocs;
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| 153 | uint32_t nr_dwords;
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| 154 | uint64_t buffers;
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| 155 | uint64_t relocs;
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| 156 | uint32_t suffix0;
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| 157 | uint32_t suffix1;
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| 158 | };
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| 159 |
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| 160 | struct drm_nouveau_gem_pin {
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| 161 | uint32_t handle;
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| 162 | uint32_t domain;
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| 163 | uint64_t offset;
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| 164 | };
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| 165 |
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| 166 | struct drm_nouveau_gem_unpin {
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| 167 | uint32_t handle;
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| 168 | };
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| 169 |
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| 170 | #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
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| 171 | #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
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| 172 | #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
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| 173 | struct drm_nouveau_gem_cpu_prep {
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| 174 | uint32_t handle;
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| 175 | uint32_t flags;
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| 176 | };
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| 177 |
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| 178 | struct drm_nouveau_gem_cpu_fini {
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| 179 | uint32_t handle;
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| 180 | };
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| 181 |
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| 182 | struct drm_nouveau_gem_tile {
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| 183 | uint32_t handle;
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| 184 | uint32_t offset;
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| 185 | uint32_t size;
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| 186 | uint32_t tile_mode;
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| 187 | uint32_t tile_flags;
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| 188 | };
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| 189 |
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| 190 | enum nouveau_bus_type {
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| 191 | NV_AGP = 0,
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| 192 | NV_PCI = 1,
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| 193 | NV_PCIE = 2,
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| 194 | };
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| 195 |
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| 196 | struct drm_nouveau_sarea {
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| 197 | };
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| 198 |
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| 199 | #define DRM_NOUVEAU_CARD_INIT 0x00
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| 200 | #define DRM_NOUVEAU_GETPARAM 0x01
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| 201 | #define DRM_NOUVEAU_SETPARAM 0x02
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| 202 | #define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
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| 203 | #define DRM_NOUVEAU_CHANNEL_FREE 0x04
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| 204 | #define DRM_NOUVEAU_GROBJ_ALLOC 0x05
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| 205 | #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
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| 206 | #define DRM_NOUVEAU_GPUOBJ_FREE 0x07
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| 207 | #define DRM_NOUVEAU_GEM_NEW 0x40
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| 208 | #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
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| 209 | #define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42
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| 210 | #define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */
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| 211 | #define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */
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| 212 | #define DRM_NOUVEAU_GEM_CPU_PREP 0x45
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| 213 | #define DRM_NOUVEAU_GEM_CPU_FINI 0x46
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| 214 | #define DRM_NOUVEAU_GEM_INFO 0x47
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| 215 |
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| 216 | #endif /* __NOUVEAU_DRM_H__ */
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