1 | /* savage_drm.h -- Public header for the savage driver
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2 | *
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3 | * Copyright 2004 Felix Kuehling
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4 | * All Rights Reserved.
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5 | *
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6 | * Permission is hereby granted, free of charge, to any person obtaining a
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7 | * copy of this software and associated documentation files (the "Software"),
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8 | * to deal in the Software without restriction, including without limitation
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9 | * the rights to use, copy, modify, merge, publish, distribute, sub license,
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10 | * and/or sell copies of the Software, and to permit persons to whom the
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11 | * Software is furnished to do so, subject to the following conditions:
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12 | *
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13 | * The above copyright notice and this permission notice (including the
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14 | * next paragraph) shall be included in all copies or substantial portions
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15 | * of the Software.
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16 | *
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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20 | * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
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21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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22 | * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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24 | */
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25 |
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26 | #ifndef __SAVAGE_DRM_H__
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27 | #define __SAVAGE_DRM_H__
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28 |
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29 | #ifndef __SAVAGE_SAREA_DEFINES__
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30 | #define __SAVAGE_SAREA_DEFINES__
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31 |
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32 | /* 2 heaps (1 for card, 1 for agp), each divided into upto 128
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33 | * regions, subject to a minimum region size of (1<<16) == 64k.
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34 | *
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35 | * Clients may subdivide regions internally, but when sharing between
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36 | * clients, the region size is the minimum granularity.
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37 | */
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38 |
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39 | #define SAVAGE_CARD_HEAP 0
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40 | #define SAVAGE_AGP_HEAP 1
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41 | #define SAVAGE_NR_TEX_HEAPS 2
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42 | #define SAVAGE_NR_TEX_REGIONS 16
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43 | #define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
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44 |
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45 | #endif /* __SAVAGE_SAREA_DEFINES__ */
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46 |
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47 | typedef struct _drm_savage_sarea {
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48 | /* LRU lists for texture memory in agp space and on the card.
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49 | */
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50 | struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1];
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51 | unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
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52 |
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53 | /* Mechanism to validate card state.
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54 | */
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55 | int ctxOwner;
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56 | } drm_savage_sarea_t, *drm_savage_sarea_ptr;
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57 |
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58 | /* Savage-specific ioctls
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59 | */
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60 | #define DRM_SAVAGE_BCI_INIT 0x00
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61 | #define DRM_SAVAGE_BCI_CMDBUF 0x01
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62 | #define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
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63 | #define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
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64 |
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65 | #define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
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66 | #define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
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67 | #define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
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68 | #define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
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69 |
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70 | #define SAVAGE_DMA_PCI 1
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71 | #define SAVAGE_DMA_AGP 3
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72 | typedef struct drm_savage_init {
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73 | enum {
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74 | SAVAGE_INIT_BCI = 1,
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75 | SAVAGE_CLEANUP_BCI = 2
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76 | } func;
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77 | unsigned int sarea_priv_offset;
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78 |
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79 | /* some parameters */
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80 | unsigned int cob_size;
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81 | unsigned int bci_threshold_lo, bci_threshold_hi;
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82 | unsigned int dma_type;
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83 |
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84 | /* frame buffer layout */
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85 | unsigned int fb_bpp;
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86 | unsigned int front_offset, front_pitch;
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87 | unsigned int back_offset, back_pitch;
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88 | unsigned int depth_bpp;
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89 | unsigned int depth_offset, depth_pitch;
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90 |
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91 | /* local textures */
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92 | unsigned int texture_offset;
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93 | unsigned int texture_size;
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94 |
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95 | /* physical locations of non-permanent maps */
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96 | unsigned long status_offset;
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97 | unsigned long buffers_offset;
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98 | unsigned long agp_textures_offset;
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99 | unsigned long cmd_dma_offset;
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100 | } drm_savage_init_t;
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101 |
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102 | typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
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103 | typedef struct drm_savage_cmdbuf {
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104 | /* command buffer in client's address space */
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105 | drm_savage_cmd_header_t __user *cmd_addr;
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106 | unsigned int size; /* size of the command buffer in 64bit units */
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107 |
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108 | unsigned int dma_idx; /* DMA buffer index to use */
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109 | int discard; /* discard DMA buffer when done */
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110 | /* vertex buffer in client's address space */
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111 | unsigned int __user *vb_addr;
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112 | unsigned int vb_size; /* size of client vertex buffer in bytes */
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113 | unsigned int vb_stride; /* stride of vertices in 32bit words */
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114 | /* boxes in client's address space */
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115 | struct drm_clip_rect __user *box_addr;
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116 | unsigned int nbox; /* number of clipping boxes */
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117 | } drm_savage_cmdbuf_t;
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118 |
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119 | #define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */
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120 | #define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */
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121 | #define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
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122 | typedef struct drm_savage_event {
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123 | unsigned int count;
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124 | unsigned int flags;
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125 | } drm_savage_event_emit_t, drm_savage_event_wait_t;
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126 |
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127 | /* Commands for the cmdbuf ioctl
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128 | */
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129 | #define SAVAGE_CMD_STATE 0 /* a range of state registers */
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130 | #define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */
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131 | #define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */
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132 | #define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */
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133 | #define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */
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134 | #define SAVAGE_CMD_CLEAR 5 /* clear buffers */
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135 | #define SAVAGE_CMD_SWAP 6 /* swap buffers */
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136 |
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137 | /* Primitive types
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138 | */
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139 | #define SAVAGE_PRIM_TRILIST 0 /* triangle list */
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140 | #define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */
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141 | #define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */
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142 | #define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat
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143 | * shading on s3d */
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144 |
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145 | /* Skip flags (vertex format)
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146 | */
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147 | #define SAVAGE_SKIP_Z 0x01
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148 | #define SAVAGE_SKIP_W 0x02
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149 | #define SAVAGE_SKIP_C0 0x04
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150 | #define SAVAGE_SKIP_C1 0x08
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151 | #define SAVAGE_SKIP_S0 0x10
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152 | #define SAVAGE_SKIP_T0 0x20
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153 | #define SAVAGE_SKIP_ST0 0x30
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154 | #define SAVAGE_SKIP_S1 0x40
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155 | #define SAVAGE_SKIP_T1 0x80
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156 | #define SAVAGE_SKIP_ST1 0xc0
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157 | #define SAVAGE_SKIP_ALL_S3D 0x3f
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158 | #define SAVAGE_SKIP_ALL_S4 0xff
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159 |
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160 | /* Buffer names for clear command
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161 | */
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162 | #define SAVAGE_FRONT 0x1
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163 | #define SAVAGE_BACK 0x2
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164 | #define SAVAGE_DEPTH 0x4
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165 |
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166 | /* 64-bit command header
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167 | */
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168 | union drm_savage_cmd_header {
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169 | struct {
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170 | unsigned char cmd; /* command */
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171 | unsigned char pad0;
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172 | unsigned short pad1;
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173 | unsigned short pad2;
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174 | unsigned short pad3;
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175 | } cmd; /* generic */
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176 | struct {
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177 | unsigned char cmd;
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178 | unsigned char global; /* need idle engine? */
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179 | unsigned short count; /* number of consecutive registers */
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180 | unsigned short start; /* first register */
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181 | unsigned short pad3;
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182 | } state; /* SAVAGE_CMD_STATE */
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183 | struct {
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184 | unsigned char cmd;
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185 | unsigned char prim; /* primitive type */
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186 | unsigned short skip; /* vertex format (skip flags) */
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187 | unsigned short count; /* number of vertices */
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188 | unsigned short start; /* first vertex in DMA/vertex buffer */
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189 | } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
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190 | struct {
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191 | unsigned char cmd;
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192 | unsigned char prim;
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193 | unsigned short skip;
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194 | unsigned short count; /* number of indices that follow */
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195 | unsigned short pad3;
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196 | } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
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197 | struct {
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198 | unsigned char cmd;
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199 | unsigned char pad0;
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200 | unsigned short pad1;
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201 | unsigned int flags;
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202 | } clear0; /* SAVAGE_CMD_CLEAR */
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203 | struct {
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204 | unsigned int mask;
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205 | unsigned int value;
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206 | } clear1; /* SAVAGE_CMD_CLEAR data */
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207 | };
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208 |
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209 | #endif
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