| 1 | /** @file
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| 2 | The file lists the PCI class codes only defined in PCI code and ID assignment specification
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| 3 | revision 1.3.
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| 4 |
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| 5 | Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
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| 6 | This program and the accompanying materials
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| 7 | are licensed and made available under the terms and conditions of the BSD License
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| 8 | which accompanies this distribution. The full text of the license may be found at
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| 9 | http://opensource.org/licenses/bsd-license.php
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| 10 |
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| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 13 |
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| 14 | **/
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| 15 |
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| 16 | #ifndef __PCI_CODE_ID_H__
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| 17 | #define __PCI_CODE_ID_H__
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| 18 |
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| 19 |
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| 20 | ///
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| 21 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.
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| 22 | ///
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| 23 | ///@{
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| 24 | #define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
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| 25 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
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| 26 | #define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
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| 27 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
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| 28 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
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| 29 | #define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
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| 30 | #define PCI_CLASS_MASS_STORAGE_SAS 0x07
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| 31 | #define PCI_IF_MASS_STORAGE_SAS 0x00
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| 32 | #define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
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| 33 | #define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
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| 34 | #define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
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| 35 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
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| 36 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
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| 37 | ///@}
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| 38 |
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| 39 | ///
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| 40 | /// PCI_CLASS_NETWORK, Base Class 02h.
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| 41 | ///
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| 42 | ///@{
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| 43 | #define PCI_CLASS_NETWORK_INFINIBAND 0x07
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| 44 | ///@}
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| 45 |
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| 46 | ///
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| 47 | /// PCI_CLASS_MEDIA, Base Class 04h.
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| 48 | ///
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| 49 | ///@{
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| 50 | #define PCI_CLASS_MEDIA_MIXED_MODE 0x03
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| 51 | ///@}
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| 52 |
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| 53 | ///
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| 54 | /// PCI_CLASS_BRIDGE, Base Class 06h.
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| 55 | ///
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| 56 | ///@{
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| 57 | #define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
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| 58 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
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| 59 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
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| 60 | ///@}
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| 61 |
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| 62 | ///
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| 63 | /// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.
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| 64 | ///
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| 65 | ///@{
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| 66 | #define PCI_IF_HPET 0x03
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| 67 | #define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
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| 68 | #define PCI_SUBCLASS_IOMMU 0x06
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| 69 | ///@}
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| 70 |
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| 71 | ///
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| 72 | /// PCI_CLASS_PROCESSOR, Base Class 0Bh.
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| 73 | ///
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| 74 | ///@{
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| 75 | #define PCI_SUBCLASS_PROC_OTHER 0x80
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| 76 | ///@}
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| 77 |
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| 78 | ///
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| 79 | /// PCI_CLASS_SERIAL, Base Class 0Ch.
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| 80 | ///
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| 81 | ///@{
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| 82 | #define PCI_IF_XHCI 0x30
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| 83 | #define PCI_CLASS_SERIAL_OTHER 0x80
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| 84 | ///@}
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| 85 |
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| 86 | ///
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| 87 | /// PCI_CLASS_SATELLITE, Base Class 0Fh.
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| 88 | ///
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| 89 | ///@{
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| 90 | #define PCI_SUBCLASS_SATELLITE_OTHER 0x80
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| 91 | ///@}
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| 92 |
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| 93 | ///
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| 94 | /// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.
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| 95 | ///
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| 96 | ///@{
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| 97 | #define PCI_CLASS_PROCESSING_ACCELERATOR 0x12
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| 98 | ///@}
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| 99 |
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| 100 | #endif
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