| 1 | /** @file
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| 2 | Support for the latest PCI standard.
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| 3 |
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| 4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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| 5 | This program and the accompanying materials
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| 6 | are licensed and made available under the terms and conditions of the BSD License
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| 7 | which accompanies this distribution. The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 | **/
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| 14 |
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| 15 | #ifndef _PCIEXPRESS21_H_
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| 16 | #define _PCIEXPRESS21_H_
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| 17 |
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| 18 | #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
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| 19 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
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| 20 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
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| 21 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
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| 22 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
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| 23 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
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| 24 |
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| 25 | //
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| 26 | // for SR-IOV
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| 27 | //
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| 28 | #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
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| 29 | #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
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| 30 | #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
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| 31 | #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
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| 32 |
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| 33 | typedef struct {
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| 34 | UINT32 CapabilityHeader;
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| 35 | UINT32 Capability;
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| 36 | UINT16 Control;
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| 37 | UINT16 Status;
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| 38 | UINT16 InitialVFs;
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| 39 | UINT16 TotalVFs;
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| 40 | UINT16 NumVFs;
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| 41 | UINT8 FunctionDependencyLink;
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| 42 | UINT8 Reserved0;
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| 43 | UINT16 FirstVFOffset;
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| 44 | UINT16 VFStride;
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| 45 | UINT16 Reserved1;
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| 46 | UINT16 VFDeviceID;
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| 47 | UINT32 SupportedPageSize;
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| 48 | UINT32 SystemPageSize;
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| 49 | UINT32 VFBar[6];
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| 50 | UINT32 VFMigrationStateArrayOffset;
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| 51 | } SR_IOV_CAPABILITY_REGISTER;
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| 52 |
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| 53 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
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| 54 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
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| 55 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
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| 56 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
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| 57 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
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| 58 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
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| 59 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
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| 60 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
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| 61 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
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| 62 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
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| 63 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
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| 64 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
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| 65 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
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| 66 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
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| 67 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
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| 68 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
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| 69 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
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| 70 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
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| 71 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
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| 72 |
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| 73 | typedef struct {
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| 74 | UINT32 CapabilityId:16;
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| 75 | UINT32 CapabilityVersion:4;
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| 76 | UINT32 NextCapabilityOffset:12;
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| 77 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
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| 78 |
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| 79 | #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
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| 80 |
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| 81 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
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| 82 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
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| 83 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
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| 84 |
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| 85 | typedef struct {
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| 86 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 87 | UINT32 UncorrectableErrorStatus;
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| 88 | UINT32 UncorrectableErrorMask;
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| 89 | UINT32 UncorrectableErrorSeverity;
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| 90 | UINT32 CorrectableErrorStatus;
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| 91 | UINT32 CorrectableErrorMask;
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| 92 | UINT32 AdvancedErrorCapabilitiesAndControl;
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| 93 | UINT32 HeaderLog;
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| 94 | UINT32 RootErrorCommand;
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| 95 | UINT32 RootErrorStatus;
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| 96 | UINT16 ErrorSourceIdentification;
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| 97 | UINT16 CorrectableErrorSourceIdentification;
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| 98 | UINT32 TlpPrefixLog[4];
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| 99 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
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| 100 |
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| 101 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
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| 102 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
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| 103 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
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| 104 |
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| 105 | typedef struct {
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| 106 | UINT32 VcResourceCapability:24;
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| 107 | UINT32 PortArbTableOffset:8;
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| 108 | UINT32 VcResourceControl;
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| 109 | UINT16 Reserved1;
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| 110 | UINT16 VcResourceStatus;
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| 111 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
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| 112 |
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| 113 | typedef struct {
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| 114 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 115 | UINT32 ExtendedVcCount:3;
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| 116 | UINT32 PortVcCapability1:29;
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| 117 | UINT32 PortVcCapability2:24;
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| 118 | UINT32 VcArbTableOffset:8;
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| 119 | UINT16 PortVcControl;
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| 120 | UINT16 PortVcStatus;
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| 121 | PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];
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| 122 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
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| 123 |
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| 124 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
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| 125 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
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| 126 |
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| 127 | typedef struct {
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| 128 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 129 | UINT64 SerialNumber;
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| 130 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
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| 131 |
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| 132 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
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| 133 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
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| 134 |
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| 135 | typedef struct {
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| 136 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 137 | UINT32 ElementSelfDescription;
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| 138 | UINT32 Reserved;
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| 139 | UINT32 LinkEntry[1];
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| 140 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
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| 141 |
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| 142 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
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| 143 |
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| 144 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
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| 145 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
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| 146 |
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| 147 | typedef struct {
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| 148 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 149 | UINT32 RootComplexLinkCapabilities;
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| 150 | UINT16 RootComplexLinkControl;
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| 151 | UINT16 RootComplexLinkStatus;
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| 152 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
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| 153 |
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| 154 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
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| 155 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
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| 156 |
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| 157 | typedef struct {
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| 158 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 159 | UINT32 DataSelect:8;
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| 160 | UINT32 Reserved:24;
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| 161 | UINT32 Data;
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| 162 | UINT32 PowerBudgetCapability:1;
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| 163 | UINT32 Reserved2:7;
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| 164 | UINT32 Reserved3:24;
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| 165 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
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| 166 |
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| 167 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
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| 168 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
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| 169 |
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| 170 | typedef struct {
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| 171 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 172 | UINT16 AcsCapability;
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| 173 | UINT16 AcsControl;
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| 174 | UINT8 EgressControlVectorArray[1];
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| 175 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
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| 176 |
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| 177 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
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| 178 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
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| 179 |
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| 180 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
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| 181 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
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| 182 |
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| 183 | typedef struct {
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| 184 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 185 | UINT32 AssociationBitmap;
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| 186 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
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| 187 |
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| 188 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
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| 189 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
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| 190 |
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| 191 | typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
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| 192 |
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| 193 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
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| 194 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
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| 195 |
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| 196 | typedef struct {
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| 197 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 198 | UINT32 VendorSpecificHeader;
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| 199 | UINT8 VendorSpecific[1];
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| 200 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
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| 201 |
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| 202 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
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| 203 |
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| 204 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
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| 205 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
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| 206 |
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| 207 | typedef struct {
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| 208 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 209 | UINT16 VendorId;
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| 210 | UINT16 DeviceId;
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| 211 | UINT32 RcrbCapabilities;
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| 212 | UINT32 RcrbControl;
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| 213 | UINT32 Reserved;
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| 214 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
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| 215 |
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| 216 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
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| 217 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
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| 218 |
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| 219 | typedef struct {
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| 220 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 221 | UINT16 MultiCastCapability;
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| 222 | UINT16 MulticastControl;
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| 223 | UINT64 McBaseAddress;
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| 224 | UINT64 McReceiveAddress;
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| 225 | UINT64 McBlockAll;
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| 226 | UINT64 McBlockUntranslated;
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| 227 | UINT64 McOverlayBar;
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| 228 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
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| 229 |
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| 230 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
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| 231 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
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| 232 |
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| 233 | typedef struct {
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| 234 | UINT32 ResizableBarCapability;
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| 235 | UINT16 ResizableBarControl;
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| 236 | UINT16 Reserved;
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| 237 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
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| 238 |
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| 239 | typedef struct {
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| 240 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 241 | PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];
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| 242 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
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| 243 |
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| 244 | #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
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| 245 |
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| 246 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
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| 247 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
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| 248 |
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| 249 | typedef struct {
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| 250 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 251 | UINT16 AriCapability;
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| 252 | UINT16 AriControl;
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| 253 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
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| 254 |
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| 255 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
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| 256 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
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| 257 |
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| 258 | typedef struct {
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| 259 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 260 | UINT32 DpaCapability;
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| 261 | UINT32 DpaLatencyIndicator;
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| 262 | UINT16 DpaStatus;
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| 263 | UINT16 DpaControl;
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| 264 | UINT8 DpaPowerAllocationArray[1];
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| 265 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
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| 266 |
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| 267 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
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| 268 |
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| 269 |
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| 270 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
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| 271 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
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| 272 |
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| 273 | typedef struct {
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| 274 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 275 | UINT16 MaxSnoopLatency;
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| 276 | UINT16 MaxNoSnoopLatency;
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| 277 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
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| 278 |
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| 279 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
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| 280 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
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| 281 |
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| 282 | typedef struct {
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| 283 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 284 | UINT32 TphRequesterCapability;
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| 285 | UINT32 TphRequesterControl;
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| 286 | UINT16 TphStTable[1];
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| 287 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
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| 288 |
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| 289 | #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
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| 290 |
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| 291 | #endif
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