| 1 | /** @file
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| 2 | This file contains definitions for the SPD fields on an SDRAM.
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| 3 |
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| 4 | Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
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| 5 | This program and the accompanying materials
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| 6 | are licensed and made available under the terms and conditions of the BSD License
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| 7 | which accompanies this distribution. The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 | **/
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| 13 |
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| 14 | #ifndef _SDRAM_SPD_H_
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| 15 | #define _SDRAM_SPD_H_
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| 16 |
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| 17 | //
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| 18 | // SDRAM SPD field definitions
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| 19 | //
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| 20 | #define SPD_MEMORY_TYPE 2
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| 21 | #define SPD_SDRAM_ROW_ADDR 3
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| 22 | #define SPD_SDRAM_COL_ADDR 4
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| 23 | #define SPD_SDRAM_MODULE_ROWS 5
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| 24 | #define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
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| 25 | #define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
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| 26 | #define SPD_SDRAM_ECC_SUPPORT 11
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| 27 | #define SPD_SDRAM_REFRESH 12
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| 28 | #define SPD_SDRAM_WIDTH 13
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| 29 | #define SPD_SDRAM_ERROR_WIDTH 14
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| 30 | #define SPD_SDRAM_BURST_LENGTH 16
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| 31 | #define SPD_SDRAM_NO_OF_BANKS 17
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| 32 | #define SPD_SDRAM_CAS_LATENCY 18
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| 33 | #define SPD_SDRAM_MODULE_ATTR 21
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| 34 |
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| 35 | #define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency
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| 36 | #define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency
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| 37 | #define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency
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| 38 | #define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency
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| 39 | #define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency
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| 40 | #define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency
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| 41 | #define SPD_SDRAM_MIN_PRECHARGE 27
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| 42 | #define SPD_SDRAM_ACTIVE_MIN 28
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| 43 | #define SPD_SDRAM_RAS_CAS 29
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| 44 | #define SPD_SDRAM_RAS_PULSE 30
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| 45 | #define SPD_SDRAM_DENSITY 31
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| 46 |
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| 47 | //
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| 48 | // Memory Type Definitions
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| 49 | //
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| 50 | #define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory
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| 51 | #define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory
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| 52 | #define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory
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| 53 | //
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| 54 | // ECC Type Definitions
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| 55 | //
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| 56 | #define SPD_ECC_TYPE_NONE 0x00 ///< No error checking
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| 57 | #define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking
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| 58 | #define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only
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| 59 | //
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| 60 | // Module Attributes (Bit positions)
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| 61 | //
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| 62 | #define SPD_BUFFERED 0x01
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| 63 | #define SPD_REGISTERED 0x02
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| 64 |
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| 65 | #endif
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