PciExpressLib.h@ 105681

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1	/** @file
2	Provides services to access PCI Configuration Space using the MMIO PCI Express window.
3
4	This library is identical to the PCI Library, except the access method for performing PCI
5	configuration cycles must be through the PCI Express MMIO window whose base address
6	is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.
7
8
9	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
10	SPDX-License-Identifier: BSD-2-Clause-Patent
11
12	**/
13
14	#ifndef __PCI_EXPRESS_LIB_H__
15	#define __PCI_EXPRESS_LIB_H__
16
17	#include <IndustryStandard/PciExpress21.h>
18
19	/**
20	Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
21	address that can be passed to the PCI Library functions.
22
23	Computes an address that is compatible with the PCI Library functions. The
24	unused upper bits of Bus, Device, Function and Register are stripped prior to
25	the generation of the address.
26
27	@param Bus PCI Bus number. Range 0..255.
28	@param Device PCI Device number. Range 0..31.
29	@param Function PCI Function number. Range 0..7.
30	@param Register PCI Register number. Range 0..4095.
31
32	@return The encode PCI address.
33
34	**/
35	#define PCI_EXPRESS_LIB_ADDRESS(Bus, Device, Function, Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
36
37	/**
38	Registers a PCI device so PCI configuration registers may be accessed after
39	SetVirtualAddressMap().
40
41	Registers the PCI device specified by Address so all the PCI configuration
42	registers associated with that PCI device may be accessed after SetVirtualAddressMap()
43	is called.
44
45	If Address > 0x0FFFFFFF, then ASSERT().
46
47	@param Address Address that encodes the PCI Bus, Device, Function and
48	Register.
49
50	@retval RETURN_SUCCESS The PCI device was registered for runtime access.
51	@retval RETURN_UNSUPPORTED An attempt was made to call this function
52	after ExitBootServices().
53	@retval RETURN_UNSUPPORTED The resources required to access the PCI device
54	at runtime could not be mapped.
55	@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
56	complete the registration.
57
58	**/
59	RETURN_STATUS
60	EFIAPI
61	PciExpressRegisterForRuntimeAccess (
62	IN UINTN Address
63	);
64
65	/**
66	Reads an 8-bit PCI configuration register.
67
68	Reads and returns the 8-bit PCI configuration register specified by Address.
69	This function must guarantee that all PCI read and write operations are
70	serialized.
71
72	If Address > 0x0FFFFFFF, then ASSERT().
73
74	@param Address Address that encodes the PCI Bus, Device, Function and
75	Register.
76
77	@return The read value from the PCI configuration register.
78
79	**/
80	UINT8
81	EFIAPI
82	PciExpressRead8 (
83	IN UINTN Address
84	);
85
86	/**
87	Writes an 8-bit PCI configuration register.
88
89	Writes the 8-bit PCI configuration register specified by Address with the
90	value specified by Value. Value is returned. This function must guarantee
91	that all PCI read and write operations are serialized.
92
93	If Address > 0x0FFFFFFF, then ASSERT().
94
95	@param Address Address that encodes the PCI Bus, Device, Function and
96	Register.
97	@param Value The value to write.
98
99	@return The value written to the PCI configuration register.
100
101	**/
102	UINT8
103	EFIAPI
104	PciExpressWrite8 (
105	IN UINTN Address,
106	IN UINT8 Value
107	);
108
109	/**
110	Performs a bitwise OR of an 8-bit PCI configuration register with
111	an 8-bit value.
112
113	Reads the 8-bit PCI configuration register specified by Address, performs a
114	bitwise OR between the read result and the value specified by
115	OrData, and writes the result to the 8-bit PCI configuration register
116	specified by Address. The value written to the PCI configuration register is
117	returned. This function must guarantee that all PCI read and write operations
118	are serialized.
119
120	If Address > 0x0FFFFFFF, then ASSERT().
121
122	@param Address Address that encodes the PCI Bus, Device, Function and
123	Register.
124	@param OrData The value to OR with the PCI configuration register.
125
126	@return The value written back to the PCI configuration register.
127
128	**/
129	UINT8
130	EFIAPI
131	PciExpressOr8 (
132	IN UINTN Address,
133	IN UINT8 OrData
134	);
135
136	/**
137	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
138	value.
139
140	Reads the 8-bit PCI configuration register specified by Address, performs a
141	bitwise AND between the read result and the value specified by AndData, and
142	writes the result to the 8-bit PCI configuration register specified by
143	Address. The value written to the PCI configuration register is returned.
144	This function must guarantee that all PCI read and write operations are
145	serialized.
146
147	If Address > 0x0FFFFFFF, then ASSERT().
148
149	@param Address Address that encodes the PCI Bus, Device, Function and
150	Register.
151	@param AndData The value to AND with the PCI configuration register.
152
153	@return The value written back to the PCI configuration register.
154
155	**/
156	UINT8
157	EFIAPI
158	PciExpressAnd8 (
159	IN UINTN Address,
160	IN UINT8 AndData
161	);
162
163	/**
164	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
165	value, followed a bitwise OR with another 8-bit value.
166
167	Reads the 8-bit PCI configuration register specified by Address, performs a
168	bitwise AND between the read result and the value specified by AndData,
169	performs a bitwise OR between the result of the AND operation and
170	the value specified by OrData, and writes the result to the 8-bit PCI
171	configuration register specified by Address. The value written to the PCI
172	configuration register is returned. This function must guarantee that all PCI
173	read and write operations are serialized.
174
175	If Address > 0x0FFFFFFF, then ASSERT().
176
177	@param Address Address that encodes the PCI Bus, Device, Function and
178	Register.
179	@param AndData The value to AND with the PCI configuration register.
180	@param OrData The value to OR with the result of the AND operation.
181
182	@return The value written back to the PCI configuration register.
183
184	**/
185	UINT8
186	EFIAPI
187	PciExpressAndThenOr8 (
188	IN UINTN Address,
189	IN UINT8 AndData,
190	IN UINT8 OrData
191	);
192
193	/**
194	Reads a bit field of a PCI configuration register.
195
196	Reads the bit field in an 8-bit PCI configuration register. The bit field is
197	specified by the StartBit and the EndBit. The value of the bit field is
198	returned.
199
200	If Address > 0x0FFFFFFF, then ASSERT().
201	If StartBit is greater than 7, then ASSERT().
202	If EndBit is greater than 7, then ASSERT().
203	If EndBit is less than StartBit, then ASSERT().
204
205	@param Address PCI configuration register to read.
206	@param StartBit The ordinal of the least significant bit in the bit field.
207	Range 0..7.
208	@param EndBit The ordinal of the most significant bit in the bit field.
209	Range 0..7.
210
211	@return The value of the bit field read from the PCI configuration register.
212
213	**/
214	UINT8
215	EFIAPI
216	PciExpressBitFieldRead8 (
217	IN UINTN Address,
218	IN UINTN StartBit,
219	IN UINTN EndBit
220	);
221
222	/**
223	Writes a bit field to a PCI configuration register.
224
225	Writes Value to the bit field of the PCI configuration register. The bit
226	field is specified by the StartBit and the EndBit. All other bits in the
227	destination PCI configuration register are preserved. The new value of the
228	8-bit register is returned.
229
230	If Address > 0x0FFFFFFF, then ASSERT().
231	If StartBit is greater than 7, then ASSERT().
232	If EndBit is greater than 7, then ASSERT().
233	If EndBit is less than StartBit, then ASSERT().
234	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
235
236	@param Address PCI configuration register to write.
237	@param StartBit The ordinal of the least significant bit in the bit field.
238	Range 0..7.
239	@param EndBit The ordinal of the most significant bit in the bit field.
240	Range 0..7.
241	@param Value New value of the bit field.
242
243	@return The value written back to the PCI configuration register.
244
245	**/
246	UINT8
247	EFIAPI
248	PciExpressBitFieldWrite8 (
249	IN UINTN Address,
250	IN UINTN StartBit,
251	IN UINTN EndBit,
252	IN UINT8 Value
253	);
254
255	/**
256	Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
257	writes the result back to the bit field in the 8-bit port.
258
259	Reads the 8-bit PCI configuration register specified by Address, performs a
260	bitwise OR between the read result and the value specified by
261	OrData, and writes the result to the 8-bit PCI configuration register
262	specified by Address. The value written to the PCI configuration register is
263	returned. This function must guarantee that all PCI read and write operations
264	are serialized. Extra left bits in OrData are stripped.
265
266	If Address > 0x0FFFFFFF, then ASSERT().
267	If StartBit is greater than 7, then ASSERT().
268	If EndBit is greater than 7, then ASSERT().
269	If EndBit is less than StartBit, then ASSERT().
270	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
271
272	@param Address PCI configuration register to write.
273	@param StartBit The ordinal of the least significant bit in the bit field.
274	Range 0..7.
275	@param EndBit The ordinal of the most significant bit in the bit field.
276	Range 0..7.
277	@param OrData The value to OR with the PCI configuration register.
278
279	@return The value written back to the PCI configuration register.
280
281	**/
282	UINT8
283	EFIAPI
284	PciExpressBitFieldOr8 (
285	IN UINTN Address,
286	IN UINTN StartBit,
287	IN UINTN EndBit,
288	IN UINT8 OrData
289	);
290
291	/**
292	Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
293	AND, and writes the result back to the bit field in the 8-bit register.
294
295	Reads the 8-bit PCI configuration register specified by Address, performs a
296	bitwise AND between the read result and the value specified by AndData, and
297	writes the result to the 8-bit PCI configuration register specified by
298	Address. The value written to the PCI configuration register is returned.
299	This function must guarantee that all PCI read and write operations are
300	serialized. Extra left bits in AndData are stripped.
301
302	If Address > 0x0FFFFFFF, then ASSERT().
303	If StartBit is greater than 7, then ASSERT().
304	If EndBit is greater than 7, then ASSERT().
305	If EndBit is less than StartBit, then ASSERT().
306	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
307
308	@param Address PCI configuration register to write.
309	@param StartBit The ordinal of the least significant bit in the bit field.
310	Range 0..7.
311	@param EndBit The ordinal of the most significant bit in the bit field.
312	Range 0..7.
313	@param AndData The value to AND with the PCI configuration register.
314
315	@return The value written back to the PCI configuration register.
316
317	**/
318	UINT8
319	EFIAPI
320	PciExpressBitFieldAnd8 (
321	IN UINTN Address,
322	IN UINTN StartBit,
323	IN UINTN EndBit,
324	IN UINT8 AndData
325	);
326
327	/**
328	Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
329	bitwise OR, and writes the result back to the bit field in the
330	8-bit port.
331
332	Reads the 8-bit PCI configuration register specified by Address, performs a
333	bitwise AND followed by a bitwise OR between the read result and
334	the value specified by AndData, and writes the result to the 8-bit PCI
335	configuration register specified by Address. The value written to the PCI
336	configuration register is returned. This function must guarantee that all PCI
337	read and write operations are serialized. Extra left bits in both AndData and
338	OrData are stripped.
339
340	If Address > 0x0FFFFFFF, then ASSERT().
341	If StartBit is greater than 7, then ASSERT().
342	If EndBit is greater than 7, then ASSERT().
343	If EndBit is less than StartBit, then ASSERT().
344	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
345	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
346
347	@param Address PCI configuration register to write.
348	@param StartBit The ordinal of the least significant bit in the bit field.
349	Range 0..7.
350	@param EndBit The ordinal of the most significant bit in the bit field.
351	Range 0..7.
352	@param AndData The value to AND with the PCI configuration register.
353	@param OrData The value to OR with the result of the AND operation.
354
355	@return The value written back to the PCI configuration register.
356
357	**/
358	UINT8
359	EFIAPI
360	PciExpressBitFieldAndThenOr8 (
361	IN UINTN Address,
362	IN UINTN StartBit,
363	IN UINTN EndBit,
364	IN UINT8 AndData,
365	IN UINT8 OrData
366	);
367
368	/**
369	Reads a 16-bit PCI configuration register.
370
371	Reads and returns the 16-bit PCI configuration register specified by Address.
372	This function must guarantee that all PCI read and write operations are
373	serialized.
374
375	If Address > 0x0FFFFFFF, then ASSERT().
376	If Address is not aligned on a 16-bit boundary, then ASSERT().
377
378	@param Address Address that encodes the PCI Bus, Device, Function and
379	Register.
380
381	@return The read value from the PCI configuration register.
382
383	**/
384	UINT16
385	EFIAPI
386	PciExpressRead16 (
387	IN UINTN Address
388	);
389
390	/**
391	Writes a 16-bit PCI configuration register.
392
393	Writes the 16-bit PCI configuration register specified by Address with the
394	value specified by Value. Value is returned. This function must guarantee
395	that all PCI read and write operations are serialized.
396
397	If Address > 0x0FFFFFFF, then ASSERT().
398	If Address is not aligned on a 16-bit boundary, then ASSERT().
399
400	@param Address Address that encodes the PCI Bus, Device, Function and
401	Register.
402	@param Value The value to write.
403
404	@return The value written to the PCI configuration register.
405
406	**/
407	UINT16
408	EFIAPI
409	PciExpressWrite16 (
410	IN UINTN Address,
411	IN UINT16 Value
412	);
413
414	/**
415	Performs a bitwise OR of a 16-bit PCI configuration register with
416	a 16-bit value.
417
418	Reads the 16-bit PCI configuration register specified by Address, performs a
419	bitwise OR between the read result and the value specified by
420	OrData, and writes the result to the 16-bit PCI configuration register
421	specified by Address. The value written to the PCI configuration register is
422	returned. This function must guarantee that all PCI read and write operations
423	are serialized.
424
425	If Address > 0x0FFFFFFF, then ASSERT().
426	If Address is not aligned on a 16-bit boundary, then ASSERT().
427
428	@param Address Address that encodes the PCI Bus, Device, Function and
429	Register.
430	@param OrData The value to OR with the PCI configuration register.
431
432	@return The value written back to the PCI configuration register.
433
434	**/
435	UINT16
436	EFIAPI
437	PciExpressOr16 (
438	IN UINTN Address,
439	IN UINT16 OrData
440	);
441
442	/**
443	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
444	value.
445
446	Reads the 16-bit PCI configuration register specified by Address, performs a
447	bitwise AND between the read result and the value specified by AndData, and
448	writes the result to the 16-bit PCI configuration register specified by
449	Address. The value written to the PCI configuration register is returned.
450	This function must guarantee that all PCI read and write operations are
451	serialized.
452
453	If Address > 0x0FFFFFFF, then ASSERT().
454	If Address is not aligned on a 16-bit boundary, then ASSERT().
455
456	@param Address Address that encodes the PCI Bus, Device, Function and
457	Register.
458	@param AndData The value to AND with the PCI configuration register.
459
460	@return The value written back to the PCI configuration register.
461
462	**/
463	UINT16
464	EFIAPI
465	PciExpressAnd16 (
466	IN UINTN Address,
467	IN UINT16 AndData
468	);
469
470	/**
471	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
472	value, followed a bitwise OR with another 16-bit value.
473
474	Reads the 16-bit PCI configuration register specified by Address, performs a
475	bitwise AND between the read result and the value specified by AndData,
476	performs a bitwise OR between the result of the AND operation and
477	the value specified by OrData, and writes the result to the 16-bit PCI
478	configuration register specified by Address. The value written to the PCI
479	configuration register is returned. This function must guarantee that all PCI
480	read and write operations are serialized.
481
482	If Address > 0x0FFFFFFF, then ASSERT().
483	If Address is not aligned on a 16-bit boundary, then ASSERT().
484
485	@param Address Address that encodes the PCI Bus, Device, Function and
486	Register.
487	@param AndData The value to AND with the PCI configuration register.
488	@param OrData The value to OR with the result of the AND operation.
489
490	@return The value written back to the PCI configuration register.
491
492	**/
493	UINT16
494	EFIAPI
495	PciExpressAndThenOr16 (
496	IN UINTN Address,
497	IN UINT16 AndData,
498	IN UINT16 OrData
499	);
500
501	/**
502	Reads a bit field of a PCI configuration register.
503
504	Reads the bit field in a 16-bit PCI configuration register. The bit field is
505	specified by the StartBit and the EndBit. The value of the bit field is
506	returned.
507
508	If Address > 0x0FFFFFFF, then ASSERT().
509	If Address is not aligned on a 16-bit boundary, then ASSERT().
510	If StartBit is greater than 15, then ASSERT().
511	If EndBit is greater than 15, then ASSERT().
512	If EndBit is less than StartBit, then ASSERT().
513
514	@param Address PCI configuration register to read.
515	@param StartBit The ordinal of the least significant bit in the bit field.
516	Range 0..15.
517	@param EndBit The ordinal of the most significant bit in the bit field.
518	Range 0..15.
519
520	@return The value of the bit field read from the PCI configuration register.
521
522	**/
523	UINT16
524	EFIAPI
525	PciExpressBitFieldRead16 (
526	IN UINTN Address,
527	IN UINTN StartBit,
528	IN UINTN EndBit
529	);
530
531	/**
532	Writes a bit field to a PCI configuration register.
533
534	Writes Value to the bit field of the PCI configuration register. The bit
535	field is specified by the StartBit and the EndBit. All other bits in the
536	destination PCI configuration register are preserved. The new value of the
537	16-bit register is returned.
538
539	If Address > 0x0FFFFFFF, then ASSERT().
540	If Address is not aligned on a 16-bit boundary, then ASSERT().
541	If StartBit is greater than 15, then ASSERT().
542	If EndBit is greater than 15, then ASSERT().
543	If EndBit is less than StartBit, then ASSERT().
544	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
545
546	@param Address PCI configuration register to write.
547	@param StartBit The ordinal of the least significant bit in the bit field.
548	Range 0..15.
549	@param EndBit The ordinal of the most significant bit in the bit field.
550	Range 0..15.
551	@param Value New value of the bit field.
552
553	@return The value written back to the PCI configuration register.
554
555	**/
556	UINT16
557	EFIAPI
558	PciExpressBitFieldWrite16 (
559	IN UINTN Address,
560	IN UINTN StartBit,
561	IN UINTN EndBit,
562	IN UINT16 Value
563	);
564
565	/**
566	Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
567	writes the result back to the bit field in the 16-bit port.
568
569	Reads the 16-bit PCI configuration register specified by Address, performs a
570	bitwise OR between the read result and the value specified by
571	OrData, and writes the result to the 16-bit PCI configuration register
572	specified by Address. The value written to the PCI configuration register is
573	returned. This function must guarantee that all PCI read and write operations
574	are serialized. Extra left bits in OrData are stripped.
575
576	If Address > 0x0FFFFFFF, then ASSERT().
577	If Address is not aligned on a 16-bit boundary, then ASSERT().
578	If StartBit is greater than 15, then ASSERT().
579	If EndBit is greater than 15, then ASSERT().
580	If EndBit is less than StartBit, then ASSERT().
581	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
582
583	@param Address PCI configuration register to write.
584	@param StartBit The ordinal of the least significant bit in the bit field.
585	Range 0..15.
586	@param EndBit The ordinal of the most significant bit in the bit field.
587	Range 0..15.
588	@param OrData The value to OR with the PCI configuration register.
589
590	@return The value written back to the PCI configuration register.
591
592	**/
593	UINT16
594	EFIAPI
595	PciExpressBitFieldOr16 (
596	IN UINTN Address,
597	IN UINTN StartBit,
598	IN UINTN EndBit,
599	IN UINT16 OrData
600	);
601
602	/**
603	Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
604	AND, and writes the result back to the bit field in the 16-bit register.
605
606	Reads the 16-bit PCI configuration register specified by Address, performs a
607	bitwise AND between the read result and the value specified by AndData, and
608	writes the result to the 16-bit PCI configuration register specified by
609	Address. The value written to the PCI configuration register is returned.
610	This function must guarantee that all PCI read and write operations are
611	serialized. Extra left bits in AndData are stripped.
612
613	If Address > 0x0FFFFFFF, then ASSERT().
614	If Address is not aligned on a 16-bit boundary, then ASSERT().
615	If StartBit is greater than 15, then ASSERT().
616	If EndBit is greater than 15, then ASSERT().
617	If EndBit is less than StartBit, then ASSERT().
618	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
619
620	@param Address PCI configuration register to write.
621	@param StartBit The ordinal of the least significant bit in the bit field.
622	Range 0..15.
623	@param EndBit The ordinal of the most significant bit in the bit field.
624	Range 0..15.
625	@param AndData The value to AND with the PCI configuration register.
626
627	@return The value written back to the PCI configuration register.
628
629	**/
630	UINT16
631	EFIAPI
632	PciExpressBitFieldAnd16 (
633	IN UINTN Address,
634	IN UINTN StartBit,
635	IN UINTN EndBit,
636	IN UINT16 AndData
637	);
638
639	/**
640	Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
641	bitwise OR, and writes the result back to the bit field in the
642	16-bit port.
643
644	Reads the 16-bit PCI configuration register specified by Address, performs a
645	bitwise AND followed by a bitwise OR between the read result and
646	the value specified by AndData, and writes the result to the 16-bit PCI
647	configuration register specified by Address. The value written to the PCI
648	configuration register is returned. This function must guarantee that all PCI
649	read and write operations are serialized. Extra left bits in both AndData and
650	OrData are stripped.
651
652	If Address > 0x0FFFFFFF, then ASSERT().
653	If Address is not aligned on a 16-bit boundary, then ASSERT().
654	If StartBit is greater than 15, then ASSERT().
655	If EndBit is greater than 15, then ASSERT().
656	If EndBit is less than StartBit, then ASSERT().
657	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
658	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
659
660	@param Address PCI configuration register to write.
661	@param StartBit The ordinal of the least significant bit in the bit field.
662	Range 0..15.
663	@param EndBit The ordinal of the most significant bit in the bit field.
664	Range 0..15.
665	@param AndData The value to AND with the PCI configuration register.
666	@param OrData The value to OR with the result of the AND operation.
667
668	@return The value written back to the PCI configuration register.
669
670	**/
671	UINT16
672	EFIAPI
673	PciExpressBitFieldAndThenOr16 (
674	IN UINTN Address,
675	IN UINTN StartBit,
676	IN UINTN EndBit,
677	IN UINT16 AndData,
678	IN UINT16 OrData
679	);
680
681	/**
682	Reads a 32-bit PCI configuration register.
683
684	Reads and returns the 32-bit PCI configuration register specified by Address.
685	This function must guarantee that all PCI read and write operations are
686	serialized.
687
688	If Address > 0x0FFFFFFF, then ASSERT().
689	If Address is not aligned on a 32-bit boundary, then ASSERT().
690
691	@param Address Address that encodes the PCI Bus, Device, Function and
692	Register.
693
694	@return The read value from the PCI configuration register.
695
696	**/
697	UINT32
698	EFIAPI
699	PciExpressRead32 (
700	IN UINTN Address
701	);
702
703	/**
704	Writes a 32-bit PCI configuration register.
705
706	Writes the 32-bit PCI configuration register specified by Address with the
707	value specified by Value. Value is returned. This function must guarantee
708	that all PCI read and write operations are serialized.
709
710	If Address > 0x0FFFFFFF, then ASSERT().
711	If Address is not aligned on a 32-bit boundary, then ASSERT().
712
713	@param Address Address that encodes the PCI Bus, Device, Function and
714	Register.
715	@param Value The value to write.
716
717	@return The value written to the PCI configuration register.
718
719	**/
720	UINT32
721	EFIAPI
722	PciExpressWrite32 (
723	IN UINTN Address,
724	IN UINT32 Value
725	);
726
727	/**
728	Performs a bitwise OR of a 32-bit PCI configuration register with
729	a 32-bit value.
730
731	Reads the 32-bit PCI configuration register specified by Address, performs a
732	bitwise OR between the read result and the value specified by
733	OrData, and writes the result to the 32-bit PCI configuration register
734	specified by Address. The value written to the PCI configuration register is
735	returned. This function must guarantee that all PCI read and write operations
736	are serialized.
737
738	If Address > 0x0FFFFFFF, then ASSERT().
739	If Address is not aligned on a 32-bit boundary, then ASSERT().
740
741	@param Address Address that encodes the PCI Bus, Device, Function and
742	Register.
743	@param OrData The value to OR with the PCI configuration register.
744
745	@return The value written back to the PCI configuration register.
746
747	**/
748	UINT32
749	EFIAPI
750	PciExpressOr32 (
751	IN UINTN Address,
752	IN UINT32 OrData
753	);
754
755	/**
756	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
757	value.
758
759	Reads the 32-bit PCI configuration register specified by Address, performs a
760	bitwise AND between the read result and the value specified by AndData, and
761	writes the result to the 32-bit PCI configuration register specified by
762	Address. The value written to the PCI configuration register is returned.
763	This function must guarantee that all PCI read and write operations are
764	serialized.
765
766	If Address > 0x0FFFFFFF, then ASSERT().
767	If Address is not aligned on a 32-bit boundary, then ASSERT().
768
769	@param Address Address that encodes the PCI Bus, Device, Function and
770	Register.
771	@param AndData The value to AND with the PCI configuration register.
772
773	@return The value written back to the PCI configuration register.
774
775	**/
776	UINT32
777	EFIAPI
778	PciExpressAnd32 (
779	IN UINTN Address,
780	IN UINT32 AndData
781	);
782
783	/**
784	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
785	value, followed a bitwise OR with another 32-bit value.
786
787	Reads the 32-bit PCI configuration register specified by Address, performs a
788	bitwise AND between the read result and the value specified by AndData,
789	performs a bitwise OR between the result of the AND operation and
790	the value specified by OrData, and writes the result to the 32-bit PCI
791	configuration register specified by Address. The value written to the PCI
792	configuration register is returned. This function must guarantee that all PCI
793	read and write operations are serialized.
794
795	If Address > 0x0FFFFFFF, then ASSERT().
796	If Address is not aligned on a 32-bit boundary, then ASSERT().
797
798	@param Address Address that encodes the PCI Bus, Device, Function and
799	Register.
800	@param AndData The value to AND with the PCI configuration register.
801	@param OrData The value to OR with the result of the AND operation.
802
803	@return The value written back to the PCI configuration register.
804
805	**/
806	UINT32
807	EFIAPI
808	PciExpressAndThenOr32 (
809	IN UINTN Address,
810	IN UINT32 AndData,
811	IN UINT32 OrData
812	);
813
814	/**
815	Reads a bit field of a PCI configuration register.
816
817	Reads the bit field in a 32-bit PCI configuration register. The bit field is
818	specified by the StartBit and the EndBit. The value of the bit field is
819	returned.
820
821	If Address > 0x0FFFFFFF, then ASSERT().
822	If Address is not aligned on a 32-bit boundary, then ASSERT().
823	If StartBit is greater than 31, then ASSERT().
824	If EndBit is greater than 31, then ASSERT().
825	If EndBit is less than StartBit, then ASSERT().
826
827	@param Address PCI configuration register to read.
828	@param StartBit The ordinal of the least significant bit in the bit field.
829	Range 0..31.
830	@param EndBit The ordinal of the most significant bit in the bit field.
831	Range 0..31.
832
833	@return The value of the bit field read from the PCI configuration register.
834
835	**/
836	UINT32
837	EFIAPI
838	PciExpressBitFieldRead32 (
839	IN UINTN Address,
840	IN UINTN StartBit,
841	IN UINTN EndBit
842	);
843
844	/**
845	Writes a bit field to a PCI configuration register.
846
847	Writes Value to the bit field of the PCI configuration register. The bit
848	field is specified by the StartBit and the EndBit. All other bits in the
849	destination PCI configuration register are preserved. The new value of the
850	32-bit register is returned.
851
852	If Address > 0x0FFFFFFF, then ASSERT().
853	If Address is not aligned on a 32-bit boundary, then ASSERT().
854	If StartBit is greater than 31, then ASSERT().
855	If EndBit is greater than 31, then ASSERT().
856	If EndBit is less than StartBit, then ASSERT().
857	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
858
859	@param Address PCI configuration register to write.
860	@param StartBit The ordinal of the least significant bit in the bit field.
861	Range 0..31.
862	@param EndBit The ordinal of the most significant bit in the bit field.
863	Range 0..31.
864	@param Value New value of the bit field.
865
866	@return The value written back to the PCI configuration register.
867
868	**/
869	UINT32
870	EFIAPI
871	PciExpressBitFieldWrite32 (
872	IN UINTN Address,
873	IN UINTN StartBit,
874	IN UINTN EndBit,
875	IN UINT32 Value
876	);
877
878	/**
879	Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
880	writes the result back to the bit field in the 32-bit port.
881
882	Reads the 32-bit PCI configuration register specified by Address, performs a
883	bitwise OR between the read result and the value specified by
884	OrData, and writes the result to the 32-bit PCI configuration register
885	specified by Address. The value written to the PCI configuration register is
886	returned. This function must guarantee that all PCI read and write operations
887	are serialized. Extra left bits in OrData are stripped.
888
889	If Address > 0x0FFFFFFF, then ASSERT().
890	If Address is not aligned on a 32-bit boundary, then ASSERT().
891	If StartBit is greater than 31, then ASSERT().
892	If EndBit is greater than 31, then ASSERT().
893	If EndBit is less than StartBit, then ASSERT().
894	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
895
896	@param Address PCI configuration register to write.
897	@param StartBit The ordinal of the least significant bit in the bit field.
898	Range 0..31.
899	@param EndBit The ordinal of the most significant bit in the bit field.
900	Range 0..31.
901	@param OrData The value to OR with the PCI configuration register.
902
903	@return The value written back to the PCI configuration register.
904
905	**/
906	UINT32
907	EFIAPI
908	PciExpressBitFieldOr32 (
909	IN UINTN Address,
910	IN UINTN StartBit,
911	IN UINTN EndBit,
912	IN UINT32 OrData
913	);
914
915	/**
916	Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
917	AND, and writes the result back to the bit field in the 32-bit register.
918
919	Reads the 32-bit PCI configuration register specified by Address, performs a
920	bitwise AND between the read result and the value specified by AndData, and
921	writes the result to the 32-bit PCI configuration register specified by
922	Address. The value written to the PCI configuration register is returned.
923	This function must guarantee that all PCI read and write operations are
924	serialized. Extra left bits in AndData are stripped.
925
926	If Address > 0x0FFFFFFF, then ASSERT().
927	If Address is not aligned on a 32-bit boundary, then ASSERT().
928	If StartBit is greater than 31, then ASSERT().
929	If EndBit is greater than 31, then ASSERT().
930	If EndBit is less than StartBit, then ASSERT().
931	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
932
933	@param Address PCI configuration register to write.
934	@param StartBit The ordinal of the least significant bit in the bit field.
935	Range 0..31.
936	@param EndBit The ordinal of the most significant bit in the bit field.
937	Range 0..31.
938	@param AndData The value to AND with the PCI configuration register.
939
940	@return The value written back to the PCI configuration register.
941
942	**/
943	UINT32
944	EFIAPI
945	PciExpressBitFieldAnd32 (
946	IN UINTN Address,
947	IN UINTN StartBit,
948	IN UINTN EndBit,
949	IN UINT32 AndData
950	);
951
952	/**
953	Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
954	bitwise OR, and writes the result back to the bit field in the
955	32-bit port.
956
957	Reads the 32-bit PCI configuration register specified by Address, performs a
958	bitwise AND followed by a bitwise OR between the read result and
959	the value specified by AndData, and writes the result to the 32-bit PCI
960	configuration register specified by Address. The value written to the PCI
961	configuration register is returned. This function must guarantee that all PCI
962	read and write operations are serialized. Extra left bits in both AndData and
963	OrData are stripped.
964
965	If Address > 0x0FFFFFFF, then ASSERT().
966	If Address is not aligned on a 32-bit boundary, then ASSERT().
967	If StartBit is greater than 31, then ASSERT().
968	If EndBit is greater than 31, then ASSERT().
969	If EndBit is less than StartBit, then ASSERT().
970	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
971	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
972
973	@param Address PCI configuration register to write.
974	@param StartBit The ordinal of the least significant bit in the bit field.
975	Range 0..31.
976	@param EndBit The ordinal of the most significant bit in the bit field.
977	Range 0..31.
978	@param AndData The value to AND with the PCI configuration register.
979	@param OrData The value to OR with the result of the AND operation.
980
981	@return The value written back to the PCI configuration register.
982
983	**/
984	UINT32
985	EFIAPI
986	PciExpressBitFieldAndThenOr32 (
987	IN UINTN Address,
988	IN UINTN StartBit,
989	IN UINTN EndBit,
990	IN UINT32 AndData,
991	IN UINT32 OrData
992	);
993
994	/**
995	Reads a range of PCI configuration registers into a caller supplied buffer.
996
997	Reads the range of PCI configuration registers specified by StartAddress and
998	Size into the buffer specified by Buffer. This function only allows the PCI
999	configuration registers from a single PCI function to be read. Size is
1000	returned. When possible 32-bit PCI configuration read cycles are used to read
1001	from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
1002	and 16-bit PCI configuration read cycles may be used at the beginning and the
1003	end of the range.
1004
1005	If StartAddress > 0x0FFFFFFF, then ASSERT().
1006	If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1007	If Size > 0 and Buffer is NULL, then ASSERT().
1008
1009	@param StartAddress Starting address that encodes the PCI Bus, Device,
1010	Function and Register.
1011	@param Size Size in bytes of the transfer.
1012	@param Buffer Pointer to a buffer receiving the data read.
1013
1014	@return Size read data from StartAddress.
1015
1016	**/
1017	UINTN
1018	EFIAPI
1019	PciExpressReadBuffer (
1020	IN UINTN StartAddress,
1021	IN UINTN Size,
1022	OUT VOID *Buffer
1023	);
1024
1025	/**
1026	Copies the data in a caller supplied buffer to a specified range of PCI
1027	configuration space.
1028
1029	Writes the range of PCI configuration registers specified by StartAddress and
1030	Size from the buffer specified by Buffer. This function only allows the PCI
1031	configuration registers from a single PCI function to be written. Size is
1032	returned. When possible 32-bit PCI configuration write cycles are used to
1033	write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1034	8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1035	and the end of the range.
1036
1037	If StartAddress > 0x0FFFFFFF, then ASSERT().
1038	If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1039	If Size > 0 and Buffer is NULL, then ASSERT().
1040
1041	@param StartAddress Starting address that encodes the PCI Bus, Device,
1042	Function and Register.
1043	@param Size Size in bytes of the transfer.
1044	@param Buffer Pointer to a buffer containing the data to write.
1045
1046	@return Size written to StartAddress.
1047
1048	**/
1049	UINTN
1050	EFIAPI
1051	PciExpressWriteBuffer (
1052	IN UINTN StartAddress,
1053	IN UINTN Size,
1054	IN VOID *Buffer
1055	);
1056
1057	#endif

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source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Library/PciExpressLib.h@ 105681

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