PciExpressLib.h@ 48674

最後變更在這個檔案從48674是 48674,由 vboxsync 提交於 11 年前
EFI: Export newly imported tinaocore UEFI sources to OSE.
屬性 svn:eol-style 設為 `native`
檔案大小: 37.5 KB

行
1	/** @file
2	Provides services to access PCI Configuration Space using the MMIO PCI Express window.
3
4	This library is identical to the PCI Library, except the access method for performing PCI
5	configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
6	is defined by PcdPciExpressBaseAddress.
7
8	Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
9	This program and the accompanying materials
10	are licensed and made available under the terms and conditions of the BSD License
11	which accompanies this distribution. The full text of the license may be found at
12	http://opensource.org/licenses/bsd-license.php
13
14	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17	**/
18
19	#ifndef __PCI_EXPRESS_LIB_H__
20	#define __PCI_EXPRESS_LIB_H__
21
22	/**
23	Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24	address that can be passed to the PCI Library functions.
25
26	Computes an address that is compatible with the PCI Library functions. The
27	unused upper bits of Bus, Device, Function and Register are stripped prior to
28	the generation of the address.
29
30	@param Bus PCI Bus number. Range 0..255.
31	@param Device PCI Device number. Range 0..31.
32	@param Function PCI Function number. Range 0..7.
33	@param Register PCI Register number. Range 0..4095.
34
35	@return The encode PCI address.
36
37	**/
38	#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
39	(((Offset) & 0xfff) \| (((Function) & 0x07) << 12) \| (((Device) & 0x1f) << 15) \| (((Bus) & 0xff) << 20))
40
41	/**
42	Registers a PCI device so PCI configuration registers may be accessed after
43	SetVirtualAddressMap().
44
45	Registers the PCI device specified by Address so all the PCI configuration
46	registers associated with that PCI device may be accessed after SetVirtualAddressMap()
47	is called.
48
49	If Address > 0x0FFFFFFF, then ASSERT().
50
51	@param Address Address that encodes the PCI Bus, Device, Function and
52	Register.
53
54	@retval RETURN_SUCCESS The PCI device was registered for runtime access.
55	@retval RETURN_UNSUPPORTED An attempt was made to call this function
56	after ExitBootServices().
57	@retval RETURN_UNSUPPORTED The resources required to access the PCI device
58	at runtime could not be mapped.
59	@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
60	complete the registration.
61
62	**/
63	RETURN_STATUS
64	EFIAPI
65	PciExpressRegisterForRuntimeAccess (
66	IN UINTN Address
67	);
68
69	/**
70	Reads an 8-bit PCI configuration register.
71
72	Reads and returns the 8-bit PCI configuration register specified by Address.
73	This function must guarantee that all PCI read and write operations are
74	serialized.
75
76	If Address > 0x0FFFFFFF, then ASSERT().
77
78	@param Address Address that encodes the PCI Bus, Device, Function and
79	Register.
80
81	@return The read value from the PCI configuration register.
82
83	**/
84	UINT8
85	EFIAPI
86	PciExpressRead8 (
87	IN UINTN Address
88	);
89
90	/**
91	Writes an 8-bit PCI configuration register.
92
93	Writes the 8-bit PCI configuration register specified by Address with the
94	value specified by Value. Value is returned. This function must guarantee
95	that all PCI read and write operations are serialized.
96
97	If Address > 0x0FFFFFFF, then ASSERT().
98
99	@param Address Address that encodes the PCI Bus, Device, Function and
100	Register.
101	@param Value The value to write.
102
103	@return The value written to the PCI configuration register.
104
105	**/
106	UINT8
107	EFIAPI
108	PciExpressWrite8 (
109	IN UINTN Address,
110	IN UINT8 Value
111	);
112
113	/**
114	Performs a bitwise OR of an 8-bit PCI configuration register with
115	an 8-bit value.
116
117	Reads the 8-bit PCI configuration register specified by Address, performs a
118	bitwise OR between the read result and the value specified by
119	OrData, and writes the result to the 8-bit PCI configuration register
120	specified by Address. The value written to the PCI configuration register is
121	returned. This function must guarantee that all PCI read and write operations
122	are serialized.
123
124	If Address > 0x0FFFFFFF, then ASSERT().
125
126	@param Address Address that encodes the PCI Bus, Device, Function and
127	Register.
128	@param OrData The value to OR with the PCI configuration register.
129
130	@return The value written back to the PCI configuration register.
131
132	**/
133	UINT8
134	EFIAPI
135	PciExpressOr8 (
136	IN UINTN Address,
137	IN UINT8 OrData
138	);
139
140	/**
141	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
142	value.
143
144	Reads the 8-bit PCI configuration register specified by Address, performs a
145	bitwise AND between the read result and the value specified by AndData, and
146	writes the result to the 8-bit PCI configuration register specified by
147	Address. The value written to the PCI configuration register is returned.
148	This function must guarantee that all PCI read and write operations are
149	serialized.
150
151	If Address > 0x0FFFFFFF, then ASSERT().
152
153	@param Address Address that encodes the PCI Bus, Device, Function and
154	Register.
155	@param AndData The value to AND with the PCI configuration register.
156
157	@return The value written back to the PCI configuration register.
158
159	**/
160	UINT8
161	EFIAPI
162	PciExpressAnd8 (
163	IN UINTN Address,
164	IN UINT8 AndData
165	);
166
167	/**
168	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
169	value, followed a bitwise OR with another 8-bit value.
170
171	Reads the 8-bit PCI configuration register specified by Address, performs a
172	bitwise AND between the read result and the value specified by AndData,
173	performs a bitwise OR between the result of the AND operation and
174	the value specified by OrData, and writes the result to the 8-bit PCI
175	configuration register specified by Address. The value written to the PCI
176	configuration register is returned. This function must guarantee that all PCI
177	read and write operations are serialized.
178
179	If Address > 0x0FFFFFFF, then ASSERT().
180
181	@param Address Address that encodes the PCI Bus, Device, Function and
182	Register.
183	@param AndData The value to AND with the PCI configuration register.
184	@param OrData The value to OR with the result of the AND operation.
185
186	@return The value written back to the PCI configuration register.
187
188	**/
189	UINT8
190	EFIAPI
191	PciExpressAndThenOr8 (
192	IN UINTN Address,
193	IN UINT8 AndData,
194	IN UINT8 OrData
195	);
196
197	/**
198	Reads a bit field of a PCI configuration register.
199
200	Reads the bit field in an 8-bit PCI configuration register. The bit field is
201	specified by the StartBit and the EndBit. The value of the bit field is
202	returned.
203
204	If Address > 0x0FFFFFFF, then ASSERT().
205	If StartBit is greater than 7, then ASSERT().
206	If EndBit is greater than 7, then ASSERT().
207	If EndBit is less than StartBit, then ASSERT().
208
209	@param Address PCI configuration register to read.
210	@param StartBit The ordinal of the least significant bit in the bit field.
211	Range 0..7.
212	@param EndBit The ordinal of the most significant bit in the bit field.
213	Range 0..7.
214
215	@return The value of the bit field read from the PCI configuration register.
216
217	**/
218	UINT8
219	EFIAPI
220	PciExpressBitFieldRead8 (
221	IN UINTN Address,
222	IN UINTN StartBit,
223	IN UINTN EndBit
224	);
225
226	/**
227	Writes a bit field to a PCI configuration register.
228
229	Writes Value to the bit field of the PCI configuration register. The bit
230	field is specified by the StartBit and the EndBit. All other bits in the
231	destination PCI configuration register are preserved. The new value of the
232	8-bit register is returned.
233
234	If Address > 0x0FFFFFFF, then ASSERT().
235	If StartBit is greater than 7, then ASSERT().
236	If EndBit is greater than 7, then ASSERT().
237	If EndBit is less than StartBit, then ASSERT().
238
239	@param Address PCI configuration register to write.
240	@param StartBit The ordinal of the least significant bit in the bit field.
241	Range 0..7.
242	@param EndBit The ordinal of the most significant bit in the bit field.
243	Range 0..7.
244	@param Value New value of the bit field.
245
246	@return The value written back to the PCI configuration register.
247
248	**/
249	UINT8
250	EFIAPI
251	PciExpressBitFieldWrite8 (
252	IN UINTN Address,
253	IN UINTN StartBit,
254	IN UINTN EndBit,
255	IN UINT8 Value
256	);
257
258	/**
259	Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
260	writes the result back to the bit field in the 8-bit port.
261
262	Reads the 8-bit PCI configuration register specified by Address, performs a
263	bitwise OR between the read result and the value specified by
264	OrData, and writes the result to the 8-bit PCI configuration register
265	specified by Address. The value written to the PCI configuration register is
266	returned. This function must guarantee that all PCI read and write operations
267	are serialized. Extra left bits in OrData are stripped.
268
269	If Address > 0x0FFFFFFF, then ASSERT().
270	If StartBit is greater than 7, then ASSERT().
271	If EndBit is greater than 7, then ASSERT().
272	If EndBit is less than StartBit, then ASSERT().
273
274	@param Address PCI configuration register to write.
275	@param StartBit The ordinal of the least significant bit in the bit field.
276	Range 0..7.
277	@param EndBit The ordinal of the most significant bit in the bit field.
278	Range 0..7.
279	@param OrData The value to OR with the PCI configuration register.
280
281	@return The value written back to the PCI configuration register.
282
283	**/
284	UINT8
285	EFIAPI
286	PciExpressBitFieldOr8 (
287	IN UINTN Address,
288	IN UINTN StartBit,
289	IN UINTN EndBit,
290	IN UINT8 OrData
291	);
292
293	/**
294	Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
295	AND, and writes the result back to the bit field in the 8-bit register.
296
297	Reads the 8-bit PCI configuration register specified by Address, performs a
298	bitwise AND between the read result and the value specified by AndData, and
299	writes the result to the 8-bit PCI configuration register specified by
300	Address. The value written to the PCI configuration register is returned.
301	This function must guarantee that all PCI read and write operations are
302	serialized. Extra left bits in AndData are stripped.
303
304	If Address > 0x0FFFFFFF, then ASSERT().
305	If StartBit is greater than 7, then ASSERT().
306	If EndBit is greater than 7, then ASSERT().
307	If EndBit is less than StartBit, then ASSERT().
308
309	@param Address PCI configuration register to write.
310	@param StartBit The ordinal of the least significant bit in the bit field.
311	Range 0..7.
312	@param EndBit The ordinal of the most significant bit in the bit field.
313	Range 0..7.
314	@param AndData The value to AND with the PCI configuration register.
315
316	@return The value written back to the PCI configuration register.
317
318	**/
319	UINT8
320	EFIAPI
321	PciExpressBitFieldAnd8 (
322	IN UINTN Address,
323	IN UINTN StartBit,
324	IN UINTN EndBit,
325	IN UINT8 AndData
326	);
327
328	/**
329	Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
330	bitwise OR, and writes the result back to the bit field in the
331	8-bit port.
332
333	Reads the 8-bit PCI configuration register specified by Address, performs a
334	bitwise AND followed by a bitwise OR between the read result and
335	the value specified by AndData, and writes the result to the 8-bit PCI
336	configuration register specified by Address. The value written to the PCI
337	configuration register is returned. This function must guarantee that all PCI
338	read and write operations are serialized. Extra left bits in both AndData and
339	OrData are stripped.
340
341	If Address > 0x0FFFFFFF, then ASSERT().
342	If StartBit is greater than 7, then ASSERT().
343	If EndBit is greater than 7, then ASSERT().
344	If EndBit is less than StartBit, then ASSERT().
345
346	@param Address PCI configuration register to write.
347	@param StartBit The ordinal of the least significant bit in the bit field.
348	Range 0..7.
349	@param EndBit The ordinal of the most significant bit in the bit field.
350	Range 0..7.
351	@param AndData The value to AND with the PCI configuration register.
352	@param OrData The value to OR with the result of the AND operation.
353
354	@return The value written back to the PCI configuration register.
355
356	**/
357	UINT8
358	EFIAPI
359	PciExpressBitFieldAndThenOr8 (
360	IN UINTN Address,
361	IN UINTN StartBit,
362	IN UINTN EndBit,
363	IN UINT8 AndData,
364	IN UINT8 OrData
365	);
366
367	/**
368	Reads a 16-bit PCI configuration register.
369
370	Reads and returns the 16-bit PCI configuration register specified by Address.
371	This function must guarantee that all PCI read and write operations are
372	serialized.
373
374	If Address > 0x0FFFFFFF, then ASSERT().
375	If Address is not aligned on a 16-bit boundary, then ASSERT().
376
377	@param Address Address that encodes the PCI Bus, Device, Function and
378	Register.
379
380	@return The read value from the PCI configuration register.
381
382	**/
383	UINT16
384	EFIAPI
385	PciExpressRead16 (
386	IN UINTN Address
387	);
388
389	/**
390	Writes a 16-bit PCI configuration register.
391
392	Writes the 16-bit PCI configuration register specified by Address with the
393	value specified by Value. Value is returned. This function must guarantee
394	that all PCI read and write operations are serialized.
395
396	If Address > 0x0FFFFFFF, then ASSERT().
397	If Address is not aligned on a 16-bit boundary, then ASSERT().
398
399	@param Address Address that encodes the PCI Bus, Device, Function and
400	Register.
401	@param Value The value to write.
402
403	@return The value written to the PCI configuration register.
404
405	**/
406	UINT16
407	EFIAPI
408	PciExpressWrite16 (
409	IN UINTN Address,
410	IN UINT16 Value
411	);
412
413	/**
414	Performs a bitwise OR of a 16-bit PCI configuration register with
415	a 16-bit value.
416
417	Reads the 16-bit PCI configuration register specified by Address, performs a
418	bitwise OR between the read result and the value specified by
419	OrData, and writes the result to the 16-bit PCI configuration register
420	specified by Address. The value written to the PCI configuration register is
421	returned. This function must guarantee that all PCI read and write operations
422	are serialized.
423
424	If Address > 0x0FFFFFFF, then ASSERT().
425	If Address is not aligned on a 16-bit boundary, then ASSERT().
426
427	@param Address Address that encodes the PCI Bus, Device, Function and
428	Register.
429	@param OrData The value to OR with the PCI configuration register.
430
431	@return The value written back to the PCI configuration register.
432
433	**/
434	UINT16
435	EFIAPI
436	PciExpressOr16 (
437	IN UINTN Address,
438	IN UINT16 OrData
439	);
440
441	/**
442	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
443	value.
444
445	Reads the 16-bit PCI configuration register specified by Address, performs a
446	bitwise AND between the read result and the value specified by AndData, and
447	writes the result to the 16-bit PCI configuration register specified by
448	Address. The value written to the PCI configuration register is returned.
449	This function must guarantee that all PCI read and write operations are
450	serialized.
451
452	If Address > 0x0FFFFFFF, then ASSERT().
453	If Address is not aligned on a 16-bit boundary, then ASSERT().
454
455	@param Address Address that encodes the PCI Bus, Device, Function and
456	Register.
457	@param AndData The value to AND with the PCI configuration register.
458
459	@return The value written back to the PCI configuration register.
460
461	**/
462	UINT16
463	EFIAPI
464	PciExpressAnd16 (
465	IN UINTN Address,
466	IN UINT16 AndData
467	);
468
469	/**
470	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
471	value, followed a bitwise OR with another 16-bit value.
472
473	Reads the 16-bit PCI configuration register specified by Address, performs a
474	bitwise AND between the read result and the value specified by AndData,
475	performs a bitwise OR between the result of the AND operation and
476	the value specified by OrData, and writes the result to the 16-bit PCI
477	configuration register specified by Address. The value written to the PCI
478	configuration register is returned. This function must guarantee that all PCI
479	read and write operations are serialized.
480
481	If Address > 0x0FFFFFFF, then ASSERT().
482	If Address is not aligned on a 16-bit boundary, then ASSERT().
483
484	@param Address Address that encodes the PCI Bus, Device, Function and
485	Register.
486	@param AndData The value to AND with the PCI configuration register.
487	@param OrData The value to OR with the result of the AND operation.
488
489	@return The value written back to the PCI configuration register.
490
491	**/
492	UINT16
493	EFIAPI
494	PciExpressAndThenOr16 (
495	IN UINTN Address,
496	IN UINT16 AndData,
497	IN UINT16 OrData
498	);
499
500	/**
501	Reads a bit field of a PCI configuration register.
502
503	Reads the bit field in a 16-bit PCI configuration register. The bit field is
504	specified by the StartBit and the EndBit. The value of the bit field is
505	returned.
506
507	If Address > 0x0FFFFFFF, then ASSERT().
508	If Address is not aligned on a 16-bit boundary, then ASSERT().
509	If StartBit is greater than 15, then ASSERT().
510	If EndBit is greater than 15, then ASSERT().
511	If EndBit is less than StartBit, then ASSERT().
512
513	@param Address PCI configuration register to read.
514	@param StartBit The ordinal of the least significant bit in the bit field.
515	Range 0..15.
516	@param EndBit The ordinal of the most significant bit in the bit field.
517	Range 0..15.
518
519	@return The value of the bit field read from the PCI configuration register.
520
521	**/
522	UINT16
523	EFIAPI
524	PciExpressBitFieldRead16 (
525	IN UINTN Address,
526	IN UINTN StartBit,
527	IN UINTN EndBit
528	);
529
530	/**
531	Writes a bit field to a PCI configuration register.
532
533	Writes Value to the bit field of the PCI configuration register. The bit
534	field is specified by the StartBit and the EndBit. All other bits in the
535	destination PCI configuration register are preserved. The new value of the
536	16-bit register is returned.
537
538	If Address > 0x0FFFFFFF, then ASSERT().
539	If Address is not aligned on a 16-bit boundary, then ASSERT().
540	If StartBit is greater than 15, then ASSERT().
541	If EndBit is greater than 15, then ASSERT().
542	If EndBit is less than StartBit, then ASSERT().
543
544	@param Address PCI configuration register to write.
545	@param StartBit The ordinal of the least significant bit in the bit field.
546	Range 0..15.
547	@param EndBit The ordinal of the most significant bit in the bit field.
548	Range 0..15.
549	@param Value New value of the bit field.
550
551	@return The value written back to the PCI configuration register.
552
553	**/
554	UINT16
555	EFIAPI
556	PciExpressBitFieldWrite16 (
557	IN UINTN Address,
558	IN UINTN StartBit,
559	IN UINTN EndBit,
560	IN UINT16 Value
561	);
562
563	/**
564	Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
565	writes the result back to the bit field in the 16-bit port.
566
567	Reads the 16-bit PCI configuration register specified by Address, performs a
568	bitwise OR between the read result and the value specified by
569	OrData, and writes the result to the 16-bit PCI configuration register
570	specified by Address. The value written to the PCI configuration register is
571	returned. This function must guarantee that all PCI read and write operations
572	are serialized. Extra left bits in OrData are stripped.
573
574	If Address > 0x0FFFFFFF, then ASSERT().
575	If Address is not aligned on a 16-bit boundary, then ASSERT().
576	If StartBit is greater than 15, then ASSERT().
577	If EndBit is greater than 15, then ASSERT().
578	If EndBit is less than StartBit, then ASSERT().
579
580	@param Address PCI configuration register to write.
581	@param StartBit The ordinal of the least significant bit in the bit field.
582	Range 0..15.
583	@param EndBit The ordinal of the most significant bit in the bit field.
584	Range 0..15.
585	@param OrData The value to OR with the PCI configuration register.
586
587	@return The value written back to the PCI configuration register.
588
589	**/
590	UINT16
591	EFIAPI
592	PciExpressBitFieldOr16 (
593	IN UINTN Address,
594	IN UINTN StartBit,
595	IN UINTN EndBit,
596	IN UINT16 OrData
597	);
598
599	/**
600	Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
601	AND, and writes the result back to the bit field in the 16-bit register.
602
603	Reads the 16-bit PCI configuration register specified by Address, performs a
604	bitwise AND between the read result and the value specified by AndData, and
605	writes the result to the 16-bit PCI configuration register specified by
606	Address. The value written to the PCI configuration register is returned.
607	This function must guarantee that all PCI read and write operations are
608	serialized. Extra left bits in AndData are stripped.
609
610	If Address > 0x0FFFFFFF, then ASSERT().
611	If Address is not aligned on a 16-bit boundary, then ASSERT().
612	If StartBit is greater than 15, then ASSERT().
613	If EndBit is greater than 15, then ASSERT().
614	If EndBit is less than StartBit, then ASSERT().
615
616	@param Address PCI configuration register to write.
617	@param StartBit The ordinal of the least significant bit in the bit field.
618	Range 0..15.
619	@param EndBit The ordinal of the most significant bit in the bit field.
620	Range 0..15.
621	@param AndData The value to AND with the PCI configuration register.
622
623	@return The value written back to the PCI configuration register.
624
625	**/
626	UINT16
627	EFIAPI
628	PciExpressBitFieldAnd16 (
629	IN UINTN Address,
630	IN UINTN StartBit,
631	IN UINTN EndBit,
632	IN UINT16 AndData
633	);
634
635	/**
636	Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
637	bitwise OR, and writes the result back to the bit field in the
638	16-bit port.
639
640	Reads the 16-bit PCI configuration register specified by Address, performs a
641	bitwise AND followed by a bitwise OR between the read result and
642	the value specified by AndData, and writes the result to the 16-bit PCI
643	configuration register specified by Address. The value written to the PCI
644	configuration register is returned. This function must guarantee that all PCI
645	read and write operations are serialized. Extra left bits in both AndData and
646	OrData are stripped.
647
648	If Address > 0x0FFFFFFF, then ASSERT().
649	If Address is not aligned on a 16-bit boundary, then ASSERT().
650	If StartBit is greater than 15, then ASSERT().
651	If EndBit is greater than 15, then ASSERT().
652	If EndBit is less than StartBit, then ASSERT().
653
654	@param Address PCI configuration register to write.
655	@param StartBit The ordinal of the least significant bit in the bit field.
656	Range 0..15.
657	@param EndBit The ordinal of the most significant bit in the bit field.
658	Range 0..15.
659	@param AndData The value to AND with the PCI configuration register.
660	@param OrData The value to OR with the result of the AND operation.
661
662	@return The value written back to the PCI configuration register.
663
664	**/
665	UINT16
666	EFIAPI
667	PciExpressBitFieldAndThenOr16 (
668	IN UINTN Address,
669	IN UINTN StartBit,
670	IN UINTN EndBit,
671	IN UINT16 AndData,
672	IN UINT16 OrData
673	);
674
675	/**
676	Reads a 32-bit PCI configuration register.
677
678	Reads and returns the 32-bit PCI configuration register specified by Address.
679	This function must guarantee that all PCI read and write operations are
680	serialized.
681
682	If Address > 0x0FFFFFFF, then ASSERT().
683	If Address is not aligned on a 32-bit boundary, then ASSERT().
684
685	@param Address Address that encodes the PCI Bus, Device, Function and
686	Register.
687
688	@return The read value from the PCI configuration register.
689
690	**/
691	UINT32
692	EFIAPI
693	PciExpressRead32 (
694	IN UINTN Address
695	);
696
697	/**
698	Writes a 32-bit PCI configuration register.
699
700	Writes the 32-bit PCI configuration register specified by Address with the
701	value specified by Value. Value is returned. This function must guarantee
702	that all PCI read and write operations are serialized.
703
704	If Address > 0x0FFFFFFF, then ASSERT().
705	If Address is not aligned on a 32-bit boundary, then ASSERT().
706
707	@param Address Address that encodes the PCI Bus, Device, Function and
708	Register.
709	@param Value The value to write.
710
711	@return The value written to the PCI configuration register.
712
713	**/
714	UINT32
715	EFIAPI
716	PciExpressWrite32 (
717	IN UINTN Address,
718	IN UINT32 Value
719	);
720
721	/**
722	Performs a bitwise OR of a 32-bit PCI configuration register with
723	a 32-bit value.
724
725	Reads the 32-bit PCI configuration register specified by Address, performs a
726	bitwise OR between the read result and the value specified by
727	OrData, and writes the result to the 32-bit PCI configuration register
728	specified by Address. The value written to the PCI configuration register is
729	returned. This function must guarantee that all PCI read and write operations
730	are serialized.
731
732	If Address > 0x0FFFFFFF, then ASSERT().
733	If Address is not aligned on a 32-bit boundary, then ASSERT().
734
735	@param Address Address that encodes the PCI Bus, Device, Function and
736	Register.
737	@param OrData The value to OR with the PCI configuration register.
738
739	@return The value written back to the PCI configuration register.
740
741	**/
742	UINT32
743	EFIAPI
744	PciExpressOr32 (
745	IN UINTN Address,
746	IN UINT32 OrData
747	);
748
749	/**
750	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
751	value.
752
753	Reads the 32-bit PCI configuration register specified by Address, performs a
754	bitwise AND between the read result and the value specified by AndData, and
755	writes the result to the 32-bit PCI configuration register specified by
756	Address. The value written to the PCI configuration register is returned.
757	This function must guarantee that all PCI read and write operations are
758	serialized.
759
760	If Address > 0x0FFFFFFF, then ASSERT().
761	If Address is not aligned on a 32-bit boundary, then ASSERT().
762
763	@param Address Address that encodes the PCI Bus, Device, Function and
764	Register.
765	@param AndData The value to AND with the PCI configuration register.
766
767	@return The value written back to the PCI configuration register.
768
769	**/
770	UINT32
771	EFIAPI
772	PciExpressAnd32 (
773	IN UINTN Address,
774	IN UINT32 AndData
775	);
776
777	/**
778	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
779	value, followed a bitwise OR with another 32-bit value.
780
781	Reads the 32-bit PCI configuration register specified by Address, performs a
782	bitwise AND between the read result and the value specified by AndData,
783	performs a bitwise OR between the result of the AND operation and
784	the value specified by OrData, and writes the result to the 32-bit PCI
785	configuration register specified by Address. The value written to the PCI
786	configuration register is returned. This function must guarantee that all PCI
787	read and write operations are serialized.
788
789	If Address > 0x0FFFFFFF, then ASSERT().
790	If Address is not aligned on a 32-bit boundary, then ASSERT().
791
792	@param Address Address that encodes the PCI Bus, Device, Function and
793	Register.
794	@param AndData The value to AND with the PCI configuration register.
795	@param OrData The value to OR with the result of the AND operation.
796
797	@return The value written back to the PCI configuration register.
798
799	**/
800	UINT32
801	EFIAPI
802	PciExpressAndThenOr32 (
803	IN UINTN Address,
804	IN UINT32 AndData,
805	IN UINT32 OrData
806	);
807
808	/**
809	Reads a bit field of a PCI configuration register.
810
811	Reads the bit field in a 32-bit PCI configuration register. The bit field is
812	specified by the StartBit and the EndBit. The value of the bit field is
813	returned.
814
815	If Address > 0x0FFFFFFF, then ASSERT().
816	If Address is not aligned on a 32-bit boundary, then ASSERT().
817	If StartBit is greater than 31, then ASSERT().
818	If EndBit is greater than 31, then ASSERT().
819	If EndBit is less than StartBit, then ASSERT().
820
821	@param Address PCI configuration register to read.
822	@param StartBit The ordinal of the least significant bit in the bit field.
823	Range 0..31.
824	@param EndBit The ordinal of the most significant bit in the bit field.
825	Range 0..31.
826
827	@return The value of the bit field read from the PCI configuration register.
828
829	**/
830	UINT32
831	EFIAPI
832	PciExpressBitFieldRead32 (
833	IN UINTN Address,
834	IN UINTN StartBit,
835	IN UINTN EndBit
836	);
837
838	/**
839	Writes a bit field to a PCI configuration register.
840
841	Writes Value to the bit field of the PCI configuration register. The bit
842	field is specified by the StartBit and the EndBit. All other bits in the
843	destination PCI configuration register are preserved. The new value of the
844	32-bit register is returned.
845
846	If Address > 0x0FFFFFFF, then ASSERT().
847	If Address is not aligned on a 32-bit boundary, then ASSERT().
848	If StartBit is greater than 31, then ASSERT().
849	If EndBit is greater than 31, then ASSERT().
850	If EndBit is less than StartBit, then ASSERT().
851
852	@param Address PCI configuration register to write.
853	@param StartBit The ordinal of the least significant bit in the bit field.
854	Range 0..31.
855	@param EndBit The ordinal of the most significant bit in the bit field.
856	Range 0..31.
857	@param Value New value of the bit field.
858
859	@return The value written back to the PCI configuration register.
860
861	**/
862	UINT32
863	EFIAPI
864	PciExpressBitFieldWrite32 (
865	IN UINTN Address,
866	IN UINTN StartBit,
867	IN UINTN EndBit,
868	IN UINT32 Value
869	);
870
871	/**
872	Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
873	writes the result back to the bit field in the 32-bit port.
874
875	Reads the 32-bit PCI configuration register specified by Address, performs a
876	bitwise OR between the read result and the value specified by
877	OrData, and writes the result to the 32-bit PCI configuration register
878	specified by Address. The value written to the PCI configuration register is
879	returned. This function must guarantee that all PCI read and write operations
880	are serialized. Extra left bits in OrData are stripped.
881
882	If Address > 0x0FFFFFFF, then ASSERT().
883	If Address is not aligned on a 32-bit boundary, then ASSERT().
884	If StartBit is greater than 31, then ASSERT().
885	If EndBit is greater than 31, then ASSERT().
886	If EndBit is less than StartBit, then ASSERT().
887
888	@param Address PCI configuration register to write.
889	@param StartBit The ordinal of the least significant bit in the bit field.
890	Range 0..31.
891	@param EndBit The ordinal of the most significant bit in the bit field.
892	Range 0..31.
893	@param OrData The value to OR with the PCI configuration register.
894
895	@return The value written back to the PCI configuration register.
896
897	**/
898	UINT32
899	EFIAPI
900	PciExpressBitFieldOr32 (
901	IN UINTN Address,
902	IN UINTN StartBit,
903	IN UINTN EndBit,
904	IN UINT32 OrData
905	);
906
907	/**
908	Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
909	AND, and writes the result back to the bit field in the 32-bit register.
910
911	Reads the 32-bit PCI configuration register specified by Address, performs a
912	bitwise AND between the read result and the value specified by AndData, and
913	writes the result to the 32-bit PCI configuration register specified by
914	Address. The value written to the PCI configuration register is returned.
915	This function must guarantee that all PCI read and write operations are
916	serialized. Extra left bits in AndData are stripped.
917
918	If Address > 0x0FFFFFFF, then ASSERT().
919	If Address is not aligned on a 32-bit boundary, then ASSERT().
920	If StartBit is greater than 31, then ASSERT().
921	If EndBit is greater than 31, then ASSERT().
922	If EndBit is less than StartBit, then ASSERT().
923
924	@param Address PCI configuration register to write.
925	@param StartBit The ordinal of the least significant bit in the bit field.
926	Range 0..31.
927	@param EndBit The ordinal of the most significant bit in the bit field.
928	Range 0..31.
929	@param AndData The value to AND with the PCI configuration register.
930
931	@return The value written back to the PCI configuration register.
932
933	**/
934	UINT32
935	EFIAPI
936	PciExpressBitFieldAnd32 (
937	IN UINTN Address,
938	IN UINTN StartBit,
939	IN UINTN EndBit,
940	IN UINT32 AndData
941	);
942
943	/**
944	Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
945	bitwise OR, and writes the result back to the bit field in the
946	32-bit port.
947
948	Reads the 32-bit PCI configuration register specified by Address, performs a
949	bitwise AND followed by a bitwise OR between the read result and
950	the value specified by AndData, and writes the result to the 32-bit PCI
951	configuration register specified by Address. The value written to the PCI
952	configuration register is returned. This function must guarantee that all PCI
953	read and write operations are serialized. Extra left bits in both AndData and
954	OrData are stripped.
955
956	If Address > 0x0FFFFFFF, then ASSERT().
957	If Address is not aligned on a 32-bit boundary, then ASSERT().
958	If StartBit is greater than 31, then ASSERT().
959	If EndBit is greater than 31, then ASSERT().
960	If EndBit is less than StartBit, then ASSERT().
961
962	@param Address PCI configuration register to write.
963	@param StartBit The ordinal of the least significant bit in the bit field.
964	Range 0..31.
965	@param EndBit The ordinal of the most significant bit in the bit field.
966	Range 0..31.
967	@param AndData The value to AND with the PCI configuration register.
968	@param OrData The value to OR with the result of the AND operation.
969
970	@return The value written back to the PCI configuration register.
971
972	**/
973	UINT32
974	EFIAPI
975	PciExpressBitFieldAndThenOr32 (
976	IN UINTN Address,
977	IN UINTN StartBit,
978	IN UINTN EndBit,
979	IN UINT32 AndData,
980	IN UINT32 OrData
981	);
982
983	/**
984	Reads a range of PCI configuration registers into a caller supplied buffer.
985
986	Reads the range of PCI configuration registers specified by StartAddress and
987	Size into the buffer specified by Buffer. This function only allows the PCI
988	configuration registers from a single PCI function to be read. Size is
989	returned. When possible 32-bit PCI configuration read cycles are used to read
990	from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
991	and 16-bit PCI configuration read cycles may be used at the beginning and the
992	end of the range.
993
994	If StartAddress > 0x0FFFFFFF, then ASSERT().
995	If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
996	If Size > 0 and Buffer is NULL, then ASSERT().
997
998	@param StartAddress Starting address that encodes the PCI Bus, Device,
999	Function and Register.
1000	@param Size Size in bytes of the transfer.
1001	@param Buffer Pointer to a buffer receiving the data read.
1002
1003	@return Size read data from StartAddress.
1004
1005	**/
1006	UINTN
1007	EFIAPI
1008	PciExpressReadBuffer (
1009	IN UINTN StartAddress,
1010	IN UINTN Size,
1011	OUT VOID *Buffer
1012	);
1013
1014	/**
1015	Copies the data in a caller supplied buffer to a specified range of PCI
1016	configuration space.
1017
1018	Writes the range of PCI configuration registers specified by StartAddress and
1019	Size from the buffer specified by Buffer. This function only allows the PCI
1020	configuration registers from a single PCI function to be written. Size is
1021	returned. When possible 32-bit PCI configuration write cycles are used to
1022	write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1023	8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1024	and the end of the range.
1025
1026	If StartAddress > 0x0FFFFFFF, then ASSERT().
1027	If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1028	If Size > 0 and Buffer is NULL, then ASSERT().
1029
1030	@param StartAddress Starting address that encodes the PCI Bus, Device,
1031	Function and Register.
1032	@param Size Size in bytes of the transfer.
1033	@param Buffer Pointer to a buffer containing the data to write.
1034
1035	@return Size written to StartAddress.
1036
1037	**/
1038	UINTN
1039	EFIAPI
1040	PciExpressWriteBuffer (
1041	IN UINTN StartAddress,
1042	IN UINTN Size,
1043	IN VOID *Buffer
1044	);
1045
1046	#endif

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Library/PciExpressLib.h@ 48674

以其他格式下載: