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1/** @file
2 Provides services to access PCI Configuration Space.
3
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
6 or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
8 accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
9 PCI Express Library may be used in conjunction with the PCI Library. The functionality of
10 these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use
11 explicit access methods.
12
13Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
14SPDX-License-Identifier: BSD-2-Clause-Patent
15
16**/
17
18#ifndef __PCI_LIB_H__
19#define __PCI_LIB_H__
20
21/**
22 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
23 address that can be passed to the PCI Library functions.
24
25 @param Bus PCI Bus number. Range 0..255.
26 @param Device PCI Device number. Range 0..31.
27 @param Function PCI Function number. Range 0..7.
28 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
29 for PCI Express.
30
31 @return The encoded PCI address.
32
33**/
34#define PCI_LIB_ADDRESS(Bus, Device, Function, Register) \
35 (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
36
37/**
38 Registers a PCI device so PCI configuration registers may be accessed after
39 SetVirtualAddressMap().
40
41 Registers the PCI device specified by Address so all the PCI configuration registers
42 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
43
44 If Address > 0x0FFFFFFF, then ASSERT().
45
46 @param Address Address that encodes the PCI Bus, Device, Function and
47 Register.
48
49 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
50 @retval RETURN_UNSUPPORTED An attempt was made to call this function
51 after ExitBootServices().
52 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
53 at runtime could not be mapped.
54 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
55 complete the registration.
56
57**/
58RETURN_STATUS
59EFIAPI
60PciRegisterForRuntimeAccess (
61 IN UINTN Address
62 );
63
64/**
65 Reads an 8-bit PCI configuration register.
66
67 Reads and returns the 8-bit PCI configuration register specified by Address.
68 This function must guarantee that all PCI read and write operations are
69 serialized.
70
71 If Address > 0x0FFFFFFF, then ASSERT().
72
73 @param Address Address that encodes the PCI Bus, Device, Function and
74 Register.
75
76 @return The read value from the PCI configuration register.
77
78**/
79UINT8
80EFIAPI
81PciRead8 (
82 IN UINTN Address
83 );
84
85/**
86 Writes an 8-bit PCI configuration register.
87
88 Writes the 8-bit PCI configuration register specified by Address with the
89 value specified by Value. Value is returned. This function must guarantee
90 that all PCI read and write operations are serialized.
91
92 If Address > 0x0FFFFFFF, then ASSERT().
93
94 @param Address Address that encodes the PCI Bus, Device, Function and
95 Register.
96 @param Value The value to write.
97
98 @return The value written to the PCI configuration register.
99
100**/
101UINT8
102EFIAPI
103PciWrite8 (
104 IN UINTN Address,
105 IN UINT8 Value
106 );
107
108/**
109 Performs a bitwise OR of an 8-bit PCI configuration register with
110 an 8-bit value.
111
112 Reads the 8-bit PCI configuration register specified by Address, performs a
113 bitwise OR between the read result and the value specified by
114 OrData, and writes the result to the 8-bit PCI configuration register
115 specified by Address. The value written to the PCI configuration register is
116 returned. This function must guarantee that all PCI read and write operations
117 are serialized.
118
119 If Address > 0x0FFFFFFF, then ASSERT().
120
121 @param Address Address that encodes the PCI Bus, Device, Function and
122 Register.
123 @param OrData The value to OR with the PCI configuration register.
124
125 @return The value written back to the PCI configuration register.
126
127**/
128UINT8
129EFIAPI
130PciOr8 (
131 IN UINTN Address,
132 IN UINT8 OrData
133 );
134
135/**
136 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
137 value.
138
139 Reads the 8-bit PCI configuration register specified by Address, performs a
140 bitwise AND between the read result and the value specified by AndData, and
141 writes the result to the 8-bit PCI configuration register specified by
142 Address. The value written to the PCI configuration register is returned.
143 This function must guarantee that all PCI read and write operations are
144 serialized.
145
146 If Address > 0x0FFFFFFF, then ASSERT().
147
148 @param Address Address that encodes the PCI Bus, Device, Function and
149 Register.
150 @param AndData The value to AND with the PCI configuration register.
151
152 @return The value written back to the PCI configuration register.
153
154**/
155UINT8
156EFIAPI
157PciAnd8 (
158 IN UINTN Address,
159 IN UINT8 AndData
160 );
161
162/**
163 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
164 value, followed by a bitwise OR with another 8-bit value.
165
166 Reads the 8-bit PCI configuration register specified by Address, performs a
167 bitwise AND between the read result and the value specified by AndData,
168 performs a bitwise OR between the result of the AND operation and
169 the value specified by OrData, and writes the result to the 8-bit PCI
170 configuration register specified by Address. The value written to the PCI
171 configuration register is returned. This function must guarantee that all PCI
172 read and write operations are serialized.
173
174 If Address > 0x0FFFFFFF, then ASSERT().
175
176 @param Address Address that encodes the PCI Bus, Device, Function and
177 Register.
178 @param AndData The value to AND with the PCI configuration register.
179 @param OrData The value to OR with the result of the AND operation.
180
181 @return The value written back to the PCI configuration register.
182
183**/
184UINT8
185EFIAPI
186PciAndThenOr8 (
187 IN UINTN Address,
188 IN UINT8 AndData,
189 IN UINT8 OrData
190 );
191
192/**
193 Reads a bit field of a PCI configuration register.
194
195 Reads the bit field in an 8-bit PCI configuration register. The bit field is
196 specified by the StartBit and the EndBit. The value of the bit field is
197 returned.
198
199 If Address > 0x0FFFFFFF, then ASSERT().
200 If StartBit is greater than 7, then ASSERT().
201 If EndBit is greater than 7, then ASSERT().
202 If EndBit is less than StartBit, then ASSERT().
203
204 @param Address PCI configuration register to read.
205 @param StartBit The ordinal of the least significant bit in the bit field.
206 Range 0..7.
207 @param EndBit The ordinal of the most significant bit in the bit field.
208 Range 0..7.
209
210 @return The value of the bit field read from the PCI configuration register.
211
212**/
213UINT8
214EFIAPI
215PciBitFieldRead8 (
216 IN UINTN Address,
217 IN UINTN StartBit,
218 IN UINTN EndBit
219 );
220
221/**
222 Writes a bit field to a PCI configuration register.
223
224 Writes Value to the bit field of the PCI configuration register. The bit
225 field is specified by the StartBit and the EndBit. All other bits in the
226 destination PCI configuration register are preserved. The new value of the
227 8-bit register is returned.
228
229 If Address > 0x0FFFFFFF, then ASSERT().
230 If StartBit is greater than 7, then ASSERT().
231 If EndBit is greater than 7, then ASSERT().
232 If EndBit is less than StartBit, then ASSERT().
233 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
234
235 @param Address PCI configuration register to write.
236 @param StartBit The ordinal of the least significant bit in the bit field.
237 Range 0..7.
238 @param EndBit The ordinal of the most significant bit in the bit field.
239 Range 0..7.
240 @param Value New value of the bit field.
241
242 @return The value written back to the PCI configuration register.
243
244**/
245UINT8
246EFIAPI
247PciBitFieldWrite8 (
248 IN UINTN Address,
249 IN UINTN StartBit,
250 IN UINTN EndBit,
251 IN UINT8 Value
252 );
253
254/**
255 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
256 writes the result back to the bit field in the 8-bit port.
257
258 Reads the 8-bit PCI configuration register specified by Address, performs a
259 bitwise OR between the read result and the value specified by
260 OrData, and writes the result to the 8-bit PCI configuration register
261 specified by Address. The value written to the PCI configuration register is
262 returned. This function must guarantee that all PCI read and write operations
263 are serialized. Extra left bits in OrData are stripped.
264
265 If Address > 0x0FFFFFFF, then ASSERT().
266 If StartBit is greater than 7, then ASSERT().
267 If EndBit is greater than 7, then ASSERT().
268 If EndBit is less than StartBit, then ASSERT().
269 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
270
271 @param Address PCI configuration register to write.
272 @param StartBit The ordinal of the least significant bit in the bit field.
273 Range 0..7.
274 @param EndBit The ordinal of the most significant bit in the bit field.
275 Range 0..7.
276 @param OrData The value to OR with the PCI configuration register.
277
278 @return The value written back to the PCI configuration register.
279
280**/
281UINT8
282EFIAPI
283PciBitFieldOr8 (
284 IN UINTN Address,
285 IN UINTN StartBit,
286 IN UINTN EndBit,
287 IN UINT8 OrData
288 );
289
290/**
291 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
292 AND, and writes the result back to the bit field in the 8-bit register.
293
294 Reads the 8-bit PCI configuration register specified by Address, performs a
295 bitwise AND between the read result and the value specified by AndData, and
296 writes the result to the 8-bit PCI configuration register specified by
297 Address. The value written to the PCI configuration register is returned.
298 This function must guarantee that all PCI read and write operations are
299 serialized. Extra left bits in AndData are stripped.
300
301 If Address > 0x0FFFFFFF, then ASSERT().
302 If StartBit is greater than 7, then ASSERT().
303 If EndBit is greater than 7, then ASSERT().
304 If EndBit is less than StartBit, then ASSERT().
305 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
306
307 @param Address PCI configuration register to write.
308 @param StartBit The ordinal of the least significant bit in the bit field.
309 Range 0..7.
310 @param EndBit The ordinal of the most significant bit in the bit field.
311 Range 0..7.
312 @param AndData The value to AND with the PCI configuration register.
313
314 @return The value written back to the PCI configuration register.
315
316**/
317UINT8
318EFIAPI
319PciBitFieldAnd8 (
320 IN UINTN Address,
321 IN UINTN StartBit,
322 IN UINTN EndBit,
323 IN UINT8 AndData
324 );
325
326/**
327 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
328 bitwise OR, and writes the result back to the bit field in the
329 8-bit port.
330
331 Reads the 8-bit PCI configuration register specified by Address, performs a
332 bitwise AND followed by a bitwise OR between the read result and
333 the value specified by AndData, and writes the result to the 8-bit PCI
334 configuration register specified by Address. The value written to the PCI
335 configuration register is returned. This function must guarantee that all PCI
336 read and write operations are serialized. Extra left bits in both AndData and
337 OrData are stripped.
338
339 If Address > 0x0FFFFFFF, then ASSERT().
340 If StartBit is greater than 7, then ASSERT().
341 If EndBit is greater than 7, then ASSERT().
342 If EndBit is less than StartBit, then ASSERT().
343 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
344 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
345
346 @param Address PCI configuration register to write.
347 @param StartBit The ordinal of the least significant bit in the bit field.
348 Range 0..7.
349 @param EndBit The ordinal of the most significant bit in the bit field.
350 Range 0..7.
351 @param AndData The value to AND with the PCI configuration register.
352 @param OrData The value to OR with the result of the AND operation.
353
354 @return The value written back to the PCI configuration register.
355
356**/
357UINT8
358EFIAPI
359PciBitFieldAndThenOr8 (
360 IN UINTN Address,
361 IN UINTN StartBit,
362 IN UINTN EndBit,
363 IN UINT8 AndData,
364 IN UINT8 OrData
365 );
366
367/**
368 Reads a 16-bit PCI configuration register.
369
370 Reads and returns the 16-bit PCI configuration register specified by Address.
371 This function must guarantee that all PCI read and write operations are
372 serialized.
373
374 If Address > 0x0FFFFFFF, then ASSERT().
375 If Address is not aligned on a 16-bit boundary, then ASSERT().
376
377 @param Address Address that encodes the PCI Bus, Device, Function and
378 Register.
379
380 @return The read value from the PCI configuration register.
381
382**/
383UINT16
384EFIAPI
385PciRead16 (
386 IN UINTN Address
387 );
388
389/**
390 Writes a 16-bit PCI configuration register.
391
392 Writes the 16-bit PCI configuration register specified by Address with the
393 value specified by Value. Value is returned. This function must guarantee
394 that all PCI read and write operations are serialized.
395
396 If Address > 0x0FFFFFFF, then ASSERT().
397 If Address is not aligned on a 16-bit boundary, then ASSERT().
398
399 @param Address Address that encodes the PCI Bus, Device, Function and
400 Register.
401 @param Value The value to write.
402
403 @return The value written to the PCI configuration register.
404
405**/
406UINT16
407EFIAPI
408PciWrite16 (
409 IN UINTN Address,
410 IN UINT16 Value
411 );
412
413/**
414 Performs a bitwise OR of a 16-bit PCI configuration register with
415 a 16-bit value.
416
417 Reads the 16-bit PCI configuration register specified by Address, performs a
418 bitwise OR between the read result and the value specified by
419 OrData, and writes the result to the 16-bit PCI configuration register
420 specified by Address. The value written to the PCI configuration register is
421 returned. This function must guarantee that all PCI read and write operations
422 are serialized.
423
424 If Address > 0x0FFFFFFF, then ASSERT().
425 If Address is not aligned on a 16-bit boundary, then ASSERT().
426
427 @param Address Address that encodes the PCI Bus, Device, Function and
428 Register.
429 @param OrData The value to OR with the PCI configuration register.
430
431 @return The value written back to the PCI configuration register.
432
433**/
434UINT16
435EFIAPI
436PciOr16 (
437 IN UINTN Address,
438 IN UINT16 OrData
439 );
440
441/**
442 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
443 value.
444
445 Reads the 16-bit PCI configuration register specified by Address, performs a
446 bitwise AND between the read result and the value specified by AndData, and
447 writes the result to the 16-bit PCI configuration register specified by
448 Address. The value written to the PCI configuration register is returned.
449 This function must guarantee that all PCI read and write operations are
450 serialized.
451
452 If Address > 0x0FFFFFFF, then ASSERT().
453 If Address is not aligned on a 16-bit boundary, then ASSERT().
454
455 @param Address Address that encodes the PCI Bus, Device, Function and
456 Register.
457 @param AndData The value to AND with the PCI configuration register.
458
459 @return The value written back to the PCI configuration register.
460
461**/
462UINT16
463EFIAPI
464PciAnd16 (
465 IN UINTN Address,
466 IN UINT16 AndData
467 );
468
469/**
470 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
471 value, followed a bitwise OR with another 16-bit value.
472
473 Reads the 16-bit PCI configuration register specified by Address, performs a
474 bitwise AND between the read result and the value specified by AndData,
475 performs a bitwise OR between the result of the AND operation and
476 the value specified by OrData, and writes the result to the 16-bit PCI
477 configuration register specified by Address. The value written to the PCI
478 configuration register is returned. This function must guarantee that all PCI
479 read and write operations are serialized.
480
481 If Address > 0x0FFFFFFF, then ASSERT().
482 If Address is not aligned on a 16-bit boundary, then ASSERT().
483
484 @param Address Address that encodes the PCI Bus, Device, Function and
485 Register.
486 @param AndData The value to AND with the PCI configuration register.
487 @param OrData The value to OR with the result of the AND operation.
488
489 @return The value written back to the PCI configuration register.
490
491**/
492UINT16
493EFIAPI
494PciAndThenOr16 (
495 IN UINTN Address,
496 IN UINT16 AndData,
497 IN UINT16 OrData
498 );
499
500/**
501 Reads a bit field of a PCI configuration register.
502
503 Reads the bit field in a 16-bit PCI configuration register. The bit field is
504 specified by the StartBit and the EndBit. The value of the bit field is
505 returned.
506
507 If Address > 0x0FFFFFFF, then ASSERT().
508 If Address is not aligned on a 16-bit boundary, then ASSERT().
509 If StartBit is greater than 15, then ASSERT().
510 If EndBit is greater than 15, then ASSERT().
511 If EndBit is less than StartBit, then ASSERT().
512
513 @param Address PCI configuration register to read.
514 @param StartBit The ordinal of the least significant bit in the bit field.
515 Range 0..15.
516 @param EndBit The ordinal of the most significant bit in the bit field.
517 Range 0..15.
518
519 @return The value of the bit field read from the PCI configuration register.
520
521**/
522UINT16
523EFIAPI
524PciBitFieldRead16 (
525 IN UINTN Address,
526 IN UINTN StartBit,
527 IN UINTN EndBit
528 );
529
530/**
531 Writes a bit field to a PCI configuration register.
532
533 Writes Value to the bit field of the PCI configuration register. The bit
534 field is specified by the StartBit and the EndBit. All other bits in the
535 destination PCI configuration register are preserved. The new value of the
536 16-bit register is returned.
537
538 If Address > 0x0FFFFFFF, then ASSERT().
539 If Address is not aligned on a 16-bit boundary, then ASSERT().
540 If StartBit is greater than 15, then ASSERT().
541 If EndBit is greater than 15, then ASSERT().
542 If EndBit is less than StartBit, then ASSERT().
543 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
544
545 @param Address PCI configuration register to write.
546 @param StartBit The ordinal of the least significant bit in the bit field.
547 Range 0..15.
548 @param EndBit The ordinal of the most significant bit in the bit field.
549 Range 0..15.
550 @param Value New value of the bit field.
551
552 @return The value written back to the PCI configuration register.
553
554**/
555UINT16
556EFIAPI
557PciBitFieldWrite16 (
558 IN UINTN Address,
559 IN UINTN StartBit,
560 IN UINTN EndBit,
561 IN UINT16 Value
562 );
563
564/**
565 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
566 writes the result back to the bit field in the 16-bit port.
567
568 Reads the 16-bit PCI configuration register specified by Address, performs a
569 bitwise OR between the read result and the value specified by
570 OrData, and writes the result to the 16-bit PCI configuration register
571 specified by Address. The value written to the PCI configuration register is
572 returned. This function must guarantee that all PCI read and write operations
573 are serialized. Extra left bits in OrData are stripped.
574
575 If Address > 0x0FFFFFFF, then ASSERT().
576 If Address is not aligned on a 16-bit boundary, then ASSERT().
577 If StartBit is greater than 15, then ASSERT().
578 If EndBit is greater than 15, then ASSERT().
579 If EndBit is less than StartBit, then ASSERT().
580 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
581
582 @param Address PCI configuration register to write.
583 @param StartBit The ordinal of the least significant bit in the bit field.
584 Range 0..15.
585 @param EndBit The ordinal of the most significant bit in the bit field.
586 Range 0..15.
587 @param OrData The value to OR with the PCI configuration register.
588
589 @return The value written back to the PCI configuration register.
590
591**/
592UINT16
593EFIAPI
594PciBitFieldOr16 (
595 IN UINTN Address,
596 IN UINTN StartBit,
597 IN UINTN EndBit,
598 IN UINT16 OrData
599 );
600
601/**
602 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
603 AND, and writes the result back to the bit field in the 16-bit register.
604
605 Reads the 16-bit PCI configuration register specified by Address, performs a
606 bitwise AND between the read result and the value specified by AndData, and
607 writes the result to the 16-bit PCI configuration register specified by
608 Address. The value written to the PCI configuration register is returned.
609 This function must guarantee that all PCI read and write operations are
610 serialized. Extra left bits in AndData are stripped.
611
612 If Address > 0x0FFFFFFF, then ASSERT().
613 If Address is not aligned on a 16-bit boundary, then ASSERT().
614 If StartBit is greater than 15, then ASSERT().
615 If EndBit is greater than 15, then ASSERT().
616 If EndBit is less than StartBit, then ASSERT().
617 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
618
619 @param Address PCI configuration register to write.
620 @param StartBit The ordinal of the least significant bit in the bit field.
621 Range 0..15.
622 @param EndBit The ordinal of the most significant bit in the bit field.
623 Range 0..15.
624 @param AndData The value to AND with the PCI configuration register.
625
626 @return The value written back to the PCI configuration register.
627
628**/
629UINT16
630EFIAPI
631PciBitFieldAnd16 (
632 IN UINTN Address,
633 IN UINTN StartBit,
634 IN UINTN EndBit,
635 IN UINT16 AndData
636 );
637
638/**
639 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
640 bitwise OR, and writes the result back to the bit field in the
641 16-bit port.
642
643 Reads the 16-bit PCI configuration register specified by Address, performs a
644 bitwise AND followed by a bitwise OR between the read result and
645 the value specified by AndData, and writes the result to the 16-bit PCI
646 configuration register specified by Address. The value written to the PCI
647 configuration register is returned. This function must guarantee that all PCI
648 read and write operations are serialized. Extra left bits in both AndData and
649 OrData are stripped.
650
651 If Address > 0x0FFFFFFF, then ASSERT().
652 If Address is not aligned on a 16-bit boundary, then ASSERT().
653 If StartBit is greater than 15, then ASSERT().
654 If EndBit is greater than 15, then ASSERT().
655 If EndBit is less than StartBit, then ASSERT().
656 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
657 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
658
659 @param Address PCI configuration register to write.
660 @param StartBit The ordinal of the least significant bit in the bit field.
661 Range 0..15.
662 @param EndBit The ordinal of the most significant bit in the bit field.
663 Range 0..15.
664 @param AndData The value to AND with the PCI configuration register.
665 @param OrData The value to OR with the result of the AND operation.
666
667 @return The value written back to the PCI configuration register.
668
669**/
670UINT16
671EFIAPI
672PciBitFieldAndThenOr16 (
673 IN UINTN Address,
674 IN UINTN StartBit,
675 IN UINTN EndBit,
676 IN UINT16 AndData,
677 IN UINT16 OrData
678 );
679
680/**
681 Reads a 32-bit PCI configuration register.
682
683 Reads and returns the 32-bit PCI configuration register specified by Address.
684 This function must guarantee that all PCI read and write operations are
685 serialized.
686
687 If Address > 0x0FFFFFFF, then ASSERT().
688 If Address is not aligned on a 32-bit boundary, then ASSERT().
689
690 @param Address Address that encodes the PCI Bus, Device, Function and
691 Register.
692
693 @return The read value from the PCI configuration register.
694
695**/
696UINT32
697EFIAPI
698PciRead32 (
699 IN UINTN Address
700 );
701
702/**
703 Writes a 32-bit PCI configuration register.
704
705 Writes the 32-bit PCI configuration register specified by Address with the
706 value specified by Value. Value is returned. This function must guarantee
707 that all PCI read and write operations are serialized.
708
709 If Address > 0x0FFFFFFF, then ASSERT().
710 If Address is not aligned on a 32-bit boundary, then ASSERT().
711
712 @param Address Address that encodes the PCI Bus, Device, Function and
713 Register.
714 @param Value The value to write.
715
716 @return The value written to the PCI configuration register.
717
718**/
719UINT32
720EFIAPI
721PciWrite32 (
722 IN UINTN Address,
723 IN UINT32 Value
724 );
725
726/**
727 Performs a bitwise OR of a 32-bit PCI configuration register with
728 a 32-bit value.
729
730 Reads the 32-bit PCI configuration register specified by Address, performs a
731 bitwise OR between the read result and the value specified by
732 OrData, and writes the result to the 32-bit PCI configuration register
733 specified by Address. The value written to the PCI configuration register is
734 returned. This function must guarantee that all PCI read and write operations
735 are serialized.
736
737 If Address > 0x0FFFFFFF, then ASSERT().
738 If Address is not aligned on a 32-bit boundary, then ASSERT().
739
740 @param Address Address that encodes the PCI Bus, Device, Function and
741 Register.
742 @param OrData The value to OR with the PCI configuration register.
743
744 @return The value written back to the PCI configuration register.
745
746**/
747UINT32
748EFIAPI
749PciOr32 (
750 IN UINTN Address,
751 IN UINT32 OrData
752 );
753
754/**
755 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
756 value.
757
758 Reads the 32-bit PCI configuration register specified by Address, performs a
759 bitwise AND between the read result and the value specified by AndData, and
760 writes the result to the 32-bit PCI configuration register specified by
761 Address. The value written to the PCI configuration register is returned.
762 This function must guarantee that all PCI read and write operations are
763 serialized.
764
765 If Address > 0x0FFFFFFF, then ASSERT().
766 If Address is not aligned on a 32-bit boundary, then ASSERT().
767
768 @param Address Address that encodes the PCI Bus, Device, Function and
769 Register.
770 @param AndData The value to AND with the PCI configuration register.
771
772 @return The value written back to the PCI configuration register.
773
774**/
775UINT32
776EFIAPI
777PciAnd32 (
778 IN UINTN Address,
779 IN UINT32 AndData
780 );
781
782/**
783 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
784 value, followed a bitwise OR with another 32-bit value.
785
786 Reads the 32-bit PCI configuration register specified by Address, performs a
787 bitwise AND between the read result and the value specified by AndData,
788 performs a bitwise OR between the result of the AND operation and
789 the value specified by OrData, and writes the result to the 32-bit PCI
790 configuration register specified by Address. The value written to the PCI
791 configuration register is returned. This function must guarantee that all PCI
792 read and write operations are serialized.
793
794 If Address > 0x0FFFFFFF, then ASSERT().
795 If Address is not aligned on a 32-bit boundary, then ASSERT().
796
797 @param Address Address that encodes the PCI Bus, Device, Function and
798 Register.
799 @param AndData The value to AND with the PCI configuration register.
800 @param OrData The value to OR with the result of the AND operation.
801
802 @return The value written back to the PCI configuration register.
803
804**/
805UINT32
806EFIAPI
807PciAndThenOr32 (
808 IN UINTN Address,
809 IN UINT32 AndData,
810 IN UINT32 OrData
811 );
812
813/**
814 Reads a bit field of a PCI configuration register.
815
816 Reads the bit field in a 32-bit PCI configuration register. The bit field is
817 specified by the StartBit and the EndBit. The value of the bit field is
818 returned.
819
820 If Address > 0x0FFFFFFF, then ASSERT().
821 If Address is not aligned on a 32-bit boundary, then ASSERT().
822 If StartBit is greater than 31, then ASSERT().
823 If EndBit is greater than 31, then ASSERT().
824 If EndBit is less than StartBit, then ASSERT().
825
826 @param Address PCI configuration register to read.
827 @param StartBit The ordinal of the least significant bit in the bit field.
828 Range 0..31.
829 @param EndBit The ordinal of the most significant bit in the bit field.
830 Range 0..31.
831
832 @return The value of the bit field read from the PCI configuration register.
833
834**/
835UINT32
836EFIAPI
837PciBitFieldRead32 (
838 IN UINTN Address,
839 IN UINTN StartBit,
840 IN UINTN EndBit
841 );
842
843/**
844 Writes a bit field to a PCI configuration register.
845
846 Writes Value to the bit field of the PCI configuration register. The bit
847 field is specified by the StartBit and the EndBit. All other bits in the
848 destination PCI configuration register are preserved. The new value of the
849 32-bit register is returned.
850
851 If Address > 0x0FFFFFFF, then ASSERT().
852 If Address is not aligned on a 32-bit boundary, then ASSERT().
853 If StartBit is greater than 31, then ASSERT().
854 If EndBit is greater than 31, then ASSERT().
855 If EndBit is less than StartBit, then ASSERT().
856 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
857
858 @param Address PCI configuration register to write.
859 @param StartBit The ordinal of the least significant bit in the bit field.
860 Range 0..31.
861 @param EndBit The ordinal of the most significant bit in the bit field.
862 Range 0..31.
863 @param Value New value of the bit field.
864
865 @return The value written back to the PCI configuration register.
866
867**/
868UINT32
869EFIAPI
870PciBitFieldWrite32 (
871 IN UINTN Address,
872 IN UINTN StartBit,
873 IN UINTN EndBit,
874 IN UINT32 Value
875 );
876
877/**
878 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
879 writes the result back to the bit field in the 32-bit port.
880
881 Reads the 32-bit PCI configuration register specified by Address, performs a
882 bitwise OR between the read result and the value specified by
883 OrData, and writes the result to the 32-bit PCI configuration register
884 specified by Address. The value written to the PCI configuration register is
885 returned. This function must guarantee that all PCI read and write operations
886 are serialized. Extra left bits in OrData are stripped.
887
888 If Address > 0x0FFFFFFF, then ASSERT().
889 If Address is not aligned on a 32-bit boundary, then ASSERT().
890 If StartBit is greater than 31, then ASSERT().
891 If EndBit is greater than 31, then ASSERT().
892 If EndBit is less than StartBit, then ASSERT().
893 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
894
895 @param Address PCI configuration register to write.
896 @param StartBit The ordinal of the least significant bit in the bit field.
897 Range 0..31.
898 @param EndBit The ordinal of the most significant bit in the bit field.
899 Range 0..31.
900 @param OrData The value to OR with the PCI configuration register.
901
902 @return The value written back to the PCI configuration register.
903
904**/
905UINT32
906EFIAPI
907PciBitFieldOr32 (
908 IN UINTN Address,
909 IN UINTN StartBit,
910 IN UINTN EndBit,
911 IN UINT32 OrData
912 );
913
914/**
915 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
916 AND, and writes the result back to the bit field in the 32-bit register.
917
918 Reads the 32-bit PCI configuration register specified by Address, performs a
919 bitwise AND between the read result and the value specified by AndData, and
920 writes the result to the 32-bit PCI configuration register specified by
921 Address. The value written to the PCI configuration register is returned.
922 This function must guarantee that all PCI read and write operations are
923 serialized. Extra left bits in AndData are stripped.
924
925 If Address > 0x0FFFFFFF, then ASSERT().
926 If Address is not aligned on a 32-bit boundary, then ASSERT().
927 If StartBit is greater than 31, then ASSERT().
928 If EndBit is greater than 31, then ASSERT().
929 If EndBit is less than StartBit, then ASSERT().
930 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
931
932 @param Address PCI configuration register to write.
933 @param StartBit The ordinal of the least significant bit in the bit field.
934 Range 0..31.
935 @param EndBit The ordinal of the most significant bit in the bit field.
936 Range 0..31.
937 @param AndData The value to AND with the PCI configuration register.
938
939 @return The value written back to the PCI configuration register.
940
941**/
942UINT32
943EFIAPI
944PciBitFieldAnd32 (
945 IN UINTN Address,
946 IN UINTN StartBit,
947 IN UINTN EndBit,
948 IN UINT32 AndData
949 );
950
951/**
952 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
953 bitwise OR, and writes the result back to the bit field in the
954 32-bit port.
955
956 Reads the 32-bit PCI configuration register specified by Address, performs a
957 bitwise AND followed by a bitwise OR between the read result and
958 the value specified by AndData, and writes the result to the 32-bit PCI
959 configuration register specified by Address. The value written to the PCI
960 configuration register is returned. This function must guarantee that all PCI
961 read and write operations are serialized. Extra left bits in both AndData and
962 OrData are stripped.
963
964 If Address > 0x0FFFFFFF, then ASSERT().
965 If Address is not aligned on a 32-bit boundary, then ASSERT().
966 If StartBit is greater than 31, then ASSERT().
967 If EndBit is greater than 31, then ASSERT().
968 If EndBit is less than StartBit, then ASSERT().
969 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
970 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
971
972 @param Address PCI configuration register to write.
973 @param StartBit The ordinal of the least significant bit in the bit field.
974 Range 0..31.
975 @param EndBit The ordinal of the most significant bit in the bit field.
976 Range 0..31.
977 @param AndData The value to AND with the PCI configuration register.
978 @param OrData The value to OR with the result of the AND operation.
979
980 @return The value written back to the PCI configuration register.
981
982**/
983UINT32
984EFIAPI
985PciBitFieldAndThenOr32 (
986 IN UINTN Address,
987 IN UINTN StartBit,
988 IN UINTN EndBit,
989 IN UINT32 AndData,
990 IN UINT32 OrData
991 );
992
993/**
994 Reads a range of PCI configuration registers into a caller supplied buffer.
995
996 Reads the range of PCI configuration registers specified by StartAddress and
997 Size into the buffer specified by Buffer. This function only allows the PCI
998 configuration registers from a single PCI function to be read. Size is
999 returned. When possible 32-bit PCI configuration read cycles are used to read
1000 from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
1001 and 16-bit PCI configuration read cycles may be used at the beginning and the
1002 end of the range.
1003
1004 If StartAddress > 0x0FFFFFFF, then ASSERT().
1005 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1006 If Size > 0 and Buffer is NULL, then ASSERT().
1007
1008 @param StartAddress Starting address that encodes the PCI Bus, Device,
1009 Function and Register.
1010 @param Size Size in bytes of the transfer.
1011 @param Buffer Pointer to a buffer receiving the data read.
1012
1013 @return Size
1014
1015**/
1016UINTN
1017EFIAPI
1018PciReadBuffer (
1019 IN UINTN StartAddress,
1020 IN UINTN Size,
1021 OUT VOID *Buffer
1022 );
1023
1024/**
1025 Copies the data in a caller supplied buffer to a specified range of PCI
1026 configuration space.
1027
1028 Writes the range of PCI configuration registers specified by StartAddress and
1029 Size from the buffer specified by Buffer. This function only allows the PCI
1030 configuration registers from a single PCI function to be written. Size is
1031 returned. When possible 32-bit PCI configuration write cycles are used to
1032 write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1033 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1034 and the end of the range.
1035
1036 If StartAddress > 0x0FFFFFFF, then ASSERT().
1037 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1038 If Size > 0 and Buffer is NULL, then ASSERT().
1039
1040 @param StartAddress Starting address that encodes the PCI Bus, Device,
1041 Function and Register.
1042 @param Size Size in bytes of the transfer.
1043 @param Buffer Pointer to a buffer containing the data to write.
1044
1045 @return Size written to StartAddress.
1046
1047**/
1048UINTN
1049EFIAPI
1050PciWriteBuffer (
1051 IN UINTN StartAddress,
1052 IN UINTN Size,
1053 IN VOID *Buffer
1054 );
1055
1056#endif
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