PciLib.h@ 48674

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1	/** @file
2	Provides services to access PCI Configuration Space.
3
4	These functions perform PCI configuration cycles using the default PCI configuration
5	access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
6	or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
7	alternate access method. Modules will typically use the PCI Library for its PCI configuration
8	accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
9	PCI Express Library may be used in conjunction with the PCI Library. The functionality of
10	these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use
11	explicit access methods.
12
13	Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
14	This program and the accompanying materials
15	are licensed and made available under the terms and conditions of the BSD License
16	which accompanies this distribution. The full text of the license may be found at
17	http://opensource.org/licenses/bsd-license.php
18
19	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
20	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21
22	**/
23
24	#ifndef __PCI_LIB_H__
25	#define __PCI_LIB_H__
26
27	/**
28	Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
29	address that can be passed to the PCI Library functions.
30
31	@param Bus PCI Bus number. Range 0..255.
32	@param Device PCI Device number. Range 0..31.
33	@param Function PCI Function number. Range 0..7.
34	@param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
35	for PCI Express.
36
37	@return The encoded PCI address.
38
39	**/
40	#define PCI_LIB_ADDRESS(Bus,Device,Function,Register) \
41	(((Register) & 0xfff) \| (((Function) & 0x07) << 12) \| (((Device) & 0x1f) << 15) \| (((Bus) & 0xff) << 20))
42
43	/**
44	Registers a PCI device so PCI configuration registers may be accessed after
45	SetVirtualAddressMap().
46
47	Registers the PCI device specified by Address so all the PCI configuration registers
48	associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
49
50	If Address > 0x0FFFFFFF, then ASSERT().
51
52	@param Address Address that encodes the PCI Bus, Device, Function and
53	Register.
54
55	@retval RETURN_SUCCESS The PCI device was registered for runtime access.
56	@retval RETURN_UNSUPPORTED An attempt was made to call this function
57	after ExitBootServices().
58	@retval RETURN_UNSUPPORTED The resources required to access the PCI device
59	at runtime could not be mapped.
60	@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
61	complete the registration.
62
63	**/
64	RETURN_STATUS
65	EFIAPI
66	PciRegisterForRuntimeAccess (
67	IN UINTN Address
68	);
69
70	/**
71	Reads an 8-bit PCI configuration register.
72
73	Reads and returns the 8-bit PCI configuration register specified by Address.
74	This function must guarantee that all PCI read and write operations are
75	serialized.
76
77	If Address > 0x0FFFFFFF, then ASSERT().
78
79	@param Address Address that encodes the PCI Bus, Device, Function and
80	Register.
81
82	@return The read value from the PCI configuration register.
83
84	**/
85	UINT8
86	EFIAPI
87	PciRead8 (
88	IN UINTN Address
89	);
90
91	/**
92	Writes an 8-bit PCI configuration register.
93
94	Writes the 8-bit PCI configuration register specified by Address with the
95	value specified by Value. Value is returned. This function must guarantee
96	that all PCI read and write operations are serialized.
97
98	If Address > 0x0FFFFFFF, then ASSERT().
99
100	@param Address Address that encodes the PCI Bus, Device, Function and
101	Register.
102	@param Value The value to write.
103
104	@return The value written to the PCI configuration register.
105
106	**/
107	UINT8
108	EFIAPI
109	PciWrite8 (
110	IN UINTN Address,
111	IN UINT8 Value
112	);
113
114	/**
115	Performs a bitwise OR of an 8-bit PCI configuration register with
116	an 8-bit value.
117
118	Reads the 8-bit PCI configuration register specified by Address, performs a
119	bitwise OR between the read result and the value specified by
120	OrData, and writes the result to the 8-bit PCI configuration register
121	specified by Address. The value written to the PCI configuration register is
122	returned. This function must guarantee that all PCI read and write operations
123	are serialized.
124
125	If Address > 0x0FFFFFFF, then ASSERT().
126
127	@param Address Address that encodes the PCI Bus, Device, Function and
128	Register.
129	@param OrData The value to OR with the PCI configuration register.
130
131	@return The value written back to the PCI configuration register.
132
133	**/
134	UINT8
135	EFIAPI
136	PciOr8 (
137	IN UINTN Address,
138	IN UINT8 OrData
139	);
140
141	/**
142	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
143	value.
144
145	Reads the 8-bit PCI configuration register specified by Address, performs a
146	bitwise AND between the read result and the value specified by AndData, and
147	writes the result to the 8-bit PCI configuration register specified by
148	Address. The value written to the PCI configuration register is returned.
149	This function must guarantee that all PCI read and write operations are
150	serialized.
151
152	If Address > 0x0FFFFFFF, then ASSERT().
153
154	@param Address Address that encodes the PCI Bus, Device, Function and
155	Register.
156	@param AndData The value to AND with the PCI configuration register.
157
158	@return The value written back to the PCI configuration register.
159
160	**/
161	UINT8
162	EFIAPI
163	PciAnd8 (
164	IN UINTN Address,
165	IN UINT8 AndData
166	);
167
168	/**
169	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
170	value, followed by a bitwise OR with another 8-bit value.
171
172	Reads the 8-bit PCI configuration register specified by Address, performs a
173	bitwise AND between the read result and the value specified by AndData,
174	performs a bitwise OR between the result of the AND operation and
175	the value specified by OrData, and writes the result to the 8-bit PCI
176	configuration register specified by Address. The value written to the PCI
177	configuration register is returned. This function must guarantee that all PCI
178	read and write operations are serialized.
179
180	If Address > 0x0FFFFFFF, then ASSERT().
181
182	@param Address Address that encodes the PCI Bus, Device, Function and
183	Register.
184	@param AndData The value to AND with the PCI configuration register.
185	@param OrData The value to OR with the result of the AND operation.
186
187	@return The value written back to the PCI configuration register.
188
189	**/
190	UINT8
191	EFIAPI
192	PciAndThenOr8 (
193	IN UINTN Address,
194	IN UINT8 AndData,
195	IN UINT8 OrData
196	);
197
198	/**
199	Reads a bit field of a PCI configuration register.
200
201	Reads the bit field in an 8-bit PCI configuration register. The bit field is
202	specified by the StartBit and the EndBit. The value of the bit field is
203	returned.
204
205	If Address > 0x0FFFFFFF, then ASSERT().
206	If StartBit is greater than 7, then ASSERT().
207	If EndBit is greater than 7, then ASSERT().
208	If EndBit is less than StartBit, then ASSERT().
209
210	@param Address PCI configuration register to read.
211	@param StartBit The ordinal of the least significant bit in the bit field.
212	Range 0..7.
213	@param EndBit The ordinal of the most significant bit in the bit field.
214	Range 0..7.
215
216	@return The value of the bit field read from the PCI configuration register.
217
218	**/
219	UINT8
220	EFIAPI
221	PciBitFieldRead8 (
222	IN UINTN Address,
223	IN UINTN StartBit,
224	IN UINTN EndBit
225	);
226
227	/**
228	Writes a bit field to a PCI configuration register.
229
230	Writes Value to the bit field of the PCI configuration register. The bit
231	field is specified by the StartBit and the EndBit. All other bits in the
232	destination PCI configuration register are preserved. The new value of the
233	8-bit register is returned.
234
235	If Address > 0x0FFFFFFF, then ASSERT().
236	If StartBit is greater than 7, then ASSERT().
237	If EndBit is greater than 7, then ASSERT().
238	If EndBit is less than StartBit, then ASSERT().
239
240	@param Address PCI configuration register to write.
241	@param StartBit The ordinal of the least significant bit in the bit field.
242	Range 0..7.
243	@param EndBit The ordinal of the most significant bit in the bit field.
244	Range 0..7.
245	@param Value New value of the bit field.
246
247	@return The value written back to the PCI configuration register.
248
249	**/
250	UINT8
251	EFIAPI
252	PciBitFieldWrite8 (
253	IN UINTN Address,
254	IN UINTN StartBit,
255	IN UINTN EndBit,
256	IN UINT8 Value
257	);
258
259	/**
260	Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
261	writes the result back to the bit field in the 8-bit port.
262
263	Reads the 8-bit PCI configuration register specified by Address, performs a
264	bitwise OR between the read result and the value specified by
265	OrData, and writes the result to the 8-bit PCI configuration register
266	specified by Address. The value written to the PCI configuration register is
267	returned. This function must guarantee that all PCI read and write operations
268	are serialized. Extra left bits in OrData are stripped.
269
270	If Address > 0x0FFFFFFF, then ASSERT().
271	If StartBit is greater than 7, then ASSERT().
272	If EndBit is greater than 7, then ASSERT().
273	If EndBit is less than StartBit, then ASSERT().
274
275	@param Address PCI configuration register to write.
276	@param StartBit The ordinal of the least significant bit in the bit field.
277	Range 0..7.
278	@param EndBit The ordinal of the most significant bit in the bit field.
279	Range 0..7.
280	@param OrData The value to OR with the PCI configuration register.
281
282	@return The value written back to the PCI configuration register.
283
284	**/
285	UINT8
286	EFIAPI
287	PciBitFieldOr8 (
288	IN UINTN Address,
289	IN UINTN StartBit,
290	IN UINTN EndBit,
291	IN UINT8 OrData
292	);
293
294	/**
295	Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
296	AND, and writes the result back to the bit field in the 8-bit register.
297
298	Reads the 8-bit PCI configuration register specified by Address, performs a
299	bitwise AND between the read result and the value specified by AndData, and
300	writes the result to the 8-bit PCI configuration register specified by
301	Address. The value written to the PCI configuration register is returned.
302	This function must guarantee that all PCI read and write operations are
303	serialized. Extra left bits in AndData are stripped.
304
305	If Address > 0x0FFFFFFF, then ASSERT().
306	If StartBit is greater than 7, then ASSERT().
307	If EndBit is greater than 7, then ASSERT().
308	If EndBit is less than StartBit, then ASSERT().
309
310	@param Address PCI configuration register to write.
311	@param StartBit The ordinal of the least significant bit in the bit field.
312	Range 0..7.
313	@param EndBit The ordinal of the most significant bit in the bit field.
314	Range 0..7.
315	@param AndData The value to AND with the PCI configuration register.
316
317	@return The value written back to the PCI configuration register.
318
319	**/
320	UINT8
321	EFIAPI
322	PciBitFieldAnd8 (
323	IN UINTN Address,
324	IN UINTN StartBit,
325	IN UINTN EndBit,
326	IN UINT8 AndData
327	);
328
329	/**
330	Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
331	bitwise OR, and writes the result back to the bit field in the
332	8-bit port.
333
334	Reads the 8-bit PCI configuration register specified by Address, performs a
335	bitwise AND followed by a bitwise OR between the read result and
336	the value specified by AndData, and writes the result to the 8-bit PCI
337	configuration register specified by Address. The value written to the PCI
338	configuration register is returned. This function must guarantee that all PCI
339	read and write operations are serialized. Extra left bits in both AndData and
340	OrData are stripped.
341
342	If Address > 0x0FFFFFFF, then ASSERT().
343	If StartBit is greater than 7, then ASSERT().
344	If EndBit is greater than 7, then ASSERT().
345	If EndBit is less than StartBit, then ASSERT().
346
347	@param Address PCI configuration register to write.
348	@param StartBit The ordinal of the least significant bit in the bit field.
349	Range 0..7.
350	@param EndBit The ordinal of the most significant bit in the bit field.
351	Range 0..7.
352	@param AndData The value to AND with the PCI configuration register.
353	@param OrData The value to OR with the result of the AND operation.
354
355	@return The value written back to the PCI configuration register.
356
357	**/
358	UINT8
359	EFIAPI
360	PciBitFieldAndThenOr8 (
361	IN UINTN Address,
362	IN UINTN StartBit,
363	IN UINTN EndBit,
364	IN UINT8 AndData,
365	IN UINT8 OrData
366	);
367
368	/**
369	Reads a 16-bit PCI configuration register.
370
371	Reads and returns the 16-bit PCI configuration register specified by Address.
372	This function must guarantee that all PCI read and write operations are
373	serialized.
374
375	If Address > 0x0FFFFFFF, then ASSERT().
376	If Address is not aligned on a 16-bit boundary, then ASSERT().
377
378	@param Address Address that encodes the PCI Bus, Device, Function and
379	Register.
380
381	@return The read value from the PCI configuration register.
382
383	**/
384	UINT16
385	EFIAPI
386	PciRead16 (
387	IN UINTN Address
388	);
389
390	/**
391	Writes a 16-bit PCI configuration register.
392
393	Writes the 16-bit PCI configuration register specified by Address with the
394	value specified by Value. Value is returned. This function must guarantee
395	that all PCI read and write operations are serialized.
396
397	If Address > 0x0FFFFFFF, then ASSERT().
398	If Address is not aligned on a 16-bit boundary, then ASSERT().
399
400	@param Address Address that encodes the PCI Bus, Device, Function and
401	Register.
402	@param Value The value to write.
403
404	@return The value written to the PCI configuration register.
405
406	**/
407	UINT16
408	EFIAPI
409	PciWrite16 (
410	IN UINTN Address,
411	IN UINT16 Value
412	);
413
414	/**
415	Performs a bitwise OR of a 16-bit PCI configuration register with
416	a 16-bit value.
417
418	Reads the 16-bit PCI configuration register specified by Address, performs a
419	bitwise OR between the read result and the value specified by
420	OrData, and writes the result to the 16-bit PCI configuration register
421	specified by Address. The value written to the PCI configuration register is
422	returned. This function must guarantee that all PCI read and write operations
423	are serialized.
424
425	If Address > 0x0FFFFFFF, then ASSERT().
426	If Address is not aligned on a 16-bit boundary, then ASSERT().
427
428	@param Address Address that encodes the PCI Bus, Device, Function and
429	Register.
430	@param OrData The value to OR with the PCI configuration register.
431
432	@return The value written back to the PCI configuration register.
433
434	**/
435	UINT16
436	EFIAPI
437	PciOr16 (
438	IN UINTN Address,
439	IN UINT16 OrData
440	);
441
442	/**
443	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
444	value.
445
446	Reads the 16-bit PCI configuration register specified by Address, performs a
447	bitwise AND between the read result and the value specified by AndData, and
448	writes the result to the 16-bit PCI configuration register specified by
449	Address. The value written to the PCI configuration register is returned.
450	This function must guarantee that all PCI read and write operations are
451	serialized.
452
453	If Address > 0x0FFFFFFF, then ASSERT().
454	If Address is not aligned on a 16-bit boundary, then ASSERT().
455
456	@param Address Address that encodes the PCI Bus, Device, Function and
457	Register.
458	@param AndData The value to AND with the PCI configuration register.
459
460	@return The value written back to the PCI configuration register.
461
462	**/
463	UINT16
464	EFIAPI
465	PciAnd16 (
466	IN UINTN Address,
467	IN UINT16 AndData
468	);
469
470	/**
471	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
472	value, followed a bitwise OR with another 16-bit value.
473
474	Reads the 16-bit PCI configuration register specified by Address, performs a
475	bitwise AND between the read result and the value specified by AndData,
476	performs a bitwise OR between the result of the AND operation and
477	the value specified by OrData, and writes the result to the 16-bit PCI
478	configuration register specified by Address. The value written to the PCI
479	configuration register is returned. This function must guarantee that all PCI
480	read and write operations are serialized.
481
482	If Address > 0x0FFFFFFF, then ASSERT().
483	If Address is not aligned on a 16-bit boundary, then ASSERT().
484
485	@param Address Address that encodes the PCI Bus, Device, Function and
486	Register.
487	@param AndData The value to AND with the PCI configuration register.
488	@param OrData The value to OR with the result of the AND operation.
489
490	@return The value written back to the PCI configuration register.
491
492	**/
493	UINT16
494	EFIAPI
495	PciAndThenOr16 (
496	IN UINTN Address,
497	IN UINT16 AndData,
498	IN UINT16 OrData
499	);
500
501	/**
502	Reads a bit field of a PCI configuration register.
503
504	Reads the bit field in a 16-bit PCI configuration register. The bit field is
505	specified by the StartBit and the EndBit. The value of the bit field is
506	returned.
507
508	If Address > 0x0FFFFFFF, then ASSERT().
509	If Address is not aligned on a 16-bit boundary, then ASSERT().
510	If StartBit is greater than 15, then ASSERT().
511	If EndBit is greater than 15, then ASSERT().
512	If EndBit is less than StartBit, then ASSERT().
513
514	@param Address PCI configuration register to read.
515	@param StartBit The ordinal of the least significant bit in the bit field.
516	Range 0..15.
517	@param EndBit The ordinal of the most significant bit in the bit field.
518	Range 0..15.
519
520	@return The value of the bit field read from the PCI configuration register.
521
522	**/
523	UINT16
524	EFIAPI
525	PciBitFieldRead16 (
526	IN UINTN Address,
527	IN UINTN StartBit,
528	IN UINTN EndBit
529	);
530
531	/**
532	Writes a bit field to a PCI configuration register.
533
534	Writes Value to the bit field of the PCI configuration register. The bit
535	field is specified by the StartBit and the EndBit. All other bits in the
536	destination PCI configuration register are preserved. The new value of the
537	16-bit register is returned.
538
539	If Address > 0x0FFFFFFF, then ASSERT().
540	If Address is not aligned on a 16-bit boundary, then ASSERT().
541	If StartBit is greater than 15, then ASSERT().
542	If EndBit is greater than 15, then ASSERT().
543	If EndBit is less than StartBit, then ASSERT().
544
545	@param Address PCI configuration register to write.
546	@param StartBit The ordinal of the least significant bit in the bit field.
547	Range 0..15.
548	@param EndBit The ordinal of the most significant bit in the bit field.
549	Range 0..15.
550	@param Value New value of the bit field.
551
552	@return The value written back to the PCI configuration register.
553
554	**/
555	UINT16
556	EFIAPI
557	PciBitFieldWrite16 (
558	IN UINTN Address,
559	IN UINTN StartBit,
560	IN UINTN EndBit,
561	IN UINT16 Value
562	);
563
564	/**
565	Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
566	writes the result back to the bit field in the 16-bit port.
567
568	Reads the 16-bit PCI configuration register specified by Address, performs a
569	bitwise OR between the read result and the value specified by
570	OrData, and writes the result to the 16-bit PCI configuration register
571	specified by Address. The value written to the PCI configuration register is
572	returned. This function must guarantee that all PCI read and write operations
573	are serialized. Extra left bits in OrData are stripped.
574
575	If Address > 0x0FFFFFFF, then ASSERT().
576	If Address is not aligned on a 16-bit boundary, then ASSERT().
577	If StartBit is greater than 15, then ASSERT().
578	If EndBit is greater than 15, then ASSERT().
579	If EndBit is less than StartBit, then ASSERT().
580
581	@param Address PCI configuration register to write.
582	@param StartBit The ordinal of the least significant bit in the bit field.
583	Range 0..15.
584	@param EndBit The ordinal of the most significant bit in the bit field.
585	Range 0..15.
586	@param OrData The value to OR with the PCI configuration register.
587
588	@return The value written back to the PCI configuration register.
589
590	**/
591	UINT16
592	EFIAPI
593	PciBitFieldOr16 (
594	IN UINTN Address,
595	IN UINTN StartBit,
596	IN UINTN EndBit,
597	IN UINT16 OrData
598	);
599
600	/**
601	Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
602	AND, and writes the result back to the bit field in the 16-bit register.
603
604	Reads the 16-bit PCI configuration register specified by Address, performs a
605	bitwise AND between the read result and the value specified by AndData, and
606	writes the result to the 16-bit PCI configuration register specified by
607	Address. The value written to the PCI configuration register is returned.
608	This function must guarantee that all PCI read and write operations are
609	serialized. Extra left bits in AndData are stripped.
610
611	If Address > 0x0FFFFFFF, then ASSERT().
612	If Address is not aligned on a 16-bit boundary, then ASSERT().
613	If StartBit is greater than 15, then ASSERT().
614	If EndBit is greater than 15, then ASSERT().
615	If EndBit is less than StartBit, then ASSERT().
616
617	@param Address PCI configuration register to write.
618	@param StartBit The ordinal of the least significant bit in the bit field.
619	Range 0..15.
620	@param EndBit The ordinal of the most significant bit in the bit field.
621	Range 0..15.
622	@param AndData The value to AND with the PCI configuration register.
623
624	@return The value written back to the PCI configuration register.
625
626	**/
627	UINT16
628	EFIAPI
629	PciBitFieldAnd16 (
630	IN UINTN Address,
631	IN UINTN StartBit,
632	IN UINTN EndBit,
633	IN UINT16 AndData
634	);
635
636	/**
637	Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
638	bitwise OR, and writes the result back to the bit field in the
639	16-bit port.
640
641	Reads the 16-bit PCI configuration register specified by Address, performs a
642	bitwise AND followed by a bitwise OR between the read result and
643	the value specified by AndData, and writes the result to the 16-bit PCI
644	configuration register specified by Address. The value written to the PCI
645	configuration register is returned. This function must guarantee that all PCI
646	read and write operations are serialized. Extra left bits in both AndData and
647	OrData are stripped.
648
649	If Address > 0x0FFFFFFF, then ASSERT().
650	If Address is not aligned on a 16-bit boundary, then ASSERT().
651	If StartBit is greater than 15, then ASSERT().
652	If EndBit is greater than 15, then ASSERT().
653	If EndBit is less than StartBit, then ASSERT().
654
655	@param Address PCI configuration register to write.
656	@param StartBit The ordinal of the least significant bit in the bit field.
657	Range 0..15.
658	@param EndBit The ordinal of the most significant bit in the bit field.
659	Range 0..15.
660	@param AndData The value to AND with the PCI configuration register.
661	@param OrData The value to OR with the result of the AND operation.
662
663	@return The value written back to the PCI configuration register.
664
665	**/
666	UINT16
667	EFIAPI
668	PciBitFieldAndThenOr16 (
669	IN UINTN Address,
670	IN UINTN StartBit,
671	IN UINTN EndBit,
672	IN UINT16 AndData,
673	IN UINT16 OrData
674	);
675
676	/**
677	Reads a 32-bit PCI configuration register.
678
679	Reads and returns the 32-bit PCI configuration register specified by Address.
680	This function must guarantee that all PCI read and write operations are
681	serialized.
682
683	If Address > 0x0FFFFFFF, then ASSERT().
684	If Address is not aligned on a 32-bit boundary, then ASSERT().
685
686	@param Address Address that encodes the PCI Bus, Device, Function and
687	Register.
688
689	@return The read value from the PCI configuration register.
690
691	**/
692	UINT32
693	EFIAPI
694	PciRead32 (
695	IN UINTN Address
696	);
697
698	/**
699	Writes a 32-bit PCI configuration register.
700
701	Writes the 32-bit PCI configuration register specified by Address with the
702	value specified by Value. Value is returned. This function must guarantee
703	that all PCI read and write operations are serialized.
704
705	If Address > 0x0FFFFFFF, then ASSERT().
706	If Address is not aligned on a 32-bit boundary, then ASSERT().
707
708	@param Address Address that encodes the PCI Bus, Device, Function and
709	Register.
710	@param Value The value to write.
711
712	@return The value written to the PCI configuration register.
713
714	**/
715	UINT32
716	EFIAPI
717	PciWrite32 (
718	IN UINTN Address,
719	IN UINT32 Value
720	);
721
722	/**
723	Performs a bitwise OR of a 32-bit PCI configuration register with
724	a 32-bit value.
725
726	Reads the 32-bit PCI configuration register specified by Address, performs a
727	bitwise OR between the read result and the value specified by
728	OrData, and writes the result to the 32-bit PCI configuration register
729	specified by Address. The value written to the PCI configuration register is
730	returned. This function must guarantee that all PCI read and write operations
731	are serialized.
732
733	If Address > 0x0FFFFFFF, then ASSERT().
734	If Address is not aligned on a 32-bit boundary, then ASSERT().
735
736	@param Address Address that encodes the PCI Bus, Device, Function and
737	Register.
738	@param OrData The value to OR with the PCI configuration register.
739
740	@return The value written back to the PCI configuration register.
741
742	**/
743	UINT32
744	EFIAPI
745	PciOr32 (
746	IN UINTN Address,
747	IN UINT32 OrData
748	);
749
750	/**
751	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
752	value.
753
754	Reads the 32-bit PCI configuration register specified by Address, performs a
755	bitwise AND between the read result and the value specified by AndData, and
756	writes the result to the 32-bit PCI configuration register specified by
757	Address. The value written to the PCI configuration register is returned.
758	This function must guarantee that all PCI read and write operations are
759	serialized.
760
761	If Address > 0x0FFFFFFF, then ASSERT().
762	If Address is not aligned on a 32-bit boundary, then ASSERT().
763
764	@param Address Address that encodes the PCI Bus, Device, Function and
765	Register.
766	@param AndData The value to AND with the PCI configuration register.
767
768	@return The value written back to the PCI configuration register.
769
770	**/
771	UINT32
772	EFIAPI
773	PciAnd32 (
774	IN UINTN Address,
775	IN UINT32 AndData
776	);
777
778	/**
779	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
780	value, followed a bitwise OR with another 32-bit value.
781
782	Reads the 32-bit PCI configuration register specified by Address, performs a
783	bitwise AND between the read result and the value specified by AndData,
784	performs a bitwise OR between the result of the AND operation and
785	the value specified by OrData, and writes the result to the 32-bit PCI
786	configuration register specified by Address. The value written to the PCI
787	configuration register is returned. This function must guarantee that all PCI
788	read and write operations are serialized.
789
790	If Address > 0x0FFFFFFF, then ASSERT().
791	If Address is not aligned on a 32-bit boundary, then ASSERT().
792
793	@param Address Address that encodes the PCI Bus, Device, Function and
794	Register.
795	@param AndData The value to AND with the PCI configuration register.
796	@param OrData The value to OR with the result of the AND operation.
797
798	@return The value written back to the PCI configuration register.
799
800	**/
801	UINT32
802	EFIAPI
803	PciAndThenOr32 (
804	IN UINTN Address,
805	IN UINT32 AndData,
806	IN UINT32 OrData
807	);
808
809	/**
810	Reads a bit field of a PCI configuration register.
811
812	Reads the bit field in a 32-bit PCI configuration register. The bit field is
813	specified by the StartBit and the EndBit. The value of the bit field is
814	returned.
815
816	If Address > 0x0FFFFFFF, then ASSERT().
817	If Address is not aligned on a 32-bit boundary, then ASSERT().
818	If StartBit is greater than 31, then ASSERT().
819	If EndBit is greater than 31, then ASSERT().
820	If EndBit is less than StartBit, then ASSERT().
821
822	@param Address PCI configuration register to read.
823	@param StartBit The ordinal of the least significant bit in the bit field.
824	Range 0..31.
825	@param EndBit The ordinal of the most significant bit in the bit field.
826	Range 0..31.
827
828	@return The value of the bit field read from the PCI configuration register.
829
830	**/
831	UINT32
832	EFIAPI
833	PciBitFieldRead32 (
834	IN UINTN Address,
835	IN UINTN StartBit,
836	IN UINTN EndBit
837	);
838
839	/**
840	Writes a bit field to a PCI configuration register.
841
842	Writes Value to the bit field of the PCI configuration register. The bit
843	field is specified by the StartBit and the EndBit. All other bits in the
844	destination PCI configuration register are preserved. The new value of the
845	32-bit register is returned.
846
847	If Address > 0x0FFFFFFF, then ASSERT().
848	If Address is not aligned on a 32-bit boundary, then ASSERT().
849	If StartBit is greater than 31, then ASSERT().
850	If EndBit is greater than 31, then ASSERT().
851	If EndBit is less than StartBit, then ASSERT().
852
853	@param Address PCI configuration register to write.
854	@param StartBit The ordinal of the least significant bit in the bit field.
855	Range 0..31.
856	@param EndBit The ordinal of the most significant bit in the bit field.
857	Range 0..31.
858	@param Value New value of the bit field.
859
860	@return The value written back to the PCI configuration register.
861
862	**/
863	UINT32
864	EFIAPI
865	PciBitFieldWrite32 (
866	IN UINTN Address,
867	IN UINTN StartBit,
868	IN UINTN EndBit,
869	IN UINT32 Value
870	);
871
872	/**
873	Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
874	writes the result back to the bit field in the 32-bit port.
875
876	Reads the 32-bit PCI configuration register specified by Address, performs a
877	bitwise OR between the read result and the value specified by
878	OrData, and writes the result to the 32-bit PCI configuration register
879	specified by Address. The value written to the PCI configuration register is
880	returned. This function must guarantee that all PCI read and write operations
881	are serialized. Extra left bits in OrData are stripped.
882
883	If Address > 0x0FFFFFFF, then ASSERT().
884	If Address is not aligned on a 32-bit boundary, then ASSERT().
885	If StartBit is greater than 31, then ASSERT().
886	If EndBit is greater than 31, then ASSERT().
887	If EndBit is less than StartBit, then ASSERT().
888
889	@param Address PCI configuration register to write.
890	@param StartBit The ordinal of the least significant bit in the bit field.
891	Range 0..31.
892	@param EndBit The ordinal of the most significant bit in the bit field.
893	Range 0..31.
894	@param OrData The value to OR with the PCI configuration register.
895
896	@return The value written back to the PCI configuration register.
897
898	**/
899	UINT32
900	EFIAPI
901	PciBitFieldOr32 (
902	IN UINTN Address,
903	IN UINTN StartBit,
904	IN UINTN EndBit,
905	IN UINT32 OrData
906	);
907
908	/**
909	Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
910	AND, and writes the result back to the bit field in the 32-bit register.
911
912	Reads the 32-bit PCI configuration register specified by Address, performs a
913	bitwise AND between the read result and the value specified by AndData, and
914	writes the result to the 32-bit PCI configuration register specified by
915	Address. The value written to the PCI configuration register is returned.
916	This function must guarantee that all PCI read and write operations are
917	serialized. Extra left bits in AndData are stripped.
918
919	If Address > 0x0FFFFFFF, then ASSERT().
920	If Address is not aligned on a 32-bit boundary, then ASSERT().
921	If StartBit is greater than 31, then ASSERT().
922	If EndBit is greater than 31, then ASSERT().
923	If EndBit is less than StartBit, then ASSERT().
924
925	@param Address PCI configuration register to write.
926	@param StartBit The ordinal of the least significant bit in the bit field.
927	Range 0..31.
928	@param EndBit The ordinal of the most significant bit in the bit field.
929	Range 0..31.
930	@param AndData The value to AND with the PCI configuration register.
931
932	@return The value written back to the PCI configuration register.
933
934	**/
935	UINT32
936	EFIAPI
937	PciBitFieldAnd32 (
938	IN UINTN Address,
939	IN UINTN StartBit,
940	IN UINTN EndBit,
941	IN UINT32 AndData
942	);
943
944	/**
945	Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
946	bitwise OR, and writes the result back to the bit field in the
947	32-bit port.
948
949	Reads the 32-bit PCI configuration register specified by Address, performs a
950	bitwise AND followed by a bitwise OR between the read result and
951	the value specified by AndData, and writes the result to the 32-bit PCI
952	configuration register specified by Address. The value written to the PCI
953	configuration register is returned. This function must guarantee that all PCI
954	read and write operations are serialized. Extra left bits in both AndData and
955	OrData are stripped.
956
957	If Address > 0x0FFFFFFF, then ASSERT().
958	If Address is not aligned on a 32-bit boundary, then ASSERT().
959	If StartBit is greater than 31, then ASSERT().
960	If EndBit is greater than 31, then ASSERT().
961	If EndBit is less than StartBit, then ASSERT().
962
963	@param Address PCI configuration register to write.
964	@param StartBit The ordinal of the least significant bit in the bit field.
965	Range 0..31.
966	@param EndBit The ordinal of the most significant bit in the bit field.
967	Range 0..31.
968	@param AndData The value to AND with the PCI configuration register.
969	@param OrData The value to OR with the result of the AND operation.
970
971	@return The value written back to the PCI configuration register.
972
973	**/
974	UINT32
975	EFIAPI
976	PciBitFieldAndThenOr32 (
977	IN UINTN Address,
978	IN UINTN StartBit,
979	IN UINTN EndBit,
980	IN UINT32 AndData,
981	IN UINT32 OrData
982	);
983
984	/**
985	Reads a range of PCI configuration registers into a caller supplied buffer.
986
987	Reads the range of PCI configuration registers specified by StartAddress and
988	Size into the buffer specified by Buffer. This function only allows the PCI
989	configuration registers from a single PCI function to be read. Size is
990	returned. When possible 32-bit PCI configuration read cycles are used to read
991	from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
992	and 16-bit PCI configuration read cycles may be used at the beginning and the
993	end of the range.
994
995	If StartAddress > 0x0FFFFFFF, then ASSERT().
996	If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
997	If Size > 0 and Buffer is NULL, then ASSERT().
998
999	@param StartAddress Starting address that encodes the PCI Bus, Device,
1000	Function and Register.
1001	@param Size Size in bytes of the transfer.
1002	@param Buffer Pointer to a buffer receiving the data read.
1003
1004	@return Size
1005
1006	**/
1007	UINTN
1008	EFIAPI
1009	PciReadBuffer (
1010	IN UINTN StartAddress,
1011	IN UINTN Size,
1012	OUT VOID *Buffer
1013	);
1014
1015	/**
1016	Copies the data in a caller supplied buffer to a specified range of PCI
1017	configuration space.
1018
1019	Writes the range of PCI configuration registers specified by StartAddress and
1020	Size from the buffer specified by Buffer. This function only allows the PCI
1021	configuration registers from a single PCI function to be written. Size is
1022	returned. When possible 32-bit PCI configuration write cycles are used to
1023	write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1024	8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1025	and the end of the range.
1026
1027	If StartAddress > 0x0FFFFFFF, then ASSERT().
1028	If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1029	If Size > 0 and Buffer is NULL, then ASSERT().
1030
1031	@param StartAddress Starting address that encodes the PCI Bus, Device,
1032	Function and Register.
1033	@param Size Size in bytes of the transfer.
1034	@param Buffer Pointer to a buffer containing the data to write.
1035
1036	@return Size written to StartAddress.
1037
1038	**/
1039	UINTN
1040	EFIAPI
1041	PciWriteBuffer (
1042	IN UINTN StartAddress,
1043	IN UINTN Size,
1044	IN VOID *Buffer
1045	);
1046
1047	#endif

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source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Library/PciLib.h@ 48674

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