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source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Protocol/DebugSupport.h

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Devices/EFI/FirmwareNew: Merge edk2-stable-202405 and make it build on aarch64, bugref:4643
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1/** @file
2 DebugSupport protocol and supporting definitions as defined in the UEFI2.4
3 specification.
4
5 The DebugSupport protocol is used by source level debuggers to abstract the
6 processor and handle context save and restore operations.
7
8Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
10Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
11
12SPDX-License-Identifier: BSD-2-Clause-Patent
13
14**/
15
16#ifndef __DEBUG_SUPPORT_H__
17#define __DEBUG_SUPPORT_H__
18
19#include <IndustryStandard/PeImage.h>
20
21typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;
22
23///
24/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.
25///
26#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \
27 { \
28 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \
29 }
30
31///
32/// Processor exception to be hooked.
33/// All exception types for IA32, X64, Itanium and EBC processors are defined.
34///
35typedef INTN EFI_EXCEPTION_TYPE;
36
37///
38/// IA-32 processor exception types.
39///
40#define EXCEPT_IA32_DIVIDE_ERROR 0
41#define EXCEPT_IA32_DEBUG 1
42#define EXCEPT_IA32_NMI 2
43#define EXCEPT_IA32_BREAKPOINT 3
44#define EXCEPT_IA32_OVERFLOW 4
45#define EXCEPT_IA32_BOUND 5
46#define EXCEPT_IA32_INVALID_OPCODE 6
47#define EXCEPT_IA32_DOUBLE_FAULT 8
48#define EXCEPT_IA32_INVALID_TSS 10
49#define EXCEPT_IA32_SEG_NOT_PRESENT 11
50#define EXCEPT_IA32_STACK_FAULT 12
51#define EXCEPT_IA32_GP_FAULT 13
52#define EXCEPT_IA32_PAGE_FAULT 14
53#define EXCEPT_IA32_FP_ERROR 16
54#define EXCEPT_IA32_ALIGNMENT_CHECK 17
55#define EXCEPT_IA32_MACHINE_CHECK 18
56#define EXCEPT_IA32_SIMD 19
57
58///
59/// FXSAVE_STATE.
60/// FP / MMX / XMM registers (see fxrstor instruction definition).
61///
62typedef struct {
63 UINT16 Fcw;
64 UINT16 Fsw;
65 UINT16 Ftw;
66 UINT16 Opcode;
67 UINT32 Eip;
68 UINT16 Cs;
69 UINT16 Reserved1;
70 UINT32 DataOffset;
71 UINT16 Ds;
72 UINT8 Reserved2[10];
73 UINT8 St0Mm0[10], Reserved3[6];
74 UINT8 St1Mm1[10], Reserved4[6];
75 UINT8 St2Mm2[10], Reserved5[6];
76 UINT8 St3Mm3[10], Reserved6[6];
77 UINT8 St4Mm4[10], Reserved7[6];
78 UINT8 St5Mm5[10], Reserved8[6];
79 UINT8 St6Mm6[10], Reserved9[6];
80 UINT8 St7Mm7[10], Reserved10[6];
81 UINT8 Xmm0[16];
82 UINT8 Xmm1[16];
83 UINT8 Xmm2[16];
84 UINT8 Xmm3[16];
85 UINT8 Xmm4[16];
86 UINT8 Xmm5[16];
87 UINT8 Xmm6[16];
88 UINT8 Xmm7[16];
89 UINT8 Reserved11[14 * 16];
90} EFI_FX_SAVE_STATE_IA32;
91
92///
93/// IA-32 processor context definition.
94///
95typedef struct {
96 UINT32 ExceptionData;
97 EFI_FX_SAVE_STATE_IA32 FxSaveState;
98 UINT32 Dr0;
99 UINT32 Dr1;
100 UINT32 Dr2;
101 UINT32 Dr3;
102 UINT32 Dr6;
103 UINT32 Dr7;
104 UINT32 Cr0;
105 UINT32 Cr1; /* Reserved */
106 UINT32 Cr2;
107 UINT32 Cr3;
108 UINT32 Cr4;
109 UINT32 Eflags;
110 UINT32 Ldtr;
111 UINT32 Tr;
112 UINT32 Gdtr[2];
113 UINT32 Idtr[2];
114 UINT32 Eip;
115 UINT32 Gs;
116 UINT32 Fs;
117 UINT32 Es;
118 UINT32 Ds;
119 UINT32 Cs;
120 UINT32 Ss;
121 UINT32 Edi;
122 UINT32 Esi;
123 UINT32 Ebp;
124 UINT32 Esp;
125 UINT32 Ebx;
126 UINT32 Edx;
127 UINT32 Ecx;
128 UINT32 Eax;
129} EFI_SYSTEM_CONTEXT_IA32;
130
131///
132/// x64 processor exception types.
133///
134#define EXCEPT_X64_DIVIDE_ERROR 0
135#define EXCEPT_X64_DEBUG 1
136#define EXCEPT_X64_NMI 2
137#define EXCEPT_X64_BREAKPOINT 3
138#define EXCEPT_X64_OVERFLOW 4
139#define EXCEPT_X64_BOUND 5
140#define EXCEPT_X64_INVALID_OPCODE 6
141#define EXCEPT_X64_DOUBLE_FAULT 8
142#define EXCEPT_X64_INVALID_TSS 10
143#define EXCEPT_X64_SEG_NOT_PRESENT 11
144#define EXCEPT_X64_STACK_FAULT 12
145#define EXCEPT_X64_GP_FAULT 13
146#define EXCEPT_X64_PAGE_FAULT 14
147#define EXCEPT_X64_FP_ERROR 16
148#define EXCEPT_X64_ALIGNMENT_CHECK 17
149#define EXCEPT_X64_MACHINE_CHECK 18
150#define EXCEPT_X64_SIMD 19
151
152///
153/// FXSAVE_STATE.
154/// FP / MMX / XMM registers (see fxrstor instruction definition).
155///
156typedef struct {
157 UINT16 Fcw;
158 UINT16 Fsw;
159 UINT16 Ftw;
160 UINT16 Opcode;
161 UINT64 Rip;
162 UINT64 DataOffset;
163 UINT8 Reserved1[8];
164 UINT8 St0Mm0[10], Reserved2[6];
165 UINT8 St1Mm1[10], Reserved3[6];
166 UINT8 St2Mm2[10], Reserved4[6];
167 UINT8 St3Mm3[10], Reserved5[6];
168 UINT8 St4Mm4[10], Reserved6[6];
169 UINT8 St5Mm5[10], Reserved7[6];
170 UINT8 St6Mm6[10], Reserved8[6];
171 UINT8 St7Mm7[10], Reserved9[6];
172 UINT8 Xmm0[16];
173 UINT8 Xmm1[16];
174 UINT8 Xmm2[16];
175 UINT8 Xmm3[16];
176 UINT8 Xmm4[16];
177 UINT8 Xmm5[16];
178 UINT8 Xmm6[16];
179 UINT8 Xmm7[16];
180 //
181 // NOTE: UEFI 2.0 spec definition as follows.
182 //
183 UINT8 Reserved11[14 * 16];
184} EFI_FX_SAVE_STATE_X64;
185
186///
187/// x64 processor context definition.
188///
189typedef struct {
190 UINT64 ExceptionData;
191 EFI_FX_SAVE_STATE_X64 FxSaveState;
192 UINT64 Dr0;
193 UINT64 Dr1;
194 UINT64 Dr2;
195 UINT64 Dr3;
196 UINT64 Dr6;
197 UINT64 Dr7;
198 UINT64 Cr0;
199 UINT64 Cr1; /* Reserved */
200 UINT64 Cr2;
201 UINT64 Cr3;
202 UINT64 Cr4;
203 UINT64 Cr8;
204 UINT64 Rflags;
205 UINT64 Ldtr;
206 UINT64 Tr;
207 UINT64 Gdtr[2];
208 UINT64 Idtr[2];
209 UINT64 Rip;
210 UINT64 Gs;
211 UINT64 Fs;
212 UINT64 Es;
213 UINT64 Ds;
214 UINT64 Cs;
215 UINT64 Ss;
216 UINT64 Rdi;
217 UINT64 Rsi;
218 UINT64 Rbp;
219 UINT64 Rsp;
220 UINT64 Rbx;
221 UINT64 Rdx;
222 UINT64 Rcx;
223 UINT64 Rax;
224 UINT64 R8;
225 UINT64 R9;
226 UINT64 R10;
227 UINT64 R11;
228 UINT64 R12;
229 UINT64 R13;
230 UINT64 R14;
231 UINT64 R15;
232} EFI_SYSTEM_CONTEXT_X64;
233
234///
235/// Itanium Processor Family Exception types.
236///
237#define EXCEPT_IPF_VHTP_TRANSLATION 0
238#define EXCEPT_IPF_INSTRUCTION_TLB 1
239#define EXCEPT_IPF_DATA_TLB 2
240#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3
241#define EXCEPT_IPF_ALT_DATA_TLB 4
242#define EXCEPT_IPF_DATA_NESTED_TLB 5
243#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6
244#define EXCEPT_IPF_DATA_KEY_MISSED 7
245#define EXCEPT_IPF_DIRTY_BIT 8
246#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9
247#define EXCEPT_IPF_DATA_ACCESS_BIT 10
248#define EXCEPT_IPF_BREAKPOINT 11
249#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12
250//
251// 13 - 19 reserved
252//
253#define EXCEPT_IPF_PAGE_NOT_PRESENT 20
254#define EXCEPT_IPF_KEY_PERMISSION 21
255#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22
256#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23
257#define EXCEPT_IPF_GENERAL_EXCEPTION 24
258#define EXCEPT_IPF_DISABLED_FP_REGISTER 25
259#define EXCEPT_IPF_NAT_CONSUMPTION 26
260#define EXCEPT_IPF_SPECULATION 27
261//
262// 28 reserved
263//
264#define EXCEPT_IPF_DEBUG 29
265#define EXCEPT_IPF_UNALIGNED_REFERENCE 30
266#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31
267#define EXCEPT_IPF_FP_FAULT 32
268#define EXCEPT_IPF_FP_TRAP 33
269#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34
270#define EXCEPT_IPF_TAKEN_BRANCH 35
271#define EXCEPT_IPF_SINGLE_STEP 36
272//
273// 37 - 44 reserved
274//
275#define EXCEPT_IPF_IA32_EXCEPTION 45
276#define EXCEPT_IPF_IA32_INTERCEPT 46
277#define EXCEPT_IPF_IA32_INTERRUPT 47
278
279///
280/// IPF processor context definition.
281///
282typedef struct {
283 //
284 // The first reserved field is necessary to preserve alignment for the correct
285 // bits in UNAT and to insure F2 is 16 byte aligned.
286 //
287 UINT64 Reserved;
288 UINT64 R1;
289 UINT64 R2;
290 UINT64 R3;
291 UINT64 R4;
292 UINT64 R5;
293 UINT64 R6;
294 UINT64 R7;
295 UINT64 R8;
296 UINT64 R9;
297 UINT64 R10;
298 UINT64 R11;
299 UINT64 R12;
300 UINT64 R13;
301 UINT64 R14;
302 UINT64 R15;
303 UINT64 R16;
304 UINT64 R17;
305 UINT64 R18;
306 UINT64 R19;
307 UINT64 R20;
308 UINT64 R21;
309 UINT64 R22;
310 UINT64 R23;
311 UINT64 R24;
312 UINT64 R25;
313 UINT64 R26;
314 UINT64 R27;
315 UINT64 R28;
316 UINT64 R29;
317 UINT64 R30;
318 UINT64 R31;
319
320 UINT64 F2[2];
321 UINT64 F3[2];
322 UINT64 F4[2];
323 UINT64 F5[2];
324 UINT64 F6[2];
325 UINT64 F7[2];
326 UINT64 F8[2];
327 UINT64 F9[2];
328 UINT64 F10[2];
329 UINT64 F11[2];
330 UINT64 F12[2];
331 UINT64 F13[2];
332 UINT64 F14[2];
333 UINT64 F15[2];
334 UINT64 F16[2];
335 UINT64 F17[2];
336 UINT64 F18[2];
337 UINT64 F19[2];
338 UINT64 F20[2];
339 UINT64 F21[2];
340 UINT64 F22[2];
341 UINT64 F23[2];
342 UINT64 F24[2];
343 UINT64 F25[2];
344 UINT64 F26[2];
345 UINT64 F27[2];
346 UINT64 F28[2];
347 UINT64 F29[2];
348 UINT64 F30[2];
349 UINT64 F31[2];
350
351 UINT64 Pr;
352
353 UINT64 B0;
354 UINT64 B1;
355 UINT64 B2;
356 UINT64 B3;
357 UINT64 B4;
358 UINT64 B5;
359 UINT64 B6;
360 UINT64 B7;
361
362 //
363 // application registers
364 //
365 UINT64 ArRsc;
366 UINT64 ArBsp;
367 UINT64 ArBspstore;
368 UINT64 ArRnat;
369
370 UINT64 ArFcr;
371
372 UINT64 ArEflag;
373 UINT64 ArCsd;
374 UINT64 ArSsd;
375 UINT64 ArCflg;
376 UINT64 ArFsr;
377 UINT64 ArFir;
378 UINT64 ArFdr;
379
380 UINT64 ArCcv;
381
382 UINT64 ArUnat;
383
384 UINT64 ArFpsr;
385
386 UINT64 ArPfs;
387 UINT64 ArLc;
388 UINT64 ArEc;
389
390 //
391 // control registers
392 //
393 UINT64 CrDcr;
394 UINT64 CrItm;
395 UINT64 CrIva;
396 UINT64 CrPta;
397 UINT64 CrIpsr;
398 UINT64 CrIsr;
399 UINT64 CrIip;
400 UINT64 CrIfa;
401 UINT64 CrItir;
402 UINT64 CrIipa;
403 UINT64 CrIfs;
404 UINT64 CrIim;
405 UINT64 CrIha;
406
407 //
408 // debug registers
409 //
410 UINT64 Dbr0;
411 UINT64 Dbr1;
412 UINT64 Dbr2;
413 UINT64 Dbr3;
414 UINT64 Dbr4;
415 UINT64 Dbr5;
416 UINT64 Dbr6;
417 UINT64 Dbr7;
418
419 UINT64 Ibr0;
420 UINT64 Ibr1;
421 UINT64 Ibr2;
422 UINT64 Ibr3;
423 UINT64 Ibr4;
424 UINT64 Ibr5;
425 UINT64 Ibr6;
426 UINT64 Ibr7;
427
428 //
429 // virtual registers - nat bits for R1-R31
430 //
431 UINT64 IntNat;
432} EFI_SYSTEM_CONTEXT_IPF;
433
434///
435/// EBC processor exception types.
436///
437#define EXCEPT_EBC_UNDEFINED 0
438#define EXCEPT_EBC_DIVIDE_ERROR 1
439#define EXCEPT_EBC_DEBUG 2
440#define EXCEPT_EBC_BREAKPOINT 3
441#define EXCEPT_EBC_OVERFLOW 4
442#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.
443#define EXCEPT_EBC_STACK_FAULT 6
444#define EXCEPT_EBC_ALIGNMENT_CHECK 7
445#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.
446#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.
447#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.
448///
449/// For coding convenience, define the maximum valid EBC exception.
450///
451#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP
452
453///
454/// EBC processor context definition.
455///
456typedef struct {
457 UINT64 R0;
458 UINT64 R1;
459 UINT64 R2;
460 UINT64 R3;
461 UINT64 R4;
462 UINT64 R5;
463 UINT64 R6;
464 UINT64 R7;
465 UINT64 Flags;
466 UINT64 ControlFlags;
467 UINT64 Ip;
468} EFI_SYSTEM_CONTEXT_EBC;
469
470///
471/// ARM processor exception types.
472///
473#define EXCEPT_ARM_RESET 0
474#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
475#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
476#define EXCEPT_ARM_PREFETCH_ABORT 3
477#define EXCEPT_ARM_DATA_ABORT 4
478#define EXCEPT_ARM_RESERVED 5
479#define EXCEPT_ARM_IRQ 6
480#define EXCEPT_ARM_FIQ 7
481
482///
483/// For coding convenience, define the maximum valid ARM exception.
484///
485#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
486
487///
488/// ARM processor context definition.
489///
490typedef struct {
491 UINT32 R0;
492 UINT32 R1;
493 UINT32 R2;
494 UINT32 R3;
495 UINT32 R4;
496 UINT32 R5;
497 UINT32 R6;
498 UINT32 R7;
499 UINT32 R8;
500 UINT32 R9;
501 UINT32 R10;
502 UINT32 R11;
503 UINT32 R12;
504 UINT32 SP;
505 UINT32 LR;
506 UINT32 PC;
507 UINT32 CPSR;
508 UINT32 DFSR;
509 UINT32 DFAR;
510 UINT32 IFSR;
511 UINT32 IFAR;
512} EFI_SYSTEM_CONTEXT_ARM;
513
514///
515/// AARCH64 processor exception types.
516///
517#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0
518#define EXCEPT_AARCH64_IRQ 1
519#define EXCEPT_AARCH64_FIQ 2
520#define EXCEPT_AARCH64_SERROR 3
521
522///
523/// For coding convenience, define the maximum valid ARM exception.
524///
525#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR
526
527typedef struct {
528 // General Purpose Registers
529 UINT64 X0;
530 UINT64 X1;
531 UINT64 X2;
532 UINT64 X3;
533 UINT64 X4;
534 UINT64 X5;
535 UINT64 X6;
536 UINT64 X7;
537 UINT64 X8;
538 UINT64 X9;
539 UINT64 X10;
540 UINT64 X11;
541 UINT64 X12;
542 UINT64 X13;
543 UINT64 X14;
544 UINT64 X15;
545 UINT64 X16;
546 UINT64 X17;
547 UINT64 X18;
548 UINT64 X19;
549 UINT64 X20;
550 UINT64 X21;
551 UINT64 X22;
552 UINT64 X23;
553 UINT64 X24;
554 UINT64 X25;
555 UINT64 X26;
556 UINT64 X27;
557 UINT64 X28;
558 UINT64 FP; // x29 - Frame pointer
559 UINT64 LR; // x30 - Link Register
560 UINT64 SP; // x31 - Stack pointer
561
562 // FP/SIMD Registers
563 UINT64 V0[2];
564 UINT64 V1[2];
565 UINT64 V2[2];
566 UINT64 V3[2];
567 UINT64 V4[2];
568 UINT64 V5[2];
569 UINT64 V6[2];
570 UINT64 V7[2];
571 UINT64 V8[2];
572 UINT64 V9[2];
573 UINT64 V10[2];
574 UINT64 V11[2];
575 UINT64 V12[2];
576 UINT64 V13[2];
577 UINT64 V14[2];
578 UINT64 V15[2];
579 UINT64 V16[2];
580 UINT64 V17[2];
581 UINT64 V18[2];
582 UINT64 V19[2];
583 UINT64 V20[2];
584 UINT64 V21[2];
585 UINT64 V22[2];
586 UINT64 V23[2];
587 UINT64 V24[2];
588 UINT64 V25[2];
589 UINT64 V26[2];
590 UINT64 V27[2];
591 UINT64 V28[2];
592 UINT64 V29[2];
593 UINT64 V30[2];
594 UINT64 V31[2];
595
596 UINT64 ELR; // Exception Link Register
597 UINT64 SPSR; // Saved Processor Status Register
598 UINT64 FPSR; // Floating Point Status Register
599 UINT64 ESR; // Exception syndrome register
600 UINT64 FAR; // Fault Address Register
601} EFI_SYSTEM_CONTEXT_AARCH64;
602
603///
604/// RISC-V processor exception types.
605///
606#define EXCEPT_RISCV_INST_MISALIGNED 0
607#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
608#define EXCEPT_RISCV_ILLEGAL_INST 2
609#define EXCEPT_RISCV_BREAKPOINT 3
610#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
611#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
612#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
613#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
614#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
615#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
616#define EXCEPT_RISCV_ENV_CALL_FROM_VS_MODE 10
617#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
618#define EXCEPT_RISCV_INST_ACCESS_PAGE_FAULT 12
619#define EXCEPT_RISCV_LOAD_ACCESS_PAGE_FAULT 13
620#define EXCEPT_RISCV_14 14
621#define EXCEPT_RISCV_STORE_ACCESS_PAGE_FAULT 15
622#define EXCEPT_RISCV_16 16
623#define EXCEPT_RISCV_17 17
624#define EXCEPT_RISCV_18 18
625#define EXCEPT_RISCV_19 19
626#define EXCEPT_RISCV_INST_GUEST_PAGE_FAULT 20
627#define EXCEPT_RISCV_LOAD_GUEST_PAGE_FAULT 21
628#define EXCEPT_RISCV_VIRTUAL_INSTRUCTION 22
629#define EXCEPT_RISCV_STORE_GUEST_PAGE_FAULT 23
630#define EXCEPT_RISCV_MAX_EXCEPTIONS (EXCEPT_RISCV_STORE_GUEST_PAGE_FAULT)
631
632///
633/// RISC-V processor exception types for interrupts.
634///
635#define EXCEPT_RISCV_IS_IRQ(x) ((x & 0x8000000000000000UL) != 0)
636#define EXCEPT_RISCV_IRQ_INDEX(x) (x & 0x7FFFFFFFFFFFFFFFUL)
637#define EXCEPT_RISCV_IRQ_0 0x8000000000000000UL
638#define EXCEPT_RISCV_IRQ_SOFT_FROM_SMODE 0x8000000000000001UL
639#define EXCEPT_RISCV_IRQ_SOFT_FROM_VSMODE 0x8000000000000002UL
640#define EXCEPT_RISCV_IRQ_SOFT_FROM_MMODE 0x8000000000000003UL
641#define EXCEPT_RISCV_IRQ_4 0x8000000000000004UL
642#define EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE 0x8000000000000005UL
643#define EXCEPT_RISCV_MAX_IRQS (EXCEPT_RISCV_IRQ_INDEX(EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE))
644
645typedef struct {
646 UINT64 X0;
647 UINT64 X1;
648 UINT64 X2;
649 UINT64 X3;
650 UINT64 X4;
651 UINT64 X5;
652 UINT64 X6;
653 UINT64 X7;
654 UINT64 X8;
655 UINT64 X9;
656 UINT64 X10;
657 UINT64 X11;
658 UINT64 X12;
659 UINT64 X13;
660 UINT64 X14;
661 UINT64 X15;
662 UINT64 X16;
663 UINT64 X17;
664 UINT64 X18;
665 UINT64 X19;
666 UINT64 X20;
667 UINT64 X21;
668 UINT64 X22;
669 UINT64 X23;
670 UINT64 X24;
671 UINT64 X25;
672 UINT64 X26;
673 UINT64 X27;
674 UINT64 X28;
675 UINT64 X29;
676 UINT64 X30;
677 UINT64 X31;
678 UINT64 SEPC;
679 UINT32 SSTATUS;
680 UINT32 STVAL;
681} EFI_SYSTEM_CONTEXT_RISCV64;
682
683//
684// LoongArch processor exception types.
685//
686// The exception types is located in the CSR ESTAT
687// register offset 16 bits, width 6 bits.
688//
689// If you want to register an exception hook, you can
690// shfit the number left by 16 bits, and the exception
691// handler will know the types.
692//
693// For example:
694// mCpu->CpuRegisterInterruptHandler (
695// mCpu,
696// (EXCEPT_LOONGARCH_PPI << CSR_ESTAT_EXC_SHIFT),
697// PpiExceptionHandler
698// );
699//
700#define EXCEPT_LOONGARCH_INT 0
701#define EXCEPT_LOONGARCH_PIL 1
702#define EXCEPT_LOONGARCH_PIS 2
703#define EXCEPT_LOONGARCH_PIF 3
704#define EXCEPT_LOONGARCH_PME 4
705#define EXCEPT_LOONGARCH_PNR 5
706#define EXCEPT_LOONGARCH_PNX 6
707#define EXCEPT_LOONGARCH_PPI 7
708#define EXCEPT_LOONGARCH_ADE 8
709#define EXCEPT_LOONGARCH_ALE 9
710#define EXCEPT_LOONGARCH_BCE 10
711#define EXCEPT_LOONGARCH_SYS 11
712#define EXCEPT_LOONGARCH_BRK 12
713#define EXCEPT_LOONGARCH_INE 13
714#define EXCEPT_LOONGARCH_IPE 14
715#define EXCEPT_LOONGARCH_FPD 15
716#define EXCEPT_LOONGARCH_SXD 16
717#define EXCEPT_LOONGARCH_ASXD 17
718#define EXCEPT_LOONGARCH_FPE 18
719#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception.
720
721//
722// LoongArch processor Interrupt types.
723//
724#define EXCEPT_LOONGARCH_INT_SIP0 0
725#define EXCEPT_LOONGARCH_INT_SIP1 1
726#define EXCEPT_LOONGARCH_INT_IP0 2
727#define EXCEPT_LOONGARCH_INT_IP1 3
728#define EXCEPT_LOONGARCH_INT_IP2 4
729#define EXCEPT_LOONGARCH_INT_IP3 5
730#define EXCEPT_LOONGARCH_INT_IP4 6
731#define EXCEPT_LOONGARCH_INT_IP5 7
732#define EXCEPT_LOONGARCH_INT_IP6 8
733#define EXCEPT_LOONGARCH_INT_IP7 9
734#define EXCEPT_LOONGARCH_INT_PMC 10
735#define EXCEPT_LOONGARCH_INT_TIMER 11
736#define EXCEPT_LOONGARCH_INT_IPI 12
737
738//
739// For coding convenience, define the maximum valid
740// LoongArch interrupt.
741//
742#define MAX_LOONGARCH_INTERRUPT 14
743
744typedef struct {
745 UINT64 R0;
746 UINT64 R1;
747 UINT64 R2;
748 UINT64 R3;
749 UINT64 R4;
750 UINT64 R5;
751 UINT64 R6;
752 UINT64 R7;
753 UINT64 R8;
754 UINT64 R9;
755 UINT64 R10;
756 UINT64 R11;
757 UINT64 R12;
758 UINT64 R13;
759 UINT64 R14;
760 UINT64 R15;
761 UINT64 R16;
762 UINT64 R17;
763 UINT64 R18;
764 UINT64 R19;
765 UINT64 R20;
766 UINT64 R21;
767 UINT64 R22;
768 UINT64 R23;
769 UINT64 R24;
770 UINT64 R25;
771 UINT64 R26;
772 UINT64 R27;
773 UINT64 R28;
774 UINT64 R29;
775 UINT64 R30;
776 UINT64 R31;
777
778 UINT64 CRMD; // CuRrent MoDe information
779 UINT64 PRMD; // PRe-exception MoDe information
780 UINT64 EUEN; // Extended component Unit ENable
781 UINT64 MISC; // MISCellaneous controller
782 UINT64 ECFG; // Exception ConFiGuration
783 UINT64 ESTAT; // Exception STATus
784 UINT64 ERA; // Exception Return Address
785 UINT64 BADV; // BAD Virtual address
786 UINT64 BADI; // BAD Instruction
787} EFI_SYSTEM_CONTEXT_LOONGARCH64;
788
789///
790/// Universal EFI_SYSTEM_CONTEXT definition.
791///
792typedef union {
793 EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
794 EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
795 EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
796 EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
797 EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
798 EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
799 EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
800 EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;
801} EFI_SYSTEM_CONTEXT;
802
803//
804// DebugSupport callback function prototypes
805//
806
807/**
808 Registers and enables an exception callback function for the specified exception.
809
810 @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.
811 @param SystemContext Exception content.
812
813**/
814typedef
815VOID
816(EFIAPI *EFI_EXCEPTION_CALLBACK)(
817 IN EFI_EXCEPTION_TYPE ExceptionType,
818 IN OUT EFI_SYSTEM_CONTEXT SystemContext
819 );
820
821/**
822 Registers and enables the on-target debug agent's periodic entry point.
823
824 @param SystemContext Exception content.
825
826**/
827typedef
828VOID
829(EFIAPI *EFI_PERIODIC_CALLBACK)(
830 IN OUT EFI_SYSTEM_CONTEXT SystemContext
831 );
832
833///
834/// Machine type definition
835///
836typedef enum {
837 IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C
838 IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664
839 IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200
840 IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
841 IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2
842 IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64
843} EFI_INSTRUCTION_SET_ARCHITECTURE;
844
845//
846// DebugSupport member function definitions
847//
848
849/**
850 Returns the maximum value that may be used for the ProcessorIndex parameter in
851 RegisterPeriodicCallback() and RegisterExceptionCallback().
852
853 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
854 @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported
855 processor index is returned.
856
857 @retval EFI_SUCCESS The function completed successfully.
858
859**/
860typedef
861EFI_STATUS
862(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(
863 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
864 OUT UINTN *MaxProcessorIndex
865 );
866
867/**
868 Registers a function to be called back periodically in interrupt context.
869
870 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
871 @param ProcessorIndex Specifies which processor the callback function applies to.
872 @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main
873 periodic entry point of the debug agent.
874
875 @retval EFI_SUCCESS The function completed successfully.
876 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback
877 function was previously registered.
878 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback
879 function.
880
881**/
882typedef
883EFI_STATUS
884(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(
885 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
886 IN UINTN ProcessorIndex,
887 IN EFI_PERIODIC_CALLBACK PeriodicCallback
888 );
889
890/**
891 Registers a function to be called when a given processor exception occurs.
892
893 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
894 @param ProcessorIndex Specifies which processor the callback function applies to.
895 @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called
896 when the processor exception specified by ExceptionType occurs.
897 @param ExceptionType Specifies which processor exception to hook.
898
899 @retval EFI_SUCCESS The function completed successfully.
900 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback
901 function was previously registered.
902 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback
903 function.
904
905**/
906typedef
907EFI_STATUS
908(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(
909 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
910 IN UINTN ProcessorIndex,
911 IN EFI_EXCEPTION_CALLBACK ExceptionCallback,
912 IN EFI_EXCEPTION_TYPE ExceptionType
913 );
914
915/**
916 Invalidates processor instruction cache for a memory range. Subsequent execution in this range
917 causes a fresh memory fetch to retrieve code to be executed.
918
919 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
920 @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.
921 @param Start Specifies the physical base of the memory range to be invalidated.
922 @param Length Specifies the minimum number of bytes in the processor's instruction
923 cache to invalidate.
924
925 @retval EFI_SUCCESS The function completed successfully.
926
927**/
928typedef
929EFI_STATUS
930(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(
931 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
932 IN UINTN ProcessorIndex,
933 IN VOID *Start,
934 IN UINT64 Length
935 );
936
937///
938/// This protocol provides the services to allow the debug agent to register
939/// callback functions that are called either periodically or when specific
940/// processor exceptions occur.
941///
942struct _EFI_DEBUG_SUPPORT_PROTOCOL {
943 ///
944 /// Declares the processor architecture for this instance of the EFI Debug Support protocol.
945 ///
946 EFI_INSTRUCTION_SET_ARCHITECTURE Isa;
947 EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;
948 EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;
949 EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;
950 EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;
951};
952
953extern EFI_GUID gEfiDebugSupportProtocolGuid;
954
955#endif
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