1 | /** @file
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2 | Various register numbers and value bits based on the following publications:
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3 | - Intel(R) datasheet 290549-001
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4 | - Intel(R) datasheet 290562-001
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5 | - Intel(R) datasheet 297654-006
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6 | - Intel(R) datasheet 297738-017
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7 |
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8 | Copyright (C) 2015, Red Hat, Inc.
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9 | Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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10 |
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11 | SPDX-License-Identifier: BSD-2-Clause-Patent
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12 | **/
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13 |
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14 | #ifndef __I440FX_PIIX4_H__
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15 | #define __I440FX_PIIX4_H__
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16 |
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17 | #include <Library/PciLib.h>
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18 |
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19 | //
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20 | // Host Bridge Device ID (DID) value for I440FX
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21 | //
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22 | #define INTEL_82441_DEVICE_ID 0x1237
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23 |
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24 | //
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25 | // B/D/F/Type: 0/0/0/PCI
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26 | //
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27 | #define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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28 |
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29 | #define PIIX4_PAM0 0x59
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30 | #define PIIX4_PAM1 0x5A
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31 | #define PIIX4_PAM2 0x5B
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32 | #define PIIX4_PAM3 0x5C
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33 | #define PIIX4_PAM4 0x5D
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34 | #define PIIX4_PAM5 0x5E
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35 | #define PIIX4_PAM6 0x5F
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36 |
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37 | //
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38 | // B/D/F/Type: 0/1/3/PCI
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39 | //
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40 | #ifdef VBOX
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41 | #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 7, 0, (Offset))
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42 | #else
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43 | #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
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44 | #endif
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45 |
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46 | #define PIIX4_PMBA 0x40
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47 | #define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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48 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6)
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49 |
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50 | #define PIIX4_PMREGMISC 0x80
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51 | #define PIIX4_PMREGMISC_PMIOSE BIT0
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52 |
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53 | //
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54 | // IO ports
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55 | //
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56 | #define PIIX4_CPU_HOTPLUG_BASE 0xAF00
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57 |
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58 | #endif
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