| 1 | /** @file
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| 2 |
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| 3 | x86_64 Page Tables structures
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| 4 |
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| 5 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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| 6 | Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>
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| 7 |
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| 8 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 9 |
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| 10 | Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
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| 11 |
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| 12 | **/
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| 13 |
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| 14 | #ifndef PAGE_TABLE_H_
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| 15 | #define PAGE_TABLE_H_
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| 16 |
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| 17 | #include <Base.h>
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| 18 |
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| 19 | #pragma pack(1)
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| 20 |
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| 21 | //
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| 22 | // Page-Map Level-4 Offset (PML4) and
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| 23 | // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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| 24 | //
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| 25 |
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| 26 | typedef union {
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| 27 | struct {
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| 28 | UINT64 Present : 1; // 0 = Not present in memory,
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| 29 | // 1 = Present in memory
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| 30 | UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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| 31 | UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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| 32 | UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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| 33 | // 1 = Write-Through caching
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| 34 | UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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| 35 | UINT64 Accessed : 1; // 0 = Not accessed,
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| 36 | // 1 = Accessed (set by CPU)
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| 37 | UINT64 Reserved : 1; // Reserved
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| 38 | UINT64 MustBeZero : 2; // Must Be Zero
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| 39 | UINT64 Available : 3; // Available for use by system software
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| 40 | UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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| 41 | UINT64 AvabilableHigh : 11; // Available for use by system software
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| 42 | UINT64 Nx : 1; // No Execute bit
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| 43 | } Bits;
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| 44 | UINT64 Uint64;
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| 45 | } PAGE_MAP_AND_DIRECTORY_POINTER;
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| 46 |
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| 47 | //
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| 48 | // Page Table Entry 4KB
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| 49 | //
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| 50 | typedef union {
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| 51 | struct {
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| 52 | UINT64 Present : 1; // 0 = Not present in memory,
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| 53 | // 1 = Present in memory
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| 54 | UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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| 55 | UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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| 56 | UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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| 57 | // 1 = Write-Through caching
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| 58 | UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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| 59 | UINT64 Accessed : 1; // 0 = Not accessed,
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| 60 | // 1 = Accessed (set by CPU)
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| 61 | UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by
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| 62 | // processor on access to page
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| 63 | UINT64 PAT : 1; //
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| 64 | UINT64 Global : 1; // 0 = Not global page, 1 = global page
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| 65 | // TLB not cleared on CR3 write
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| 66 | UINT64 Available : 3; // Available for use by system software
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| 67 | UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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| 68 | UINT64 AvabilableHigh : 11; // Available for use by system software
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| 69 | UINT64 Nx : 1; // 0 = Execute Code,
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| 70 | // 1 = No Code Execution
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| 71 | } Bits;
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| 72 | UINT64 Uint64;
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| 73 | } PAGE_TABLE_4K_ENTRY;
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| 74 |
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| 75 | //
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| 76 | // Page Table Entry 2MB
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| 77 | //
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| 78 | typedef union {
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| 79 | struct {
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| 80 | UINT64 Present : 1; // 0 = Not present in memory,
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| 81 | // 1 = Present in memory
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| 82 | UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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| 83 | UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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| 84 | UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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| 85 | // 1=Write-Through caching
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| 86 | UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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| 87 | UINT64 Accessed : 1; // 0 = Not accessed,
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| 88 | // 1 = Accessed (set by CPU)
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| 89 | UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by
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| 90 | // processor on access to page
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| 91 | UINT64 MustBe1 : 1; // Must be 1
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| 92 | UINT64 Global : 1; // 0 = Not global page, 1 = global page
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| 93 | // TLB not cleared on CR3 write
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| 94 | UINT64 Available : 3; // Available for use by system software
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| 95 | UINT64 PAT : 1; //
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| 96 | UINT64 MustBeZero : 8; // Must be zero;
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| 97 | UINT64 PageTableBaseAddress : 31; // Page Table Base Address
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| 98 | UINT64 AvabilableHigh : 11; // Available for use by system software
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| 99 | UINT64 Nx : 1; // 0 = Execute Code,
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| 100 | // 1 = No Code Execution
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| 101 | } Bits;
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| 102 | UINT64 Uint64;
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| 103 | } PAGE_TABLE_ENTRY;
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| 104 |
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| 105 | //
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| 106 | // Page Table Entry 1GB
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| 107 | //
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| 108 | typedef union {
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| 109 | struct {
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| 110 | UINT64 Present : 1; // 0 = Not present in memory,
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| 111 | // 1 = Present in memory
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| 112 | UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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| 113 | UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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| 114 | UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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| 115 | // 1 = Write-Through caching
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| 116 | UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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| 117 | UINT64 Accessed : 1; // 0 = Not accessed,
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| 118 | // 1 = Accessed (set by CPU)
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| 119 | UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by
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| 120 | // processor on access to page
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| 121 | UINT64 MustBe1 : 1; // Must be 1
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| 122 | UINT64 Global : 1; // 0 = Not global page, 1 = global page
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| 123 | // TLB not cleared on CR3 write
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| 124 | UINT64 Available : 3; // Available for use by system software
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| 125 | UINT64 PAT : 1; //
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| 126 | UINT64 MustBeZero : 17; // Must be zero;
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| 127 | UINT64 PageTableBaseAddress : 22; // Page Table Base Address
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| 128 | UINT64 AvabilableHigh : 11; // Available for use by system software
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| 129 | UINT64 Nx : 1; // 0 = Execute Code,
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| 130 | // 1 = No Code Execution
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| 131 | } Bits;
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| 132 | UINT64 Uint64;
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| 133 | } PAGE_TABLE_1G_ENTRY;
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| 134 |
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| 135 | #pragma pack()
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| 136 |
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| 137 | #define IA32_PG_P BIT0
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| 138 | #define IA32_PG_RW BIT1
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| 139 | #define IA32_PG_PS BIT7
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| 140 |
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| 141 | #define PAGING_PAE_INDEX_MASK 0x1FF
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| 142 |
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| 143 | #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
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| 144 | #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
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| 145 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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| 146 |
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| 147 | #define PAGING_L1_ADDRESS_SHIFT 12
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| 148 | #define PAGING_L2_ADDRESS_SHIFT 21
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| 149 | #define PAGING_L3_ADDRESS_SHIFT 30
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| 150 | #define PAGING_L4_ADDRESS_SHIFT 39
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| 151 |
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| 152 | #define PAGING_PML4E_NUMBER 4
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| 153 |
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| 154 | #define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)
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| 155 | #define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)
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| 156 | #define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)
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| 157 | #define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)
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| 158 | #define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)
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| 159 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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| 160 |
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| 161 | #endif
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