| 1 | /** @file
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| 2 | Public include file for I/O APIC library.
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| 3 |
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| 4 | I/O APIC library assumes I/O APIC is enabled. It does not
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| 5 | handles cases where I/O APIC is disabled.
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| 6 |
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| 7 | Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
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| 8 | This program and the accompanying materials
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| 9 | are licensed and made available under the terms and conditions of the BSD License
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| 10 | which accompanies this distribution. The full text of the license may be found at
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| 11 | http://opensource.org/licenses/bsd-license.php
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| 12 |
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| 13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 15 |
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| 16 | **/
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| 17 | #ifndef __IO_APIC_LIB_H__
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| 18 | #define __IO_APIC_LIB_H__
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| 19 |
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| 20 | /**
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| 21 | Read a 32-bit I/O APIC register.
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| 22 |
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| 23 | If Index is >= 0x100, then ASSERT().
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| 24 |
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| 25 | @param Index Specifies the I/O APIC register to read.
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| 26 |
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| 27 | @return The 32-bit value read from the I/O APIC register specified by Index.
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| 28 | **/
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| 29 | UINT32
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| 30 | EFIAPI
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| 31 | IoApicRead (
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| 32 | IN UINTN Index
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| 33 | );
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| 34 |
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| 35 | /**
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| 36 | Write a 32-bit I/O APIC register.
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| 37 |
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| 38 | If Index is >= 0x100, then ASSERT().
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| 39 |
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| 40 | @param Index Specifies the I/O APIC register to write.
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| 41 | @param Value Specifies the value to write to the I/O APIC register specified by Index.
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| 42 |
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| 43 | @return The 32-bit value written to I/O APIC register specified by Index.
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| 44 | **/
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| 45 | UINT32
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| 46 | EFIAPI
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| 47 | IoApicWrite (
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| 48 | IN UINTN Index,
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| 49 | IN UINT32 Value
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| 50 | );
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| 51 |
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| 52 | /**
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| 53 | Set the interrupt mask of an I/O APIC interrupt.
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| 54 |
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| 55 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
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| 56 |
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| 57 | @param Irq Specifies the I/O APIC interrupt to enable or disable.
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| 58 | @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
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| 59 | If FALSE, then disable the I/O APIC interrupt specified by Irq.
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| 60 | **/
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| 61 | VOID
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| 62 | EFIAPI
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| 63 | IoApicEnableInterrupt (
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| 64 | IN UINTN Irq,
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| 65 | IN BOOLEAN Enable
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| 66 | );
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| 67 |
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| 68 | /**
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| 69 | Configures an I/O APIC interrupt.
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| 70 |
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| 71 | Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
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| 72 | mode to the Local APIC of the currntly executing CPU. The default state of the
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| 73 | entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
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| 74 | be used to enable(unmask) the I/O APIC Interrupt.
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| 75 |
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| 76 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
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| 77 | If Vector >= 0x100, then ASSERT().
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| 78 | If DeliveryMode is not supported, then ASSERT().
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| 79 |
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| 80 | @param Irq Specifies the I/O APIC interrupt to initialize.
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| 81 | @param Vector The 8-bit interrupt vector associated with the I/O APIC
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| 82 | Interrupt. Must be in the range 0x10..0xFE.
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| 83 | @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
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| 84 | interrupt is handled. The only supported values are:
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| 85 | 0: IO_APIC_DELIVERY_MODE_FIXED
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| 86 | 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
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| 87 | 2: IO_APIC_DELIVERY_MODE_SMI
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| 88 | 4: IO_APIC_DELIVERY_MODE_NMI
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| 89 | 5: IO_APIC_DELIVERY_MODE_INIT
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| 90 | 7: IO_APIC_DELIVERY_MODE_EXTINT
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| 91 | @param LevelTriggered TRUE specifies a level triggered interrupt.
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| 92 | FALSE specifies an edge triggered interrupt.
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| 93 | @param AssertionLevel TRUE specified an active high interrupt.
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| 94 | FALSE specifies an active low interrupt.
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| 95 | **/
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| 96 | VOID
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| 97 | EFIAPI
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| 98 | IoApicConfigureInterrupt (
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| 99 | IN UINTN Irq,
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| 100 | IN UINTN Vector,
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| 101 | IN UINTN DeliveryMode,
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| 102 | IN BOOLEAN LevelTriggered,
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| 103 | IN BOOLEAN AssertionLevel
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| 104 | );
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| 105 | #endif
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