| 1 | /** @file
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| 2 | IA32/x64 architecture specific definitions needed by debug transfer protocol.It is only
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| 3 | intended to be used by Debug related module implementation.
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| 4 |
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| 5 | Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
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| 6 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 7 |
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| 8 | **/
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| 9 |
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| 10 | #ifndef __PROCESSOR_CONTEXT_H__
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| 11 | #define __PROCESSOR_CONTEXT_H__
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| 12 |
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| 13 | //
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| 14 | // IA-32/x64 processor register index table
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| 15 | //
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| 16 | #define SOFT_DEBUGGER_REGISTER_DR0 0x00
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| 17 | #define SOFT_DEBUGGER_REGISTER_DR1 0x01
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| 18 | #define SOFT_DEBUGGER_REGISTER_DR2 0x02
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| 19 | #define SOFT_DEBUGGER_REGISTER_DR3 0x03
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| 20 | #define SOFT_DEBUGGER_REGISTER_DR6 0x04
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| 21 | #define SOFT_DEBUGGER_REGISTER_DR7 0x05
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| 22 | #define SOFT_DEBUGGER_REGISTER_EFLAGS 0x06
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| 23 | #define SOFT_DEBUGGER_REGISTER_LDTR 0x07
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| 24 | #define SOFT_DEBUGGER_REGISTER_TR 0x08
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| 25 | #define SOFT_DEBUGGER_REGISTER_GDTR0 0x09 // the low 32bit of GDTR
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| 26 | #define SOFT_DEBUGGER_REGISTER_GDTR1 0x0A // the high 32bit of GDTR
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| 27 | #define SOFT_DEBUGGER_REGISTER_IDTR0 0x0B // the low 32bit of IDTR
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| 28 | #define SOFT_DEBUGGER_REGISTER_IDTR1 0x0C // the high 32bot of IDTR
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| 29 | #define SOFT_DEBUGGER_REGISTER_EIP 0x0D
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| 30 | #define SOFT_DEBUGGER_REGISTER_GS 0x0E
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| 31 | #define SOFT_DEBUGGER_REGISTER_FS 0x0F
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| 32 | #define SOFT_DEBUGGER_REGISTER_ES 0x10
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| 33 | #define SOFT_DEBUGGER_REGISTER_DS 0x11
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| 34 | #define SOFT_DEBUGGER_REGISTER_CS 0x12
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| 35 | #define SOFT_DEBUGGER_REGISTER_SS 0x13
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| 36 | #define SOFT_DEBUGGER_REGISTER_CR0 0x14
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| 37 | #define SOFT_DEBUGGER_REGISTER_CR1 0x15
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| 38 | #define SOFT_DEBUGGER_REGISTER_CR2 0x16
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| 39 | #define SOFT_DEBUGGER_REGISTER_CR3 0x17
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| 40 | #define SOFT_DEBUGGER_REGISTER_CR4 0x18
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| 41 |
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| 42 | #define SOFT_DEBUGGER_REGISTER_DI 0x19
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| 43 | #define SOFT_DEBUGGER_REGISTER_SI 0x1A
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| 44 | #define SOFT_DEBUGGER_REGISTER_BP 0x1B
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| 45 | #define SOFT_DEBUGGER_REGISTER_SP 0x1C
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| 46 | #define SOFT_DEBUGGER_REGISTER_DX 0x1D
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| 47 | #define SOFT_DEBUGGER_REGISTER_CX 0x1E
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| 48 | #define SOFT_DEBUGGER_REGISTER_BX 0x1F
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| 49 | #define SOFT_DEBUGGER_REGISTER_AX 0x20
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| 50 |
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| 51 | //
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| 52 | // This below registers are only available for x64 (not valid for Ia32 mode)
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| 53 | //
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| 54 | #define SOFT_DEBUGGER_REGISTER_CR8 0x21
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| 55 | #define SOFT_DEBUGGER_REGISTER_R8 0x22
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| 56 | #define SOFT_DEBUGGER_REGISTER_R9 0x23
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| 57 | #define SOFT_DEBUGGER_REGISTER_R10 0x24
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| 58 | #define SOFT_DEBUGGER_REGISTER_R11 0x25
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| 59 | #define SOFT_DEBUGGER_REGISTER_R12 0x26
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| 60 | #define SOFT_DEBUGGER_REGISTER_R13 0x27
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| 61 | #define SOFT_DEBUGGER_REGISTER_R14 0x28
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| 62 | #define SOFT_DEBUGGER_REGISTER_R15 0x29
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| 63 |
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| 64 | //
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| 65 | // This below registers are FP / MMX / XMM registers
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| 66 | //
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| 67 | #define SOFT_DEBUGGER_REGISTER_FP_BASE 0x30
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| 68 |
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| 69 | #define SOFT_DEBUGGER_REGISTER_FP_FCW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x00)
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| 70 | #define SOFT_DEBUGGER_REGISTER_FP_FSW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x01)
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| 71 | #define SOFT_DEBUGGER_REGISTER_FP_FTW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x02)
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| 72 | #define SOFT_DEBUGGER_REGISTER_FP_OPCODE (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x03)
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| 73 | #define SOFT_DEBUGGER_REGISTER_FP_EIP (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x04)
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| 74 | #define SOFT_DEBUGGER_REGISTER_FP_CS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x05)
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| 75 | #define SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x06)
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| 76 | #define SOFT_DEBUGGER_REGISTER_FP_DS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x07)
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| 77 | #define SOFT_DEBUGGER_REGISTER_FP_MXCSR (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x08)
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| 78 | #define SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x09)
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| 79 | #define SOFT_DEBUGGER_REGISTER_ST0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0A)
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| 80 | #define SOFT_DEBUGGER_REGISTER_ST1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0B)
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| 81 | #define SOFT_DEBUGGER_REGISTER_ST2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0C)
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| 82 | #define SOFT_DEBUGGER_REGISTER_ST3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0D)
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| 83 | #define SOFT_DEBUGGER_REGISTER_ST4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0E)
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| 84 | #define SOFT_DEBUGGER_REGISTER_ST5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0F)
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| 85 | #define SOFT_DEBUGGER_REGISTER_ST6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x10)
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| 86 | #define SOFT_DEBUGGER_REGISTER_ST7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x11)
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| 87 | #define SOFT_DEBUGGER_REGISTER_XMM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x12)
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| 88 | #define SOFT_DEBUGGER_REGISTER_XMM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x13)
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| 89 | #define SOFT_DEBUGGER_REGISTER_XMM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x14)
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| 90 | #define SOFT_DEBUGGER_REGISTER_XMM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x15)
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| 91 | #define SOFT_DEBUGGER_REGISTER_XMM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x16)
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| 92 | #define SOFT_DEBUGGER_REGISTER_XMM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x17)
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| 93 | #define SOFT_DEBUGGER_REGISTER_XMM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x18)
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| 94 | #define SOFT_DEBUGGER_REGISTER_XMM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x19)
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| 95 | #define SOFT_DEBUGGER_REGISTER_XMM8 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1A)
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| 96 | #define SOFT_DEBUGGER_REGISTER_XMM9 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1B)
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| 97 | #define SOFT_DEBUGGER_REGISTER_XMM10 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1C)
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| 98 | #define SOFT_DEBUGGER_REGISTER_XMM11 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1D)
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| 99 | #define SOFT_DEBUGGER_REGISTER_XMM12 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1E)
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| 100 | #define SOFT_DEBUGGER_REGISTER_XMM13 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1F)
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| 101 | #define SOFT_DEBUGGER_REGISTER_XMM14 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x20)
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| 102 | #define SOFT_DEBUGGER_REGISTER_XMM15 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x21)
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| 103 | #define SOFT_DEBUGGER_REGISTER_MM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x22)
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| 104 | #define SOFT_DEBUGGER_REGISTER_MM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x23)
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| 105 | #define SOFT_DEBUGGER_REGISTER_MM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x24)
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| 106 | #define SOFT_DEBUGGER_REGISTER_MM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x25)
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| 107 | #define SOFT_DEBUGGER_REGISTER_MM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x26)
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| 108 | #define SOFT_DEBUGGER_REGISTER_MM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x27)
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| 109 | #define SOFT_DEBUGGER_REGISTER_MM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x28)
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| 110 | #define SOFT_DEBUGGER_REGISTER_MM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x29)
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| 111 |
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| 112 | #define SOFT_DEBUGGER_REGISTER_MAX SOFT_DEBUGGER_REGISTER_MM7
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| 113 |
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| 114 | #define SOFT_DEBUGGER_MSR_EFER (0xC0000080)
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| 115 |
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| 116 | #pragma pack(1)
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| 117 |
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| 118 | ///
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| 119 | /// FXSAVE_STATE
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| 120 | /// FP / MMX / XMM registers (see fxrstor instruction definition)
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| 121 | ///
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| 122 | typedef struct {
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| 123 | UINT16 Fcw;
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| 124 | UINT16 Fsw;
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| 125 | UINT16 Ftw;
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| 126 | UINT16 Opcode;
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| 127 | UINT32 Eip;
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| 128 | UINT16 Cs;
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| 129 | UINT16 Reserved1;
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| 130 | UINT32 DataOffset;
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| 131 | UINT16 Ds;
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| 132 | UINT8 Reserved2[2];
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| 133 | UINT32 Mxcsr;
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| 134 | UINT32 Mxcsr_Mask;
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| 135 | UINT8 St0Mm0[10];
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| 136 | UINT8 Reserved3[6];
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| 137 | UINT8 St1Mm1[10];
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| 138 | UINT8 Reserved4[6];
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| 139 | UINT8 St2Mm2[10];
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| 140 | UINT8 Reserved5[6];
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| 141 | UINT8 St3Mm3[10];
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| 142 | UINT8 Reserved6[6];
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| 143 | UINT8 St4Mm4[10];
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| 144 | UINT8 Reserved7[6];
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| 145 | UINT8 St5Mm5[10];
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| 146 | UINT8 Reserved8[6];
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| 147 | UINT8 St6Mm6[10];
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| 148 | UINT8 Reserved9[6];
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| 149 | UINT8 St7Mm7[10];
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| 150 | UINT8 Reserved10[6];
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| 151 | UINT8 Xmm0[16];
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| 152 | UINT8 Xmm1[16];
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| 153 | UINT8 Xmm2[16];
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| 154 | UINT8 Xmm3[16];
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| 155 | UINT8 Xmm4[16];
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| 156 | UINT8 Xmm5[16];
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| 157 | UINT8 Xmm6[16];
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| 158 | UINT8 Xmm7[16];
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| 159 | UINT8 Reserved11[14 * 16];
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| 160 | } DEBUG_DATA_IA32_FX_SAVE_STATE;
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| 161 |
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| 162 | ///
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| 163 | /// IA-32 processor context definition
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| 164 | ///
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| 165 | typedef struct {
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| 166 | UINT32 ExceptionData;
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| 167 | DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;
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| 168 | UINT32 Dr0;
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| 169 | UINT32 Dr1;
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| 170 | UINT32 Dr2;
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| 171 | UINT32 Dr3;
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| 172 | UINT32 Dr6;
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| 173 | UINT32 Dr7;
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| 174 | UINT32 Eflags;
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| 175 | UINT32 Ldtr;
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| 176 | UINT32 Tr;
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| 177 | UINT32 Gdtr[2];
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| 178 | UINT32 Idtr[2];
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| 179 | UINT32 Eip;
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| 180 | UINT32 Gs;
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| 181 | UINT32 Fs;
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| 182 | UINT32 Es;
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| 183 | UINT32 Ds;
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| 184 | UINT32 Cs;
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| 185 | UINT32 Ss;
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| 186 | UINT32 Cr0;
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| 187 | UINT32 Cr1; ///< Reserved
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| 188 | UINT32 Cr2;
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| 189 | UINT32 Cr3;
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| 190 | UINT32 Cr4;
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| 191 | UINT32 Edi;
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| 192 | UINT32 Esi;
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| 193 | UINT32 Ebp;
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| 194 | UINT32 Esp;
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| 195 | UINT32 Edx;
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| 196 | UINT32 Ecx;
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| 197 | UINT32 Ebx;
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| 198 | UINT32 Eax;
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| 199 | } DEBUG_DATA_IA32_SYSTEM_CONTEXT;
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| 200 |
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| 201 | ///
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| 202 | /// FXSAVE_STATE
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| 203 | /// FP / MMX / XMM registers (see fxrstor instruction definition)
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| 204 | ///
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| 205 | typedef struct {
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| 206 | UINT16 Fcw;
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| 207 | UINT16 Fsw;
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| 208 | UINT16 Ftw;
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| 209 | UINT16 Opcode;
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| 210 | UINT32 Eip;
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| 211 | UINT16 Cs;
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| 212 | UINT16 Reserved1;
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| 213 | UINT32 DataOffset;
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| 214 | UINT16 Ds;
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| 215 | UINT8 Reserved2[2];
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| 216 | UINT32 Mxcsr;
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| 217 | UINT32 Mxcsr_Mask;
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| 218 | UINT8 St0Mm0[10];
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| 219 | UINT8 Reserved3[6];
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| 220 | UINT8 St1Mm1[10];
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| 221 | UINT8 Reserved4[6];
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| 222 | UINT8 St2Mm2[10];
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| 223 | UINT8 Reserved5[6];
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| 224 | UINT8 St3Mm3[10];
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| 225 | UINT8 Reserved6[6];
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| 226 | UINT8 St4Mm4[10];
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| 227 | UINT8 Reserved7[6];
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| 228 | UINT8 St5Mm5[10];
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| 229 | UINT8 Reserved8[6];
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| 230 | UINT8 St6Mm6[10];
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| 231 | UINT8 Reserved9[6];
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| 232 | UINT8 St7Mm7[10];
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| 233 | UINT8 Reserved10[6];
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| 234 | UINT8 Xmm0[16];
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| 235 | UINT8 Xmm1[16];
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| 236 | UINT8 Xmm2[16];
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| 237 | UINT8 Xmm3[16];
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| 238 | UINT8 Xmm4[16];
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| 239 | UINT8 Xmm5[16];
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| 240 | UINT8 Xmm6[16];
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| 241 | UINT8 Xmm7[16];
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| 242 | UINT8 Xmm8[16];
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| 243 | UINT8 Xmm9[16];
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| 244 | UINT8 Xmm10[16];
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| 245 | UINT8 Xmm11[16];
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| 246 | UINT8 Xmm12[16];
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| 247 | UINT8 Xmm13[16];
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| 248 | UINT8 Xmm14[16];
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| 249 | UINT8 Xmm15[16];
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| 250 | UINT8 Reserved11[6 * 16];
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| 251 | } DEBUG_DATA_X64_FX_SAVE_STATE;
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| 252 |
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| 253 | ///
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| 254 | /// x64 processor context definition
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| 255 | ///
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| 256 | typedef struct {
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| 257 | UINT64 ExceptionData;
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| 258 | DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState;
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| 259 | UINT64 Dr0;
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| 260 | UINT64 Dr1;
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| 261 | UINT64 Dr2;
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| 262 | UINT64 Dr3;
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| 263 | UINT64 Dr6;
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| 264 | UINT64 Dr7;
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| 265 | UINT64 Eflags;
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| 266 | UINT64 Ldtr;
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| 267 | UINT64 Tr;
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| 268 | UINT64 Gdtr[2];
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| 269 | UINT64 Idtr[2];
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| 270 | UINT64 Eip;
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| 271 | UINT64 Gs;
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| 272 | UINT64 Fs;
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| 273 | UINT64 Es;
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| 274 | UINT64 Ds;
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| 275 | UINT64 Cs;
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| 276 | UINT64 Ss;
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| 277 | UINT64 Cr0;
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| 278 | UINT64 Cr1; ///< Reserved
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| 279 | UINT64 Cr2;
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| 280 | UINT64 Cr3;
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| 281 | UINT64 Cr4;
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| 282 | UINT64 Rdi;
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| 283 | UINT64 Rsi;
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| 284 | UINT64 Rbp;
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| 285 | UINT64 Rsp;
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| 286 | UINT64 Rdx;
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| 287 | UINT64 Rcx;
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| 288 | UINT64 Rbx;
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| 289 | UINT64 Rax;
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| 290 | UINT64 Cr8;
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| 291 | UINT64 R8;
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| 292 | UINT64 R9;
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| 293 | UINT64 R10;
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| 294 | UINT64 R11;
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| 295 | UINT64 R12;
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| 296 | UINT64 R13;
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| 297 | UINT64 R14;
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| 298 | UINT64 R15;
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| 299 | } DEBUG_DATA_X64_SYSTEM_CONTEXT;
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| 300 |
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| 301 | #pragma pack()
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| 302 |
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| 303 | #endif
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