| 1 | ;------------------------------------------------------------------------------ ;
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| 2 | ; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
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| 3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent
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| 4 | ;
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| 5 | ; Module Name:
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| 6 | ;
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| 7 | ; ExceptionHandlerAsm.Asm
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| 8 | ;
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| 9 | ; Abstract:
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| 10 | ;
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| 11 | ; x64 CPU Exception Handler
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| 12 | ;
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| 13 | ; Notes:
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| 14 | ;
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| 15 | ;------------------------------------------------------------------------------
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| 16 | %include "Nasm.inc"
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| 17 |
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| 18 | ;
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| 19 | ; Equivalent NASM structure of IA32_DESCRIPTOR
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| 20 | ;
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| 21 | struc IA32_DESCRIPTOR
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| 22 | .Limit CTYPE_UINT16 1
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| 23 | .Base CTYPE_UINTN 1
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| 24 | endstruc
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| 25 |
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| 26 | ;
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| 27 | ; Equivalent NASM structure of IA32_IDT_GATE_DESCRIPTOR
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| 28 | ;
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| 29 | struc IA32_IDT_GATE_DESCRIPTOR
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| 30 | .OffsetLow CTYPE_UINT16 1
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| 31 | .Selector CTYPE_UINT16 1
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| 32 | .Reserved_0 CTYPE_UINT8 1
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| 33 | .GateType CTYPE_UINT8 1
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| 34 | .OffsetHigh CTYPE_UINT16 1
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| 35 | .OffsetUpper CTYPE_UINT32 1
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| 36 | .Reserved_1 CTYPE_UINT32 1
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| 37 | endstruc
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| 38 |
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| 39 | ;
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| 40 | ; CommonExceptionHandler()
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| 41 | ;
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| 42 |
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| 43 | %define VC_EXCEPTION 29
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| 44 |
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| 45 | extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions
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| 46 | extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag
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| 47 | extern ASM_PFX(CommonExceptionHandler)
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| 48 |
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| 49 | SECTION .data
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| 50 |
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| 51 | DEFAULT REL
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| 52 | SECTION .text
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| 53 |
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| 54 | ALIGN 8
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| 55 |
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| 56 | ; Generate 256 IDT vectors.
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| 57 | AsmIdtVectorBegin:
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| 58 | %assign Vector 0
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| 59 | %rep 256
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| 60 | push strict dword %[Vector] ; This instruction pushes sign-extended 8-byte value on stack
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| 61 | push rax
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| 62 | %ifdef NO_ABSOLUTE_RELOCS_IN_TEXT
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| 63 | mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry)
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| 64 | %else
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| 65 | mov rax, ASM_PFX(CommonInterruptEntry)
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| 66 | %endif
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| 67 | jmp rax
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| 68 | %assign Vector Vector+1
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| 69 | %endrep
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| 70 | AsmIdtVectorEnd:
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| 71 |
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| 72 | HookAfterStubHeaderBegin:
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| 73 | push strict dword 0 ; 0 will be fixed
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| 74 | VectorNum:
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| 75 | push rax
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| 76 | %ifdef NO_ABSOLUTE_RELOCS_IN_TEXT
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| 77 | mov rax, strict qword 0 ; mov rax, HookAfterStubHeaderEnd
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| 78 | JmpAbsoluteAddress:
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| 79 | %else
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| 80 | mov rax, HookAfterStubHeaderEnd
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| 81 | %endif
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| 82 | jmp rax
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| 83 | HookAfterStubHeaderEnd:
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| 84 | mov rax, rsp
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| 85 | and sp, 0xfff0 ; make sure 16-byte aligned for exception context
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| 86 | sub rsp, 0x18 ; reserve room for filling exception data later
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| 87 | push rcx
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| 88 | mov rcx, [rax + 8]
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| 89 | bt [ASM_PFX(mErrorCodeFlag)], ecx
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| 90 | jnc .0
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| 91 | push qword [rsp] ; push additional rcx to make stack alignment
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| 92 | .0:
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| 93 | xchg rcx, [rsp] ; restore rcx, save Exception Number in stack
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| 94 | push qword [rax] ; push rax into stack to keep code consistence
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| 95 |
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| 96 | ;---------------------------------------;
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| 97 | ; CommonInterruptEntry ;
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| 98 | ;---------------------------------------;
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| 99 | ; The follow algorithm is used for the common interrupt routine.
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| 100 | ; Entry from each interrupt with a push eax and eax=interrupt number
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| 101 | ; Stack frame would be as follows as specified in IA32 manuals:
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| 102 | ;
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| 103 | ; +---------------------+ <-- 16-byte aligned ensured by processor
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| 104 | ; + Old SS +
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| 105 | ; +---------------------+
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| 106 | ; + Old RSP +
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| 107 | ; +---------------------+
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| 108 | ; + RFlags +
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| 109 | ; +---------------------+
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| 110 | ; + CS +
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| 111 | ; +---------------------+
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| 112 | ; + RIP +
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| 113 | ; +---------------------+
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| 114 | ; + Error Code +
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| 115 | ; +---------------------+
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| 116 | ; + Vector Number +
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| 117 | ; +---------------------+
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| 118 | ; + RBP +
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| 119 | ; +---------------------+ <-- RBP, 16-byte aligned
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| 120 | ; The follow algorithm is used for the common interrupt routine.
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| 121 | global ASM_PFX(CommonInterruptEntry)
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| 122 | ASM_PFX(CommonInterruptEntry):
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| 123 | cli
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| 124 | pop rax
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| 125 | ;
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| 126 | ; All interrupt handlers are invoked through interrupt gates, so
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| 127 | ; IF flag automatically cleared at the entry point
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| 128 | ;
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| 129 | xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx
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| 130 | and rcx, 0xFF
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| 131 | cmp ecx, 32 ; Intel reserved vector for exceptions?
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| 132 | jae NoErrorCode
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| 133 | bt [ASM_PFX(mErrorCodeFlag)], ecx
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| 134 | jc HasErrorCode
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| 135 |
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| 136 | NoErrorCode:
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| 137 |
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| 138 | ;
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| 139 | ; Push a dummy error code on the stack
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| 140 | ; to maintain coherent stack map
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| 141 | ;
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| 142 | push qword [rsp]
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| 143 | mov qword [rsp + 8], 0
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| 144 | HasErrorCode:
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| 145 | push rbp
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| 146 | mov rbp, rsp
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| 147 | push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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| 148 | push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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| 149 |
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| 150 | ;
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| 151 | ; Stack:
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| 152 | ; +---------------------+ <-- 16-byte aligned ensured by processor
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| 153 | ; + Old SS +
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| 154 | ; +---------------------+
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| 155 | ; + Old RSP +
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| 156 | ; +---------------------+
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| 157 | ; + RFlags +
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| 158 | ; +---------------------+
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| 159 | ; + CS +
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| 160 | ; +---------------------+
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| 161 | ; + RIP +
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| 162 | ; +---------------------+
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| 163 | ; + Error Code +
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| 164 | ; +---------------------+
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| 165 | ; + RCX / Vector Number +
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| 166 | ; +---------------------+
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| 167 | ; + RBP +
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| 168 | ; +---------------------+ <-- RBP, 16-byte aligned
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| 169 | ;
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| 170 |
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| 171 | ;
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| 172 | ; Since here the stack pointer is 16-byte aligned, so
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| 173 | ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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| 174 | ; is 16-byte aligned
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| 175 | ;
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| 176 |
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| 177 | ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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| 178 | ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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| 179 | push r15
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| 180 | push r14
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| 181 | push r13
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| 182 | push r12
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| 183 | push r11
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| 184 | push r10
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| 185 | push r9
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| 186 | push r8
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| 187 | push rax
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| 188 | push qword [rbp + 8] ; RCX
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| 189 | push rdx
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| 190 | push rbx
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| 191 | push qword [rbp + 48] ; RSP
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| 192 | push qword [rbp] ; RBP
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| 193 | push rsi
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| 194 | push rdi
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| 195 |
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| 196 | ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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| 197 | movzx rax, word [rbp + 56]
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| 198 | push rax ; for ss
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| 199 | movzx rax, word [rbp + 32]
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| 200 | push rax ; for cs
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| 201 | mov rax, ds
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| 202 | push rax
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| 203 | mov rax, es
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| 204 | push rax
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| 205 | mov rax, fs
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| 206 | push rax
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| 207 | mov rax, gs
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| 208 | push rax
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| 209 |
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| 210 | mov [rbp + 8], rcx ; save vector number
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| 211 |
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| 212 | ;; UINT64 Rip;
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| 213 | push qword [rbp + 24]
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| 214 |
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| 215 | ;; UINT64 Gdtr[2], Idtr[2];
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| 216 | xor rax, rax
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| 217 | push rax
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| 218 | push rax
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| 219 | sidt [rsp]
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| 220 | mov bx, word [rsp]
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| 221 | mov rax, qword [rsp + 2]
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| 222 | mov qword [rsp], rax
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| 223 | mov word [rsp + 8], bx
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| 224 |
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| 225 | xor rax, rax
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| 226 | push rax
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| 227 | push rax
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| 228 | sgdt [rsp]
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| 229 | mov bx, word [rsp]
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| 230 | mov rax, qword [rsp + 2]
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| 231 | mov qword [rsp], rax
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| 232 | mov word [rsp + 8], bx
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| 233 |
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| 234 | ;; UINT64 Ldtr, Tr;
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| 235 | xor rax, rax
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| 236 | str ax
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| 237 | push rax
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| 238 | sldt ax
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| 239 | push rax
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| 240 |
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| 241 | ;; UINT64 RFlags;
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| 242 | push qword [rbp + 40]
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| 243 |
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| 244 | ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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| 245 | mov rax, cr8
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| 246 | push rax
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| 247 | mov rax, cr4
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| 248 | or rax, 0x208
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| 249 | mov cr4, rax
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| 250 | push rax
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| 251 | mov rax, cr3
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| 252 | push rax
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| 253 | mov rax, cr2
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| 254 | push rax
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| 255 | xor rax, rax
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| 256 | push rax
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| 257 | mov rax, cr0
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| 258 | push rax
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| 259 |
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| 260 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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| 261 | cmp qword [rbp + 8], VC_EXCEPTION
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| 262 | je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored
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| 263 |
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| 264 | mov rax, dr7
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| 265 | push rax
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| 266 | mov rax, dr6
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| 267 | push rax
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| 268 | mov rax, dr3
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| 269 | push rax
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| 270 | mov rax, dr2
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| 271 | push rax
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| 272 | mov rax, dr1
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| 273 | push rax
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| 274 | mov rax, dr0
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| 275 | push rax
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| 276 | jmp DrFinish
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| 277 |
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| 278 | VcDebugRegs:
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| 279 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid exception recursion
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| 280 | xor rax, rax
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| 281 | push rax
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| 282 | push rax
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| 283 | push rax
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| 284 | push rax
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| 285 | push rax
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| 286 | push rax
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| 287 |
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| 288 | DrFinish:
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| 289 | ;; FX_SAVE_STATE_X64 FxSaveState;
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| 290 | sub rsp, 512
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| 291 | mov rdi, rsp
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| 292 | fxsave [rdi]
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| 293 |
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| 294 | ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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| 295 | cld
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| 296 |
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| 297 | ;; UINT32 ExceptionData;
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| 298 | push qword [rbp + 16]
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| 299 |
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| 300 | ;; Prepare parameter and call
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| 301 | mov rcx, [rbp + 8]
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| 302 | mov rdx, rsp
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| 303 | ;
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| 304 | ; Per X64 calling convention, allocate maximum parameter stack space
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| 305 | ; and make sure RSP is 16-byte aligned
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| 306 | ;
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| 307 | sub rsp, 4 * 8 + 8
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| 308 | call ASM_PFX(CommonExceptionHandler)
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| 309 | add rsp, 4 * 8 + 8
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| 310 |
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| 311 | ; The follow algorithm is used for clear shadow stack token busy bit.
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| 312 | ; The comment is based on the sample shadow stack.
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| 313 | ; Shadow stack is 32 bytes aligned.
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| 314 | ; The sample shadow stack layout :
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| 315 | ; Address | Context
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| 316 | ; +-------------------------+
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| 317 | ; 0xFB8 | FREE | It is 0xFC0|0x02|(LMA & CS.L), after SAVEPREVSSP.
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| 318 | ; +-------------------------+
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| 319 | ; 0xFC0 | Prev SSP |
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| 320 | ; +-------------------------+
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| 321 | ; 0xFC8 | RIP |
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| 322 | ; +-------------------------+
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| 323 | ; 0xFD0 | CS |
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| 324 | ; +-------------------------+
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| 325 | ; 0xFD8 | 0xFD8 | BUSY | BUSY flag cleared after CLRSSBSY
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| 326 | ; +-------------------------+
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| 327 | ; 0xFE0 | 0xFC0|0x02|(LMA & CS.L) |
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| 328 | ; +-------------------------+
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| 329 | ; Instructions for Intel Control Flow Enforcement Technology (CET) are supported since NASM version 2.15.01.
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| 330 | cmp qword [ASM_PFX(mDoFarReturnFlag)], 0
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| 331 | jz CetDone
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| 332 | mov rax, cr4
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| 333 | and rax, 0x800000 ; Check if CET is enabled
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| 334 | jz CetDone
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| 335 | sub rsp, 0x10
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| 336 | sidt [rsp]
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| 337 | mov rcx, qword [rsp + IA32_DESCRIPTOR.Base]; Get IDT base address
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| 338 | add rsp, 0x10
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| 339 | mov rax, qword [rbp + 8]; Get exception number
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| 340 | sal rax, 0x04 ; Get IDT offset
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| 341 | add rax, rcx ; Get IDT gate descriptor address
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| 342 | mov al, byte [rax + IA32_IDT_GATE_DESCRIPTOR.Reserved_0]
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| 343 | and rax, 0x01 ; Check IST field
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| 344 | jz CetDone
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| 345 | ; SSP should be 0xFC0 at this point
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| 346 | mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token
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| 347 | incsspq rax ; After this SSP should be 0xFE0
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| 348 | saveprevssp ; now the shadow stack restore token will be created at 0xFB8
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| 349 | rdsspq rax ; Read new SSP, SSP should be 0xFE8
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| 350 | sub rax, 0x10
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| 351 | clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 after this
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| 352 | sub rax, 0x20
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| 353 | rstorssp [rax] ; Restore to token at 0xFB8, new SSP will be 0xFB8
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| 354 | mov rax, 0x01 ; Pop off the new save token created
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| 355 | incsspq rax ; SSP should be 0xFC0 now
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| 356 | CetDone:
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| 357 |
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| 358 | cli
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| 359 | ;; UINT64 ExceptionData;
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| 360 | add rsp, 8
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| 361 |
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| 362 | ;; FX_SAVE_STATE_X64 FxSaveState;
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| 363 |
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| 364 | mov rsi, rsp
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| 365 | fxrstor [rsi]
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| 366 | add rsp, 512
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| 367 |
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| 368 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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| 369 | ;; Skip restoration of DRx registers to support in-circuit emualators
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| 370 | ;; or debuggers set breakpoint in interrupt/exception context
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| 371 | add rsp, 8 * 6
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| 372 |
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| 373 | ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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| 374 | pop rax
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| 375 | mov cr0, rax
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| 376 | add rsp, 8 ; not for Cr1
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| 377 | pop rax
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| 378 | mov cr2, rax
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| 379 | pop rax
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| 380 | mov cr3, rax
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| 381 | pop rax
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| 382 | mov cr4, rax
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| 383 | pop rax
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| 384 | mov cr8, rax
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| 385 |
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| 386 | ;; UINT64 RFlags;
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| 387 | pop qword [rbp + 40]
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| 388 |
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| 389 | ;; UINT64 Ldtr, Tr;
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| 390 | ;; UINT64 Gdtr[2], Idtr[2];
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| 391 | ;; Best not let anyone mess with these particular registers...
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| 392 | add rsp, 48
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| 393 |
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| 394 | ;; UINT64 Rip;
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| 395 | pop qword [rbp + 24]
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| 396 |
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| 397 | ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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| 398 | pop rax
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| 399 | ; mov gs, rax ; not for gs
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| 400 | pop rax
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| 401 | ; mov fs, rax ; not for fs
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| 402 | ; (X64 will not use fs and gs, so we do not restore it)
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| 403 | pop rax
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| 404 | mov es, rax
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| 405 | pop rax
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| 406 | mov ds, rax
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| 407 | pop qword [rbp + 32] ; for cs
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| 408 | pop qword [rbp + 56] ; for ss
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| 409 |
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| 410 | ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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| 411 | ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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| 412 | pop rdi
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| 413 | pop rsi
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| 414 | add rsp, 8 ; not for rbp
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| 415 | pop qword [rbp + 48] ; for rsp
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| 416 | pop rbx
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| 417 | pop rdx
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| 418 | pop rcx
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| 419 | pop rax
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| 420 | pop r8
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| 421 | pop r9
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| 422 | pop r10
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| 423 | pop r11
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| 424 | pop r12
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| 425 | pop r13
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| 426 | pop r14
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| 427 | pop r15
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| 428 |
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| 429 | mov rsp, rbp
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| 430 | pop rbp
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| 431 | add rsp, 16
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| 432 | cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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| 433 | jz DoReturn
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| 434 | cmp qword [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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| 435 | jz ErrorCode
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| 436 | jmp qword [rsp - 32]
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| 437 | ErrorCode:
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| 438 | sub rsp, 8
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| 439 | jmp qword [rsp - 24]
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| 440 |
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| 441 | DoReturn:
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| 442 | cmp qword [ASM_PFX(mDoFarReturnFlag)], 0 ; Check if need to do far return instead of IRET
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| 443 | jz DoIret
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| 444 | push rax
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| 445 | mov rax, rsp ; save old RSP to rax
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| 446 | mov rsp, [rsp + 0x20]
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| 447 | push qword [rax + 0x10] ; save CS in new location
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|---|
| 448 | push qword [rax + 0x8] ; save EIP in new location
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|---|
| 449 | push qword [rax + 0x18] ; save EFLAGS in new location
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|---|
| 450 | mov rax, [rax] ; restore rax
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|---|
| 451 | popfq ; restore EFLAGS
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| 452 | retfq
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| 453 | DoIret:
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| 454 | iretq
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| 455 |
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| 456 | ;-------------------------------------------------------------------------------------
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|---|
| 457 | ; GetTemplateAddressMap (&AddressMap);
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| 458 | ;-------------------------------------------------------------------------------------
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|---|
| 459 | ; comments here for definition of address map
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| 460 | global ASM_PFX(AsmGetTemplateAddressMap)
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| 461 | ASM_PFX(AsmGetTemplateAddressMap):
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| 462 | lea rax, [AsmIdtVectorBegin]
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|---|
| 463 | mov qword [rcx], rax
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| 464 | mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 256
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| 465 | lea rax, [HookAfterStubHeaderBegin]
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|---|
| 466 | mov qword [rcx + 0x10], rax
|
|---|
| 467 |
|
|---|
| 468 | %ifdef NO_ABSOLUTE_RELOCS_IN_TEXT
|
|---|
| 469 | ; Fix up CommonInterruptEntry address
|
|---|
| 470 | lea rax, [ASM_PFX(CommonInterruptEntry)]
|
|---|
| 471 | lea rcx, [AsmIdtVectorBegin]
|
|---|
| 472 | %rep 256
|
|---|
| 473 | mov qword [rcx + (JmpAbsoluteAddress - 8 - HookAfterStubHeaderBegin)], rax
|
|---|
| 474 | add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 256
|
|---|
| 475 | %endrep
|
|---|
| 476 | ; Fix up HookAfterStubHeaderEnd
|
|---|
| 477 | lea rax, [HookAfterStubHeaderEnd]
|
|---|
| 478 | lea rcx, [JmpAbsoluteAddress]
|
|---|
| 479 | mov qword [rcx - 8], rax
|
|---|
| 480 | %endif
|
|---|
| 481 |
|
|---|
| 482 | ret
|
|---|
| 483 |
|
|---|
| 484 | ;-------------------------------------------------------------------------------------
|
|---|
| 485 | ; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
|
|---|
| 486 | ;-------------------------------------------------------------------------------------
|
|---|
| 487 | global ASM_PFX(AsmVectorNumFixup)
|
|---|
| 488 | ASM_PFX(AsmVectorNumFixup):
|
|---|
| 489 | mov rax, rdx
|
|---|
| 490 | mov [rcx + (VectorNum - 4 - HookAfterStubHeaderBegin)], al
|
|---|
| 491 | ret
|
|---|
| 492 |
|
|---|
