| 1 | ;------------------------------------------------------------------------------ ;
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| 2 | ; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
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| 3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent
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| 4 | ;
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| 5 | ; Module Name:
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| 6 | ;
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| 7 | ; ExceptionHandlerAsm.Asm
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| 8 | ;
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| 9 | ; Abstract:
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| 10 | ;
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| 11 | ; x64 CPU Exception Handler
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| 12 | ;
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| 13 | ; Notes:
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| 14 | ;
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| 15 | ;------------------------------------------------------------------------------
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| 16 |
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| 17 | ;
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| 18 | ; CommonExceptionHandler()
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| 19 | ;
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| 20 |
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| 21 | %define VC_EXCEPTION 29
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| 22 |
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| 23 | extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions
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| 24 | extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag
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| 25 | extern ASM_PFX(CommonExceptionHandler)
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| 26 |
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| 27 | SECTION .data
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| 28 |
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| 29 | DEFAULT REL
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| 30 | %ifndef NO_ABSOLUTE_RELOCS_IN_TEXT
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| 31 | SECTION .text
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| 32 | %endif
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| 33 |
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| 34 | ALIGN 8
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| 35 |
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| 36 | ; Generate 32 IDT vectors.
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| 37 | ; 32 IDT vectors are enough because interrupts (32+) are not enabled in SEC and PEI phase.
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| 38 | AsmIdtVectorBegin:
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| 39 | %assign Vector 0
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| 40 | %rep 32
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| 41 | push byte %[Vector]
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| 42 | push rax
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| 43 | mov rax, ASM_PFX(CommonInterruptEntry)
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| 44 | jmp rax
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| 45 | %assign Vector Vector+1
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| 46 | %endrep
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| 47 | AsmIdtVectorEnd:
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| 48 |
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| 49 | HookAfterStubHeaderBegin:
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| 50 | db 0x6a ; push
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| 51 | @VectorNum:
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| 52 | db 0 ; 0 will be fixed
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| 53 | push rax
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| 54 | mov rax, HookAfterStubHeaderEnd
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| 55 | jmp rax
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| 56 |
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| 57 | SECTION .text
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| 58 |
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| 59 | HookAfterStubHeaderEnd:
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| 60 | mov rax, rsp
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| 61 | and sp, 0xfff0 ; make sure 16-byte aligned for exception context
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| 62 | sub rsp, 0x18 ; reserve room for filling exception data later
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| 63 | push rcx
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| 64 | mov rcx, [rax + 8]
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| 65 | bt [ASM_PFX(mErrorCodeFlag)], ecx
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| 66 | jnc .0
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| 67 | push qword [rsp] ; push additional rcx to make stack alignment
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| 68 | .0:
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| 69 | xchg rcx, [rsp] ; restore rcx, save Exception Number in stack
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| 70 | push qword [rax] ; push rax into stack to keep code consistence
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| 71 |
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| 72 | ;---------------------------------------;
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| 73 | ; CommonInterruptEntry ;
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| 74 | ;---------------------------------------;
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| 75 | ; The follow algorithm is used for the common interrupt routine.
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| 76 | ; Entry from each interrupt with a push eax and eax=interrupt number
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| 77 | ; Stack frame would be as follows as specified in IA32 manuals:
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| 78 | ;
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| 79 | ; +---------------------+ <-- 16-byte aligned ensured by processor
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| 80 | ; + Old SS +
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| 81 | ; +---------------------+
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| 82 | ; + Old RSP +
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| 83 | ; +---------------------+
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| 84 | ; + RFlags +
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| 85 | ; +---------------------+
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| 86 | ; + CS +
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| 87 | ; +---------------------+
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| 88 | ; + RIP +
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| 89 | ; +---------------------+
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| 90 | ; + Error Code +
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| 91 | ; +---------------------+
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| 92 | ; + Vector Number +
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| 93 | ; +---------------------+
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| 94 | ; + RBP +
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| 95 | ; +---------------------+ <-- RBP, 16-byte aligned
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| 96 | ; The follow algorithm is used for the common interrupt routine.
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| 97 | global ASM_PFX(CommonInterruptEntry)
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| 98 | ASM_PFX(CommonInterruptEntry):
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| 99 | cli
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| 100 | pop rax
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| 101 | ;
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| 102 | ; All interrupt handlers are invoked through interrupt gates, so
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| 103 | ; IF flag automatically cleared at the entry point
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| 104 | ;
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| 105 | xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx
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| 106 | and rcx, 0xFF
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| 107 | cmp ecx, 32 ; Intel reserved vector for exceptions?
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| 108 | jae NoErrorCode
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| 109 | bt [ASM_PFX(mErrorCodeFlag)], ecx
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| 110 | jc HasErrorCode
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| 111 |
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| 112 | NoErrorCode:
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| 113 |
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| 114 | ;
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| 115 | ; Push a dummy error code on the stack
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| 116 | ; to maintain coherent stack map
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| 117 | ;
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| 118 | push qword [rsp]
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| 119 | mov qword [rsp + 8], 0
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| 120 | HasErrorCode:
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| 121 | push rbp
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| 122 | mov rbp, rsp
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| 123 | push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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| 124 | push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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| 125 |
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| 126 | ;
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| 127 | ; Stack:
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| 128 | ; +---------------------+ <-- 16-byte aligned ensured by processor
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| 129 | ; + Old SS +
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| 130 | ; +---------------------+
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| 131 | ; + Old RSP +
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| 132 | ; +---------------------+
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| 133 | ; + RFlags +
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| 134 | ; +---------------------+
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| 135 | ; + CS +
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| 136 | ; +---------------------+
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| 137 | ; + RIP +
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| 138 | ; +---------------------+
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| 139 | ; + Error Code +
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| 140 | ; +---------------------+
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| 141 | ; + RCX / Vector Number +
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| 142 | ; +---------------------+
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| 143 | ; + RBP +
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| 144 | ; +---------------------+ <-- RBP, 16-byte aligned
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| 145 | ;
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| 146 |
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| 147 | ;
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| 148 | ; Since here the stack pointer is 16-byte aligned, so
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| 149 | ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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| 150 | ; is 16-byte aligned
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| 151 | ;
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| 152 |
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| 153 | ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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| 154 | ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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| 155 | push r15
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| 156 | push r14
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| 157 | push r13
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| 158 | push r12
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| 159 | push r11
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| 160 | push r10
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| 161 | push r9
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| 162 | push r8
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| 163 | push rax
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| 164 | push qword [rbp + 8] ; RCX
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| 165 | push rdx
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| 166 | push rbx
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| 167 | push qword [rbp + 48] ; RSP
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| 168 | push qword [rbp] ; RBP
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| 169 | push rsi
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| 170 | push rdi
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| 171 |
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| 172 | ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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| 173 | movzx rax, word [rbp + 56]
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| 174 | push rax ; for ss
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| 175 | movzx rax, word [rbp + 32]
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| 176 | push rax ; for cs
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| 177 | mov rax, ds
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| 178 | push rax
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| 179 | mov rax, es
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| 180 | push rax
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| 181 | mov rax, fs
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| 182 | push rax
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| 183 | mov rax, gs
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| 184 | push rax
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| 185 |
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| 186 | mov [rbp + 8], rcx ; save vector number
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| 187 |
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| 188 | ;; UINT64 Rip;
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| 189 | push qword [rbp + 24]
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| 190 |
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| 191 | ;; UINT64 Gdtr[2], Idtr[2];
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| 192 | xor rax, rax
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| 193 | push rax
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| 194 | push rax
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| 195 | sidt [rsp]
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| 196 | mov bx, word [rsp]
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| 197 | mov rax, qword [rsp + 2]
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| 198 | mov qword [rsp], rax
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| 199 | mov word [rsp + 8], bx
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| 200 |
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| 201 | xor rax, rax
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| 202 | push rax
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| 203 | push rax
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| 204 | sgdt [rsp]
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| 205 | mov bx, word [rsp]
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| 206 | mov rax, qword [rsp + 2]
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| 207 | mov qword [rsp], rax
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| 208 | mov word [rsp + 8], bx
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| 209 |
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| 210 | ;; UINT64 Ldtr, Tr;
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| 211 | xor rax, rax
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| 212 | str ax
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| 213 | push rax
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| 214 | sldt ax
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| 215 | push rax
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| 216 |
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| 217 | ;; UINT64 RFlags;
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| 218 | push qword [rbp + 40]
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| 219 |
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| 220 | ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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| 221 | mov rax, cr8
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| 222 | push rax
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| 223 | mov rax, cr4
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| 224 | or rax, 0x208
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| 225 | mov cr4, rax
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| 226 | push rax
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| 227 | mov rax, cr3
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| 228 | push rax
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| 229 | mov rax, cr2
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| 230 | push rax
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| 231 | xor rax, rax
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| 232 | push rax
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| 233 | mov rax, cr0
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| 234 | push rax
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| 235 |
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| 236 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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| 237 | cmp qword [rbp + 8], VC_EXCEPTION
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| 238 | je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored
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| 239 |
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| 240 | mov rax, dr7
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| 241 | push rax
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| 242 | mov rax, dr6
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| 243 | push rax
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| 244 | mov rax, dr3
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| 245 | push rax
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| 246 | mov rax, dr2
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| 247 | push rax
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| 248 | mov rax, dr1
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| 249 | push rax
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| 250 | mov rax, dr0
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| 251 | push rax
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| 252 | jmp DrFinish
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| 253 |
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| 254 | VcDebugRegs:
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| 255 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid exception recursion
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| 256 | xor rax, rax
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| 257 | push rax
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| 258 | push rax
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| 259 | push rax
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| 260 | push rax
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| 261 | push rax
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| 262 | push rax
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| 263 |
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| 264 | DrFinish:
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| 265 | ;; FX_SAVE_STATE_X64 FxSaveState;
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| 266 | sub rsp, 512
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| 267 | mov rdi, rsp
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| 268 | fxsave [rdi]
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| 269 |
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| 270 | ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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| 271 | cld
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| 272 |
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| 273 | ;; UINT32 ExceptionData;
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| 274 | push qword [rbp + 16]
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| 275 |
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| 276 | ;; Prepare parameter and call
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| 277 | mov rcx, [rbp + 8]
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| 278 | mov rdx, rsp
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| 279 | ;
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| 280 | ; Per X64 calling convention, allocate maximum parameter stack space
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| 281 | ; and make sure RSP is 16-byte aligned
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| 282 | ;
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| 283 | sub rsp, 4 * 8 + 8
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| 284 | call ASM_PFX(CommonExceptionHandler)
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| 285 | add rsp, 4 * 8 + 8
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| 286 |
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| 287 | cli
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| 288 | ;; UINT64 ExceptionData;
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| 289 | add rsp, 8
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| 290 |
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| 291 | ;; FX_SAVE_STATE_X64 FxSaveState;
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| 292 |
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| 293 | mov rsi, rsp
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| 294 | fxrstor [rsi]
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| 295 | add rsp, 512
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| 296 |
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| 297 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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| 298 | ;; Skip restoration of DRx registers to support in-circuit emualators
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| 299 | ;; or debuggers set breakpoint in interrupt/exception context
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| 300 | add rsp, 8 * 6
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| 301 |
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| 302 | ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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| 303 | pop rax
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| 304 | mov cr0, rax
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| 305 | add rsp, 8 ; not for Cr1
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| 306 | pop rax
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| 307 | mov cr2, rax
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| 308 | pop rax
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| 309 | mov cr3, rax
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| 310 | pop rax
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| 311 | mov cr4, rax
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| 312 | pop rax
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| 313 | mov cr8, rax
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| 314 |
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| 315 | ;; UINT64 RFlags;
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| 316 | pop qword [rbp + 40]
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| 317 |
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| 318 | ;; UINT64 Ldtr, Tr;
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| 319 | ;; UINT64 Gdtr[2], Idtr[2];
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| 320 | ;; Best not let anyone mess with these particular registers...
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| 321 | add rsp, 48
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| 322 |
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| 323 | ;; UINT64 Rip;
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| 324 | pop qword [rbp + 24]
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| 325 |
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| 326 | ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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| 327 | pop rax
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| 328 | ; mov gs, rax ; not for gs
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| 329 | pop rax
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| 330 | ; mov fs, rax ; not for fs
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| 331 | ; (X64 will not use fs and gs, so we do not restore it)
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| 332 | pop rax
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| 333 | mov es, rax
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| 334 | pop rax
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| 335 | mov ds, rax
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| 336 | pop qword [rbp + 32] ; for cs
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| 337 | pop qword [rbp + 56] ; for ss
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| 338 |
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| 339 | ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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| 340 | ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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| 341 | pop rdi
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| 342 | pop rsi
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| 343 | add rsp, 8 ; not for rbp
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| 344 | pop qword [rbp + 48] ; for rsp
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| 345 | pop rbx
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| 346 | pop rdx
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| 347 | pop rcx
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| 348 | pop rax
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| 349 | pop r8
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| 350 | pop r9
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| 351 | pop r10
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| 352 | pop r11
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| 353 | pop r12
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| 354 | pop r13
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| 355 | pop r14
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| 356 | pop r15
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| 357 |
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| 358 | mov rsp, rbp
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| 359 | pop rbp
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| 360 | add rsp, 16
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| 361 | cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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| 362 | jz DoReturn
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| 363 | cmp qword [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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| 364 | jz ErrorCode
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| 365 | jmp qword [rsp - 32]
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| 366 | ErrorCode:
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| 367 | sub rsp, 8
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| 368 | jmp qword [rsp - 24]
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| 369 |
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| 370 | DoReturn:
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| 371 | cmp qword [ASM_PFX(mDoFarReturnFlag)], 0 ; Check if need to do far return instead of IRET
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| 372 | jz DoIret
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| 373 | push rax
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| 374 | mov rax, rsp ; save old RSP to rax
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| 375 | mov rsp, [rsp + 0x20]
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| 376 | push qword [rax + 0x10] ; save CS in new location
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| 377 | push qword [rax + 0x8] ; save EIP in new location
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| 378 | push qword [rax + 0x18] ; save EFLAGS in new location
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| 379 | mov rax, [rax] ; restore rax
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| 380 | popfq ; restore EFLAGS
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| 381 | retfq
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| 382 | DoIret:
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| 383 | iretq
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| 384 |
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| 385 | ;-------------------------------------------------------------------------------------
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| 386 | ; GetTemplateAddressMap (&AddressMap);
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| 387 | ;-------------------------------------------------------------------------------------
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| 388 | ; comments here for definition of address map
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| 389 | global ASM_PFX(AsmGetTemplateAddressMap)
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| 390 | ASM_PFX(AsmGetTemplateAddressMap):
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| 391 | lea rax, [AsmIdtVectorBegin]
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| 392 | mov qword [rcx], rax
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| 393 | mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
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| 394 | lea rax, [HookAfterStubHeaderBegin]
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| 395 | mov qword [rcx + 0x10], rax
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| 396 | ret
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| 397 |
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| 398 | ;-------------------------------------------------------------------------------------
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| 399 | ; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
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| 400 | ;-------------------------------------------------------------------------------------
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| 401 | global ASM_PFX(AsmVectorNumFixup)
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| 402 | ASM_PFX(AsmVectorNumFixup):
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| 403 | mov rax, rdx
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| 404 | mov [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al
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| 405 | ret
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| 406 |
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