UefiCpuPkg.dec@ 101291

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EFI/FirmwareNew: Make edk2-stable202308 build on all supported platforms (using gcc at least, msvc not tested yet), bugref:4643
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1	## @file UefiCpuPkg.dec
2	# This Package provides UEFI compatible CPU modules and libraries.
3	#
4	# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR>
5	# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
6	#
7	# SPDX-License-Identifier: BSD-2-Clause-Patent
8	#
9	##
10
11	[Defines]
12	DEC_SPECIFICATION = 0x00010005
13	PACKAGE_NAME = UefiCpuPkg
14	PACKAGE_UNI_FILE = UefiCpuPkg.uni
15	PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
16	PACKAGE_VERSION = 0.90
17
18	[Includes]
19	Include
20
21	[LibraryClasses]
22	## @libraryclass Defines some routines that are used to register/manage/program
23	## CPU features.
24	##
25	RegisterCpuFeaturesLib\|Include/Library/RegisterCpuFeaturesLib.h
26
27	[LibraryClasses.IA32, LibraryClasses.X64]
28	## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
29	##
30	MtrrLib\|Include/Library/MtrrLib.h
31
32	## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
33	##
34	LocalApicLib\|Include/Library/LocalApicLib.h
35
36	## @libraryclass Provides platform specific initialization functions in the SEC phase.
37	##
38	PlatformSecLib\|Include/Library/PlatformSecLib.h
39
40	## @libraryclass Public include file for the SMM CPU Platform Hook Library.
41	##
42	SmmCpuPlatformHookLib\|Include/Library/SmmCpuPlatformHookLib.h
43
44	## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.
45	##
46	SmmCpuFeaturesLib\|Include/Library/SmmCpuFeaturesLib.h
47
48	## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
49	##
50	MpInitLib\|Include/Library/MpInitLib.h
51
52	## @libraryclass Provides function to support CcExit processing.
53	CcExitLib\|Include/Library/CcExitLib.h
54
55	## @libraryclass Provides function to get CPU cache information.
56	CpuCacheInfoLib\|Include/Library/CpuCacheInfoLib.h
57
58	## @libraryclass Provides function for loading microcode.
59	MicrocodeLib\|Include/Library/MicrocodeLib.h
60
61	## @libraryclass Provides function for manipulating x86 paging structures.
62	CpuPageTableLib\|Include/Library/CpuPageTableLib.h
63
64	## @libraryclass Provides functions for manipulating smram savestate registers.
65	MmSaveStateLib\|Include/Library/MmSaveStateLib.h
66
67	[LibraryClasses.RISCV64]
68	## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs.
69	##
70	RiscVMmuLib\|Include/Library/BaseRiscVMmuLib.h
71
72	[Guids]
73	gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
74	gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
75
76	## Include/Guid/CpuFeaturesSetDone.h
77	gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
78
79	## Include/Guid/CpuFeaturesInitDone.h
80	gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
81
82	## Include/Guid/MicrocodePatchHob.h
83	gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
84
85	## Include/Guid/SmmBaseHob.h
86	gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }}
87
88	[Protocols]
89	## Include/Protocol/SmmCpuService.h
90	gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
91	gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
92
93	## Include/Protocol/SmMonitorInit.h
94	gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
95
96	[Protocols.RISCV64]
97	#
98	# Protocols defined for RISC-V systems
99	#
100	## Include/Protocol/RiscVBootProtocol.h
101	gRiscVEfiBootProtocolGuid = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
102
103	#
104	# [Error.gUefiCpuPkgTokenSpaceGuid]
105	# 0x80000001 \| Invalid value provided.
106	#
107
108	[Ppis]
109	gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
110
111	## Include/Ppi/ShadowMicrocode.h
112	gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
113
114	## Include/Ppi/RepublishSecPpi.h
115	gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}
116
117	[PcdsFeatureFlag]
118	## Indicates if SMM Profile will be enabled.
119	# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
120	# In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
121	# In IA32 build, the page table memory is not marked as read-only when it is enabled.
122	# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
123	# TRUE - SMM Profile will be enabled.<BR>
124	# FALSE - SMM Profile will be disabled.<BR>
125	# @Prompt Enable SMM Profile.
126	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable\|FALSE\|BOOLEAN\|0x32132109
127
128	## Indicates if the SMM profile log buffer is a ring buffer.
129	# If disabled, no additional log can be done when the buffer is full.<BR><BR>
130	# TRUE - the SMM profile log buffer is a ring buffer.<BR>
131	# FALSE - the SMM profile log buffer is a normal buffer.<BR>
132	# @Prompt The SMM profile log buffer is a ring buffer.
133	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer\|FALSE\|BOOLEAN\|0x3213210a
134
135	## Indicates if SMM Startup AP in a blocking fashion.
136	# TRUE - SMM Startup AP in a blocking fashion.<BR>
137	# FALSE - SMM Startup AP in a non-blocking fashion.<BR>
138	# @Prompt SMM Startup AP in a blocking fashion.
139	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp\|FALSE\|BOOLEAN\|0x32132108
140
141	## Indicates if SMM Stack Guard will be enabled.
142	# If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
143	# TRUE - SMM Stack Guard will be enabled.<BR>
144	# FALSE - SMM Stack Guard will be disabled.<BR>
145	# @Prompt Enable SMM Stack Guard.
146	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard\|TRUE\|BOOLEAN\|0x1000001C
147
148	## Indicates if BSP election in SMM will be enabled.
149	# If enabled, a BSP will be dynamically elected among all processors in each SMI.
150	# Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
151	# TRUE - BSP election in SMM will be enabled.<BR>
152	# FALSE - BSP election in SMM will be disabled.<BR>
153	# @Prompt Enable BSP election in SMM.
154	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection\|TRUE\|BOOLEAN\|0x32132106
155
156	## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
157	# TRUE - SMM CPU hot-plug will be enabled.<BR>
158	# FALSE - SMM CPU hot-plug will be disabled.<BR>
159	# @Prompt SMM CPU hot-plug.
160	gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport\|FALSE\|BOOLEAN\|0x3213210C
161
162	## Indicates if SMM Debug will be enabled.
163	# If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
164	# TRUE - SMM Debug will be enabled.<BR>
165	# FALSE - SMM Debug will be disabled.<BR>
166	# @Prompt Enable SMM Debug.
167	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug\|FALSE\|BOOLEAN\|0x1000001B
168
169	## Indicates if lock SMM Feature Control MSR.<BR><BR>
170	# TRUE - SMM Feature Control MSR will be locked.<BR>
171	# FALSE - SMM Feature Control MSR will not be locked.<BR>
172	# @Prompt Lock SMM Feature Control MSR.
173	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock\|TRUE\|BOOLEAN\|0x3213210B
174
175	## Indicates if SMRR will be enabled.<BR><BR>
176	# TRUE - SMRR will be enabled.<BR>
177	# FALSE - SMRR will not be enabled.<BR>
178	# @Prompt Enable SMRR.
179	gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable\|TRUE\|BOOLEAN\|0x3213210D
180
181	## Indicates if SmmFeatureControl will be enabled.<BR><BR>
182	# TRUE - SmmFeatureControl will be enabled.<BR>
183	# FALSE - SmmFeatureControl will not be enabled.<BR>
184	# @Prompt Support SmmFeatureControl.
185	gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable\|TRUE\|BOOLEAN\|0x32132110
186
187	## Indicates if SMM perf logging in APs will be enabled.<BR><BR>
188	# TRUE - SMM perf logging in APs will be enabled.<BR>
189	# FALSE - SMM perf logging in APs will not be enabled.<BR>
190	# @Prompt Enable SMM perf logging in APs.
191	gUefiCpuPkgTokenSpaceGuid.PcdSmmApPerfLogEnable\|TRUE\|BOOLEAN\|0x32132114
192
193	[PcdsFixedAtBuild]
194	## List of exception vectors which need switching stack.
195	# This PCD will only take into effect if PcdCpuStackGuard is enabled.
196	# By default exception #DD(8), #PF(14) are supported.
197	# @Prompt Specify exception vectors which need switching stack.
198	gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList\|{0x08, 0x0E}\|VOID*\|0x30002000
199
200	## Size of good stack for an exception.
201	# This PCD will only take into effect if PcdCpuStackGuard is enabled.
202	# @Prompt Specify size of good stack of exception which need switching stack.
203	gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize\|2048\|UINT32\|0x30002001
204
205	## Count of pre allocated SMM MP tokens per chunk.
206	# @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
207	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk\|64\|UINT32\|0x30002002
208
209	## Area of memory where the SEV-ES work area block lives.
210	# @Prompt Configure the SEV-ES work area base
211	gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase\|0x0\|UINT32\|0x30002005
212
213	## Size of teh area of memory where the SEV-ES work area block lives.
214	# @Prompt Configure the SEV-ES work area base
215	gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize\|0x0\|UINT32\|0x30002006
216
217	## Determining APs' first-time wakeup by SIPI or INIT-SIPI-SIPI.
218	# Following a power-up or RESET of an MP system, The APs complete a
219	# minimal self-configuration, then wait for a startup signal (a SIPI
220	# message) from the BSP processor.
221	#
222	# TRUE - Broadcast SIPI.
223	# FALSE - Broadcast INIT-SIPI-SIPI.
224	#
225	# @Prompt BSP Broadcast Method for the first-time wakeup of APs
226	gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi\|TRUE\|BOOLEAN\|0x30002007
227
228	[PcdsFixedAtBuild, PcdsPatchableInModule]
229	## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
230	# @Prompt Configure base address of CPU Local APIC
231	# @Expression 0x80000001 \| (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
232	gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\|0xfee00000\|UINT32\|0x00000001
233
234	## Specifies delay value in microseconds after sending out an INIT IPI.
235	# @Prompt Configure delay value after send an INIT IPI
236	gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds\|10000\|UINT32\|0x30000002
237
238	## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
239	## aligns the address on a 4-KByte boundary.
240	# @Prompt Configure stack size for Application Processor (AP)
241	gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize\|0x8000\|UINT32\|0x00000003
242
243	## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
244	# @Prompt Stack size in the temporary RAM.
245	gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize\|0\|UINT32\|0x10001003
246
247	## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
248	# @Prompt SMM profile data buffer size.
249	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize\|0x200000\|UINT32\|0x32132107
250
251	## Specifies stack size in bytes for each processor in SMM.
252	# @Prompt Processor stack size in SMM.
253	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize\|0x2000\|UINT32\|0x32132105
254
255	## Specifies shadow stack size in bytes for each processor in SMM.
256	# @Prompt Processor shadow stack size in SMM.
257	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize\|0x2000\|UINT32\|0x3213210E
258
259	## Indicates if SMM Code Access Check is enabled.
260	# If enabled, the SMM handler cannot execute the code outside SMM regions.
261	# This PCD is suggested to TRUE in production image.<BR><BR>
262	# TRUE - SMM Code Access Check will be enabled.<BR>
263	# FALSE - SMM Code Access Check will be disabled.<BR>
264	# @Prompt SMM Code Access Check.
265	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable\|TRUE\|BOOLEAN\|0x60000013
266
267	## Specifies the number of variable MTRRs reserved for OS use. The default number of
268	# MTRRs reserved for OS use is 2.
269	# @Prompt Number of reserved variable MTRRs.
270	gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs\|0x2\|UINT32\|0x00000015
271
272	## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
273	# @Prompt STM exception stack size.
274	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize\|0x1000\|UINT32\|0x32132111
275
276	## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
277	# @Prompt MSEG size.
278	gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize\|0x200000\|UINT32\|0x32132112
279
280	## Specifies the supported CPU features bit in array.
281	# @Prompt Supported CPU features.
282	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport\|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}\|VOID*\|0x00000016
283
284	## Specifies if CPU features will be initialized after SMM relocation.
285	# @Prompt If CPU features will be initialized after SMM relocation.
286	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation\|FALSE\|BOOLEAN\|0x0000001C
287
288	## Specifies if CPU features will be initialized during S3 resume.
289	# @Prompt If CPU features will be initialized during S3 resume.
290	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume\|FALSE\|BOOLEAN\|0x0000001D
291
292	## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
293	# TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
294	# Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
295	# 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
296	# Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
297	# @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
298	gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency\|24000000\|UINT64\|0x32132113
299
300	## Specifies the periodic interval value in microseconds for the status check
301	# of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
302	# mode in DXE phase.
303	# @Prompt Periodic interval value in microseconds for AP status check in DXE.
304	gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds\|100000\|UINT32\|0x0000001E
305
306	[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
307	## Specifies max supported number of Logical Processors.
308	# @Prompt Configure max supported number of Logical Processors
309	gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber\|64\|UINT32\|0x00000002
310	## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
311	# @Prompt Timeout for the BSP to detect all APs for the first time.
312	gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds\|50000\|UINT32\|0x00000004
313	## Specifies the number of Logical Processors that are available in the
314	# preboot environment after platform reset, including BSP and APs. Possible
315	# values:<BR><BR>
316	# zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
317	# PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
318	# detection by the BSP.<BR>
319	# nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
320	# AP detection finishes only when the detected CPU count
321	# (BSP plus APs) reaches the value of
322	# PcdCpuBootLogicalProcessorNumber, regardless of how long
323	# that takes.<BR>
324	# @Prompt Number of Logical Processors available after platform reset.
325	gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber\|0\|UINT32\|0x00000008
326	## Specifies the base address of the first microcode Patch in the microcode Region.
327	# @Prompt Microcode Region base address.
328	gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress\|0x0\|UINT64\|0x00000005
329	## Specifies the size of the microcode Region.
330	# @Prompt Microcode Region size.
331	gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize\|0x0\|UINT64\|0x00000006
332	## Specifies the AP wait loop state during POST phase.
333	# The value is defined as below.<BR><BR>
334	# 1: Place AP in the Hlt-Loop state.<BR>
335	# 2: Place AP in the Mwait-Loop state.<BR>
336	# 3: Place AP in the Run-Loop state.<BR>
337	# @Prompt The AP wait loop state.
338	# @ValidRange 0x80000001 \| 1 - 3
339	gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode\|1\|UINT8\|0x60008006
340	## Specifies the AP target C-state for Mwait during POST phase.
341	# The default value 0 means C1 state.
342	# The value is defined as below.<BR><BR>
343	# @Prompt The specified AP target C-state for Mwait.
344	gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate\|0\|UINT8\|0x00000007
345
346	## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
347	# @Prompt AP synchronization timeout value in SMM.
348	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout\|1000000\|UINT64\|0x32132104
349
350	## Indicates the CPU synchronization method used when processing an SMI.
351	# 0x00 - Traditional CPU synchronization method.<BR>
352	# 0x01 - Relaxed CPU synchronization method.<BR>
353	# @Prompt SMM CPU Synchronization Method.
354	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode\|0x00\|UINT8\|0x60000014
355
356	## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
357	# @Prompt The encoded values for target duty cycle modulation.
358	# @ValidRange 0x80000001 \| 0 - 15
359	gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle\|0x0\|UINT8\|0x0000001A
360
361	## Indicates if the current boot is a power-on reset.<BR><BR>
362	# TRUE - Current boot is a power-on reset.<BR>
363	# FALSE - Current boot is not a power-on reset.<BR>
364	# @Prompt Current boot is a power-on reset.
365	gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset\|FALSE\|BOOLEAN\|0x0000001B
366
367	## This PCD indicates whether CPU processor trace is enabled on BSP only when CPU processor trace is enabled.<BR><BR>
368	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
369	# TRUE - CPU processor trace is enabled on BSP only.<BR>
370	# FASLE - CPU processor trace is enabled on all CPU.<BR>
371	# @Prompt Enable CPU processor trace only on BSP.
372	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceBspOnly\|FALSE\|BOOLEAN\|0x60000019
373
374	## This PCD indicates if enable performance collecting when CPU processor trace is enabled.<BR><BR>
375	# CYC/TSC timing packets will be generated to collect performance data if this PCD is TRUE.
376	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
377	# TRUE - Performance collecting will be enabled in processor trace.<BR>
378	# FASLE - Performance collecting will be disabled in processor trace.<BR>
379	# @Prompt Enable performance collecting when processor trace is enabled.
380	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTracePerformanceCollecting\|FALSE\|BOOLEAN\|0x60000020
381
382	[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
383	## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
384	# MMIO access is always allowed regardless of the value of this PCD.
385	# Loose of such restriction is only required by RAS components in X64 platforms.
386	# The PCD value is considered as constantly TRUE in IA32 platforms.
387	# When the PCD value is TRUE, page table is initialized to cover all memory spaces
388	# and the memory occupied by page table is protected by page table itself as read-only.
389	# In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
390	# In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
391	# (PcdHeapGuardPropertyMask in MdeModulePkg).
392	# In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
393	# or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
394	# TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>
395	# FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>
396	# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
397	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess\|TRUE\|BOOLEAN\|0x3213210F
398
399	[PcdsDynamic, PcdsDynamicEx]
400	## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
401	# @Prompt The pointer to a CPU S3 data buffer.
402	# @ValidList 0x80000001 \| 0
403	gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress\|0x0\|UINT64\|0x60000010
404
405	## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
406	# @Prompt The pointer to CPU Hot Plug Data.
407	# @ValidList 0x80000001 \| 0
408	gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress\|0x0\|UINT64\|0x60000011
409
410	## Indicates processor feature capabilities, each bit corresponding to a specific feature.
411	# @Prompt Processor feature capabilities.
412	# @ValidList 0x80000001 \| 0
413	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability\|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\|VOID*\|0x00000018
414
415	## As input, specifies user's desired settings for enabling/disabling processor features.
416	## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
417	# @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
418	# @ValidList 0x80000001 \| 0
419	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting\|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\|VOID*\|0x00000019
420
421	## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
422	# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
423	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
424	# Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
425	# 0x0 - 4K.<BR>
426	# 0x1 - 8K.<BR>
427	# 0x2 - 16K.<BR>
428	# 0x3 - 32K.<BR>
429	# 0x4 - 64K.<BR>
430	# 0x5 - 128K.<BR>
431	# 0x6 - 256K.<BR>
432	# 0x7 - 512K.<BR>
433	# 0x8 - 1M.<BR>
434	# 0x9 - 2M.<BR>
435	# 0xA - 4M.<BR>
436	# 0xB - 8M.<BR>
437	# 0xC - 16M.<BR>
438	# 0xD - 32M.<BR>
439	# 0xE - 64M.<BR>
440	# 0xF - 128M.<BR>
441	# @Prompt The memory size used for processor trace if processor trace is enabled.
442	# @ValidRange 0x80000001 \| 0 - 0xF
443	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize\|0x0\|UINT32\|0x60000012
444
445	## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
446	# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
447	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
448	# Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
449	# 0 - Single Range output scheme.<BR>
450	# 1 - ToPA(Table of physical address) scheme.<BR>
451	# @Prompt The processor trace output scheme used when processor trace is enabled.
452	# @ValidRange 0x80000001 \| 0 - 1
453	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme\|0x0\|UINT8\|0x60000015
454
455	## This dynamic PCD indicates whether SEV-ES is enabled
456	# TRUE - SEV-ES is enabled
457	# FALSE - SEV-ES is not enabled
458	# @Prompt SEV-ES Status
459	gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled\|FALSE\|BOOLEAN\|0x60000016
460
461	## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR
462	# features VMGEXIT defined in the version 2 of GHCB spec.
463	# @Prompt GHCB Hypervisor Features
464	gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures\|0x0\|UINT64\|0x60000018
465
466	[UserExtensions.TianoCore."ExtraFiles"]
467	UefiCpuPkgExtra.uni

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