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source: vbox/trunk/src/VBox/Devices/Graphics/vmsvga/svga3d_reg.h@ 69665

最後變更 在這個檔案從69665是 69665,由 vboxsync 提交於 7 年 前

Devices/Graphics: VMSVGA D3D backend: added SVGA3D_R8G8B8A8_UNORM, comment, fix for instancing cleanup.
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1/**********************************************************
2 * Copyright 1998-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_reg.h --
28 *
29 * SVGA 3D hardware definitions
30 */
31
32#ifndef _SVGA3D_REG_H_
33#define _SVGA3D_REG_H_
34
35#include "svga_reg.h"
36
37
38/*
39 * 3D Hardware Version
40 *
41 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
42 * register. Is set by the host and read by the guest. This lets
43 * us make new guest drivers which are backwards-compatible with old
44 * SVGA hardware revisions. It does not let us support old guest
45 * drivers. Good enough for now.
46 *
47 */
48
49#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
50#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
51#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
52
53typedef enum {
54 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
55 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
56 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
57 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
58 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
59 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
60 SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
61 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1
62} SVGA3dHardwareVersion;
63
64/*
65 * Generic Types
66 */
67
68typedef uint32_t SVGA3dBool; /* 32-bit Bool definition */
69#define SVGA3D_NUM_CLIPPLANES 6
70#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8
71#define SVGA3D_MAX_CONTEXT_IDS 256
72#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
73
74/*
75 * Surface formats.
76 *
77 * If you modify this list, be sure to keep GLUtil.c in sync. It
78 * includes the internal format definition of each surface in
79 * GLUtil_ConvertSurfaceFormat, and it contains a table of
80 * human-readable names in GLUtil_GetFormatName.
81 */
82
83typedef enum SVGA3dSurfaceFormat {
84 SVGA3D_FORMAT_INVALID = 0,
85
86 SVGA3D_X8R8G8B8 = 1,
87 SVGA3D_A8R8G8B8 = 2,
88
89 SVGA3D_R5G6B5 = 3,
90 SVGA3D_X1R5G5B5 = 4,
91 SVGA3D_A1R5G5B5 = 5,
92 SVGA3D_A4R4G4B4 = 6,
93
94 SVGA3D_Z_D32 = 7,
95 SVGA3D_Z_D16 = 8,
96 SVGA3D_Z_D24S8 = 9,
97 SVGA3D_Z_D15S1 = 10,
98
99 SVGA3D_LUMINANCE8 = 11,
100 SVGA3D_LUMINANCE4_ALPHA4 = 12,
101 SVGA3D_LUMINANCE16 = 13,
102 SVGA3D_LUMINANCE8_ALPHA8 = 14,
103
104 SVGA3D_DXT1 = 15,
105 SVGA3D_DXT2 = 16,
106 SVGA3D_DXT3 = 17,
107 SVGA3D_DXT4 = 18,
108 SVGA3D_DXT5 = 19,
109
110 SVGA3D_BUMPU8V8 = 20,
111 SVGA3D_BUMPL6V5U5 = 21,
112 SVGA3D_BUMPX8L8V8U8 = 22,
113 SVGA3D_BUMPL8V8U8 = 23,
114
115 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
116 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
117
118 SVGA3D_A2R10G10B10 = 26,
119
120 /* signed formats */
121 SVGA3D_V8U8 = 27,
122 SVGA3D_Q8W8V8U8 = 28,
123 SVGA3D_CxV8U8 = 29,
124
125 /* mixed formats */
126 SVGA3D_X8L8V8U8 = 30,
127 SVGA3D_A2W10V10U10 = 31,
128
129 SVGA3D_ALPHA8 = 32,
130
131 /* Single- and dual-component floating point formats */
132 SVGA3D_R_S10E5 = 33,
133 SVGA3D_R_S23E8 = 34,
134 SVGA3D_RG_S10E5 = 35,
135 SVGA3D_RG_S23E8 = 36,
136
137 /*
138 * Any surface can be used as a buffer object, but SVGA3D_BUFFER is
139 * the most efficient format to use when creating new surfaces
140 * expressly for index or vertex data.
141 */
142
143 SVGA3D_BUFFER = 37,
144
145 SVGA3D_Z_D24X8 = 38,
146
147 SVGA3D_V16U16 = 39,
148
149 SVGA3D_G16R16 = 40,
150 SVGA3D_A16B16G16R16 = 41,
151
152 /* Packed Video formats */
153 SVGA3D_UYVY = 42,
154 SVGA3D_YUY2 = 43,
155
156 /* Planar video formats */
157 SVGA3D_NV12 = 44,
158
159 /* Video format with alpha */
160 SVGA3D_AYUV = 45,
161
162 SVGA3D_R8G8B8A8_UNORM = 68, /// @todo use headers from newer Mesa
163
164 SVGA3D_BC4_UNORM = 108,
165 SVGA3D_BC5_UNORM = 111,
166
167 /* Advanced D3D9 depth formats. */
168 SVGA3D_Z_DF16 = 118,
169 SVGA3D_Z_DF24 = 119,
170 SVGA3D_Z_D24S8_INT = 120,
171
172 SVGA3D_R8G8B8A8_SNORM = 127, /// @todo use headers from newer Mesa
173 SVGA3D_R16G16_UNORM = 129, /// @todo use headers from newer Mesa
174
175 SVGA3D_FORMAT_MAX
176} SVGA3dSurfaceFormat;
177
178typedef uint32_t SVGA3dColor; /* a, r, g, b */
179
180/*
181 * These match the D3DFORMAT_OP definitions used by Direct3D. We need
182 * them so that we can query the host for what the supported surface
183 * operations are (when we're using the D3D backend, in particular),
184 * and so we can send those operations to the guest.
185 */
186typedef enum {
187 SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
188 SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
189 SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
190 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
191 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
192 SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
193 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
194
195/*
196 * This format can be used as a render target if the current display mode
197 * is the same depth if the alpha channel is ignored. e.g. if the device
198 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
199 * format op list entry for A8R8G8B8 should have this cap.
200 */
201 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
202
203/*
204 * This format contains DirectDraw support (including Flip). This flag
205 * should not to be set on alpha formats.
206 */
207 SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
208
209/*
210 * The rasterizer can support some level of Direct3D support in this format
211 * and implies that the driver can create a Context in this mode (for some
212 * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
213 * flag must also be set.
214 */
215 SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
216
217/*
218 * This is set for a private format when the driver has put the bpp in
219 * the structure.
220 */
221 SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
222
223/*
224 * Indicates that this format can be converted to any RGB format for which
225 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
226 */
227 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
228
229/*
230 * Indicates that this format can be used to create offscreen plain surfaces.
231 */
232 SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
233
234/*
235 * Indicated that this format can be read as an SRGB texture (meaning that the
236 * sampler will linearize the looked up data)
237 */
238 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
239
240/*
241 * Indicates that this format can be used in the bumpmap instructions
242 */
243 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
244
245/*
246 * Indicates that this format can be sampled by the displacement map sampler
247 */
248 SVGA3DFORMAT_OP_DMAP = 0x00020000,
249
250/*
251 * Indicates that this format cannot be used with texture filtering
252 */
253 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
254
255/*
256 * Indicates that format conversions are supported to this RGB format if
257 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
258 */
259 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
260
261/*
262 * Indicated that this format can be written as an SRGB target (meaning that the
263 * pixel pipe will DE-linearize data on output to format)
264 */
265 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
266
267/*
268 * Indicates that this format cannot be used with alpha blending
269 */
270 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
271
272/*
273 * Indicates that the device can auto-generated sublevels for resources
274 * of this format
275 */
276 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
277
278/*
279 * Indicates that this format can be used by vertex texture sampler
280 */
281 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
282
283/*
284 * Indicates that this format supports neither texture coordinate wrap
285 * modes, nor mipmapping
286 */
287 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
288} SVGA3dFormatOp;
289
290/*
291 * This structure is a conversion of SVGA3DFORMAT_OP_*.
292 * Entries must be located at the same position.
293 */
294typedef union {
295 uint32_t value;
296 struct {
297 uint32_t texture : 1;
298 uint32_t volumeTexture : 1;
299 uint32_t cubeTexture : 1;
300 uint32_t offscreenRenderTarget : 1;
301 uint32_t sameFormatRenderTarget : 1;
302 uint32_t unknown1 : 1;
303 uint32_t zStencil : 1;
304 uint32_t zStencilArbitraryDepth : 1;
305 uint32_t sameFormatUpToAlpha : 1;
306 uint32_t unknown2 : 1;
307 uint32_t displayMode : 1;
308 uint32_t acceleration3d : 1;
309 uint32_t pixelSize : 1;
310 uint32_t convertToARGB : 1;
311 uint32_t offscreenPlain : 1;
312 uint32_t sRGBRead : 1;
313 uint32_t bumpMap : 1;
314 uint32_t dmap : 1;
315 uint32_t noFilter : 1;
316 uint32_t memberOfGroupARGB : 1;
317 uint32_t sRGBWrite : 1;
318 uint32_t noAlphaBlend : 1;
319 uint32_t autoGenMipMap : 1;
320 uint32_t vertexTexture : 1;
321 uint32_t noTexCoordWrapNorMip : 1;
322 } s;
323} SVGA3dSurfaceFormatCaps;
324
325/*
326 * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
327 * must fit in a uint32_t.
328 */
329
330typedef enum {
331 SVGA3D_RS_INVALID = 0,
332 SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
333 SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
334 SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
335 SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
336 SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
337 SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
338 SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
339 SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
340 SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
341 SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
342 SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
343 SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
344 SVGA3D_RS_STENCILREF = 13, /* uint32_t */
345 SVGA3D_RS_STENCILMASK = 14, /* uint32_t */
346 SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32_t */
347 SVGA3D_RS_FOGSTART = 16, /* float */
348 SVGA3D_RS_FOGEND = 17, /* float */
349 SVGA3D_RS_FOGDENSITY = 18, /* float */
350 SVGA3D_RS_POINTSIZE = 19, /* float */
351 SVGA3D_RS_POINTSIZEMIN = 20, /* float */
352 SVGA3D_RS_POINTSIZEMAX = 21, /* float */
353 SVGA3D_RS_POINTSCALE_A = 22, /* float */
354 SVGA3D_RS_POINTSCALE_B = 23, /* float */
355 SVGA3D_RS_POINTSCALE_C = 24, /* float */
356 SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
357 SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
358 SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
359 SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
360 SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
361 SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
362 SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
363 SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
364 SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
365 SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
366 SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
367 SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
368 SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
369 SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
370 SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
371 SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
372 SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
373 SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
374 SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
375 SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
376 SVGA3D_RS_ZBIAS = 45, /* float */
377 SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
378 SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
379 SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
380 SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
381 SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
382 SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
383 SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
384 SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
385 SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
386 SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
387 SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
388 SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
389 SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
390 SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
391 SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
392 SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
393 SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
394 SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
395 SVGA3D_RS_DEPTHBIAS = 64, /* float */
396
397
398 /*
399 * Output Gamma Level
400 *
401 * Output gamma effects the gamma curve of colors that are output from the
402 * rendering pipeline. A value of 1.0 specifies a linear color space. If the
403 * value is <= 0.0, gamma correction is ignored and linear color space is
404 * used.
405 */
406
407 SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
408 SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
409 SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
410 SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
411 SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
412 SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
413 SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
414 SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
415 SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
416 SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
417 SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
418 SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
419 SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
420 SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
421 SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
422 SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
423 SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
424 SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
425 SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
426 SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
427 SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
428 SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32_t */
429 SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
430 SVGA3D_RS_TWEENFACTOR = 88, /* float */
431 SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
432 SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
433 SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
434 SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
435 SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
436 SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
437 SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
438 SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
439 SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
440 SVGA3D_RS_LINEAA = 98, /* SVGA3dBool */
441 SVGA3D_RS_LINEWIDTH = 99, /* float */
442 SVGA3D_RS_MAX
443} SVGA3dRenderStateName;
444
445typedef enum {
446 SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
447 SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
448 SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
449 SVGA3D_TRANSPARENCYANTIALIAS_MAX
450} SVGA3dTransparencyAntialiasType;
451
452typedef enum {
453 SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
454 SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
455 SVGA3D_VERTEXMATERIAL_SPECULAR = 2 /* Use the value in the specular component */
456} SVGA3dVertexMaterial;
457
458typedef enum {
459 SVGA3D_FILLMODE_INVALID = 0,
460 SVGA3D_FILLMODE_POINT = 1,
461 SVGA3D_FILLMODE_LINE = 2,
462 SVGA3D_FILLMODE_FILL = 3,
463 SVGA3D_FILLMODE_MAX
464} SVGA3dFillModeType;
465
466
467typedef
468union {
469 struct {
470 uint16_t mode; /* SVGA3dFillModeType */
471 uint16_t face; /* SVGA3dFace */
472 } s;
473 uint32_t uintValue;
474} SVGA3dFillMode;
475
476typedef enum {
477 SVGA3D_SHADEMODE_INVALID = 0,
478 SVGA3D_SHADEMODE_FLAT = 1,
479 SVGA3D_SHADEMODE_SMOOTH = 2,
480 SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
481 SVGA3D_SHADEMODE_MAX
482} SVGA3dShadeMode;
483
484typedef
485union {
486 struct {
487 uint16_t repeat;
488 uint16_t pattern;
489 } s;
490 uint32_t uintValue;
491} SVGA3dLinePattern;
492
493typedef enum {
494 SVGA3D_BLENDOP_INVALID = 0,
495 SVGA3D_BLENDOP_ZERO = 1,
496 SVGA3D_BLENDOP_ONE = 2,
497 SVGA3D_BLENDOP_SRCCOLOR = 3,
498 SVGA3D_BLENDOP_INVSRCCOLOR = 4,
499 SVGA3D_BLENDOP_SRCALPHA = 5,
500 SVGA3D_BLENDOP_INVSRCALPHA = 6,
501 SVGA3D_BLENDOP_DESTALPHA = 7,
502 SVGA3D_BLENDOP_INVDESTALPHA = 8,
503 SVGA3D_BLENDOP_DESTCOLOR = 9,
504 SVGA3D_BLENDOP_INVDESTCOLOR = 10,
505 SVGA3D_BLENDOP_SRCALPHASAT = 11,
506 SVGA3D_BLENDOP_BLENDFACTOR = 12,
507 SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
508 SVGA3D_BLENDOP_MAX
509} SVGA3dBlendOp;
510
511typedef enum {
512 SVGA3D_BLENDEQ_INVALID = 0,
513 SVGA3D_BLENDEQ_ADD = 1,
514 SVGA3D_BLENDEQ_SUBTRACT = 2,
515 SVGA3D_BLENDEQ_REVSUBTRACT = 3,
516 SVGA3D_BLENDEQ_MINIMUM = 4,
517 SVGA3D_BLENDEQ_MAXIMUM = 5,
518 SVGA3D_BLENDEQ_MAX
519} SVGA3dBlendEquation;
520
521typedef enum {
522 SVGA3D_FRONTWINDING_INVALID = 0,
523 SVGA3D_FRONTWINDING_CW = 1,
524 SVGA3D_FRONTWINDING_CCW = 2,
525 SVGA3D_FRONTWINDING_MAX
526} SVGA3dFrontWinding;
527
528typedef enum {
529 SVGA3D_FACE_INVALID = 0,
530 SVGA3D_FACE_NONE = 1,
531 SVGA3D_FACE_FRONT = 2,
532 SVGA3D_FACE_BACK = 3,
533 SVGA3D_FACE_FRONT_BACK = 4,
534 SVGA3D_FACE_MAX
535} SVGA3dFace;
536
537/*
538 * The order and the values should not be changed
539 */
540
541typedef enum {
542 SVGA3D_CMP_INVALID = 0,
543 SVGA3D_CMP_NEVER = 1,
544 SVGA3D_CMP_LESS = 2,
545 SVGA3D_CMP_EQUAL = 3,
546 SVGA3D_CMP_LESSEQUAL = 4,
547 SVGA3D_CMP_GREATER = 5,
548 SVGA3D_CMP_NOTEQUAL = 6,
549 SVGA3D_CMP_GREATEREQUAL = 7,
550 SVGA3D_CMP_ALWAYS = 8,
551 SVGA3D_CMP_MAX
552} SVGA3dCmpFunc;
553
554/*
555 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
556 * the fog factor to be specified in the alpha component of the specular
557 * (a.k.a. secondary) vertex color.
558 */
559typedef enum {
560 SVGA3D_FOGFUNC_INVALID = 0,
561 SVGA3D_FOGFUNC_EXP = 1,
562 SVGA3D_FOGFUNC_EXP2 = 2,
563 SVGA3D_FOGFUNC_LINEAR = 3,
564 SVGA3D_FOGFUNC_PER_VERTEX = 4
565} SVGA3dFogFunction;
566
567/*
568 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
569 * or per-pixel basis.
570 */
571typedef enum {
572 SVGA3D_FOGTYPE_INVALID = 0,
573 SVGA3D_FOGTYPE_VERTEX = 1,
574 SVGA3D_FOGTYPE_PIXEL = 2,
575 SVGA3D_FOGTYPE_MAX = 3
576} SVGA3dFogType;
577
578/*
579 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
580 * computed using the eye Z value of each pixel (or vertex), whereas range-
581 * based fog is computed using the actual distance (range) to the eye.
582 */
583typedef enum {
584 SVGA3D_FOGBASE_INVALID = 0,
585 SVGA3D_FOGBASE_DEPTHBASED = 1,
586 SVGA3D_FOGBASE_RANGEBASED = 2,
587 SVGA3D_FOGBASE_MAX = 3
588} SVGA3dFogBase;
589
590typedef enum {
591 SVGA3D_STENCILOP_INVALID = 0,
592 SVGA3D_STENCILOP_KEEP = 1,
593 SVGA3D_STENCILOP_ZERO = 2,
594 SVGA3D_STENCILOP_REPLACE = 3,
595 SVGA3D_STENCILOP_INCRSAT = 4,
596 SVGA3D_STENCILOP_DECRSAT = 5,
597 SVGA3D_STENCILOP_INVERT = 6,
598 SVGA3D_STENCILOP_INCR = 7,
599 SVGA3D_STENCILOP_DECR = 8,
600 SVGA3D_STENCILOP_MAX
601} SVGA3dStencilOp;
602
603typedef enum {
604 SVGA3D_CLIPPLANE_0 = (1 << 0),
605 SVGA3D_CLIPPLANE_1 = (1 << 1),
606 SVGA3D_CLIPPLANE_2 = (1 << 2),
607 SVGA3D_CLIPPLANE_3 = (1 << 3),
608 SVGA3D_CLIPPLANE_4 = (1 << 4),
609 SVGA3D_CLIPPLANE_5 = (1 << 5),
610 SVGA3D_CLIPPLANE_MAX = SVGA3D_CLIPPLANE_5
611} SVGA3dClipPlanes;
612
613typedef enum {
614 SVGA3D_CLEAR_COLOR = 0x1,
615 SVGA3D_CLEAR_DEPTH = 0x2,
616 SVGA3D_CLEAR_STENCIL = 0x4
617} SVGA3dClearFlag;
618
619typedef enum {
620 SVGA3D_RT_DEPTH = 0,
621 SVGA3D_RT_STENCIL = 1,
622 SVGA3D_RT_COLOR0 = 2,
623 SVGA3D_RT_COLOR1 = 3,
624 SVGA3D_RT_COLOR2 = 4,
625 SVGA3D_RT_COLOR3 = 5,
626 SVGA3D_RT_COLOR4 = 6,
627 SVGA3D_RT_COLOR5 = 7,
628 SVGA3D_RT_COLOR6 = 8,
629 SVGA3D_RT_COLOR7 = 9,
630 SVGA3D_RT_MAX,
631 SVGA3D_RT_INVALID = ((uint32_t)-1)
632} SVGA3dRenderTargetType;
633
634#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
635
636typedef
637union {
638 struct {
639 uint32_t red : 1;
640 uint32_t green : 1;
641 uint32_t blue : 1;
642 uint32_t alpha : 1;
643 } s;
644 uint32_t uintValue;
645} SVGA3dColorMask;
646
647typedef enum {
648 SVGA3D_VBLEND_DISABLE = 0,
649 SVGA3D_VBLEND_1WEIGHT = 1,
650 SVGA3D_VBLEND_2WEIGHT = 2,
651 SVGA3D_VBLEND_3WEIGHT = 3
652} SVGA3dVertexBlendFlags;
653
654typedef enum {
655 SVGA3D_WRAPCOORD_0 = 1 << 0,
656 SVGA3D_WRAPCOORD_1 = 1 << 1,
657 SVGA3D_WRAPCOORD_2 = 1 << 2,
658 SVGA3D_WRAPCOORD_3 = 1 << 3,
659 SVGA3D_WRAPCOORD_ALL = 0xF
660} SVGA3dWrapFlags;
661
662/*
663 * SVGA_3D_CMD_TEXTURESTATE Types. All value types
664 * must fit in a uint32_t.
665 */
666
667typedef enum {
668 SVGA3D_TS_INVALID = 0,
669 SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
670 SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
671 SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
672 SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
673 SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
674 SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
675 SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
676 SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
677 SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
678 SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
679 SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
680 SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
681 SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
682 SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32_t */
683 SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
684 SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
685 SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
686 SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
687 SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
688 SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
689 SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32_t */
690 SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
691 SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32_t */
692 SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
693
694
695 /*
696 * Sampler Gamma Level
697 *
698 * Sampler gamma effects the color of samples taken from the sampler. A
699 * value of 1.0 will produce linear samples. If the value is <= 0.0 the
700 * gamma value is ignored and a linear space is used.
701 */
702
703 SVGA3D_TS_GAMMA = 25, /* float */
704 SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
705 SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
706 SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
707 SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
708 SVGA3D_TS_MAX
709} SVGA3dTextureStateName;
710
711typedef enum {
712 SVGA3D_TC_INVALID = 0,
713 SVGA3D_TC_DISABLE = 1,
714 SVGA3D_TC_SELECTARG1 = 2,
715 SVGA3D_TC_SELECTARG2 = 3,
716 SVGA3D_TC_MODULATE = 4,
717 SVGA3D_TC_ADD = 5,
718 SVGA3D_TC_ADDSIGNED = 6,
719 SVGA3D_TC_SUBTRACT = 7,
720 SVGA3D_TC_BLENDTEXTUREALPHA = 8,
721 SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
722 SVGA3D_TC_BLENDCURRENTALPHA = 10,
723 SVGA3D_TC_BLENDFACTORALPHA = 11,
724 SVGA3D_TC_MODULATE2X = 12,
725 SVGA3D_TC_MODULATE4X = 13,
726 SVGA3D_TC_DSDT = 14,
727 SVGA3D_TC_DOTPRODUCT3 = 15,
728 SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
729 SVGA3D_TC_ADDSIGNED2X = 17,
730 SVGA3D_TC_ADDSMOOTH = 18,
731 SVGA3D_TC_PREMODULATE = 19,
732 SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
733 SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
734 SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
735 SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
736 SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
737 SVGA3D_TC_MULTIPLYADD = 25,
738 SVGA3D_TC_LERP = 26,
739 SVGA3D_TC_MAX
740} SVGA3dTextureCombiner;
741
742#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
743
744typedef enum {
745 SVGA3D_TEX_ADDRESS_INVALID = 0,
746 SVGA3D_TEX_ADDRESS_WRAP = 1,
747 SVGA3D_TEX_ADDRESS_MIRROR = 2,
748 SVGA3D_TEX_ADDRESS_CLAMP = 3,
749 SVGA3D_TEX_ADDRESS_BORDER = 4,
750 SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
751 SVGA3D_TEX_ADDRESS_EDGE = 6,
752 SVGA3D_TEX_ADDRESS_MAX
753} SVGA3dTextureAddress;
754
755/*
756 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
757 * disabled, and the rasterizer should use the magnification filter instead.
758 */
759typedef enum {
760 SVGA3D_TEX_FILTER_NONE = 0,
761 SVGA3D_TEX_FILTER_NEAREST = 1,
762 SVGA3D_TEX_FILTER_LINEAR = 2,
763 SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
764 SVGA3D_TEX_FILTER_FLATCUBIC = 4, // Deprecated, not implemented
765 SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, // Deprecated, not implemented
766 SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, // Not currently implemented
767 SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, // Not currently implemented
768 SVGA3D_TEX_FILTER_MAX
769} SVGA3dTextureFilter;
770
771typedef enum {
772 SVGA3D_TEX_TRANSFORM_OFF = 0,
773 SVGA3D_TEX_TRANSFORM_S = (1 << 0),
774 SVGA3D_TEX_TRANSFORM_T = (1 << 1),
775 SVGA3D_TEX_TRANSFORM_R = (1 << 2),
776 SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
777 SVGA3D_TEX_PROJECTED = (1 << 15)
778} SVGA3dTexTransformFlags;
779
780typedef enum {
781 SVGA3D_TEXCOORD_GEN_OFF = 0,
782 SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
783 SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
784 SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
785 SVGA3D_TEXCOORD_GEN_SPHERE = 4,
786 SVGA3D_TEXCOORD_GEN_MAX
787} SVGA3dTextureCoordGen;
788
789/*
790 * Texture argument constants for texture combiner
791 */
792typedef enum {
793 SVGA3D_TA_INVALID = 0,
794 SVGA3D_TA_CONSTANT = 1,
795 SVGA3D_TA_PREVIOUS = 2,
796 SVGA3D_TA_DIFFUSE = 3,
797 SVGA3D_TA_TEXTURE = 4,
798 SVGA3D_TA_SPECULAR = 5,
799 SVGA3D_TA_MAX
800} SVGA3dTextureArgData;
801
802#define SVGA3D_TM_MASK_LEN 4
803
804/* Modifiers for texture argument constants defined above. */
805typedef enum {
806 SVGA3D_TM_NONE = 0,
807 SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
808 SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN)
809} SVGA3dTextureArgModifier;
810
811#define SVGA3D_INVALID_ID ((uint32_t)-1)
812#define SVGA3D_MAX_CLIP_PLANES 6
813
814/*
815 * This is the limit to the number of fixed-function texture
816 * transforms and texture coordinates we can support. It does *not*
817 * correspond to the number of texture image units (samplers) we
818 * support!
819 */
820#define SVGA3D_MAX_TEXTURE_COORDS 8
821
822/*
823 * Vertex declarations
824 *
825 * Notes:
826 *
827 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
828 * draw with any POSITIONT vertex arrays, the programmable vertex
829 * pipeline will be implicitly disabled. Drawing will take place as if
830 * no vertex shader was bound.
831 */
832
833typedef enum {
834 SVGA3D_DECLUSAGE_POSITION = 0,
835 SVGA3D_DECLUSAGE_BLENDWEIGHT, // 1
836 SVGA3D_DECLUSAGE_BLENDINDICES, // 2
837 SVGA3D_DECLUSAGE_NORMAL, // 3
838 SVGA3D_DECLUSAGE_PSIZE, // 4
839 SVGA3D_DECLUSAGE_TEXCOORD, // 5
840 SVGA3D_DECLUSAGE_TANGENT, // 6
841 SVGA3D_DECLUSAGE_BINORMAL, // 7
842 SVGA3D_DECLUSAGE_TESSFACTOR, // 8
843 SVGA3D_DECLUSAGE_POSITIONT, // 9
844 SVGA3D_DECLUSAGE_COLOR, // 10
845 SVGA3D_DECLUSAGE_FOG, // 11
846 SVGA3D_DECLUSAGE_DEPTH, // 12
847 SVGA3D_DECLUSAGE_SAMPLE, // 13
848 SVGA3D_DECLUSAGE_MAX
849} SVGA3dDeclUsage;
850
851typedef enum {
852 SVGA3D_DECLMETHOD_DEFAULT = 0,
853 SVGA3D_DECLMETHOD_PARTIALU,
854 SVGA3D_DECLMETHOD_PARTIALV,
855 SVGA3D_DECLMETHOD_CROSSUV, // Normal
856 SVGA3D_DECLMETHOD_UV,
857 SVGA3D_DECLMETHOD_LOOKUP, // Lookup a displacement map
858 SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED // Lookup a pre-sampled displacement map
859} SVGA3dDeclMethod;
860
861typedef enum {
862 SVGA3D_DECLTYPE_FLOAT1 = 0,
863 SVGA3D_DECLTYPE_FLOAT2 = 1,
864 SVGA3D_DECLTYPE_FLOAT3 = 2,
865 SVGA3D_DECLTYPE_FLOAT4 = 3,
866 SVGA3D_DECLTYPE_D3DCOLOR = 4,
867 SVGA3D_DECLTYPE_UBYTE4 = 5,
868 SVGA3D_DECLTYPE_SHORT2 = 6,
869 SVGA3D_DECLTYPE_SHORT4 = 7,
870 SVGA3D_DECLTYPE_UBYTE4N = 8,
871 SVGA3D_DECLTYPE_SHORT2N = 9,
872 SVGA3D_DECLTYPE_SHORT4N = 10,
873 SVGA3D_DECLTYPE_USHORT2N = 11,
874 SVGA3D_DECLTYPE_USHORT4N = 12,
875 SVGA3D_DECLTYPE_UDEC3 = 13,
876 SVGA3D_DECLTYPE_DEC3N = 14,
877 SVGA3D_DECLTYPE_FLOAT16_2 = 15,
878 SVGA3D_DECLTYPE_FLOAT16_4 = 16,
879 SVGA3D_DECLTYPE_MAX
880} SVGA3dDeclType;
881
882/*
883 * This structure is used for the divisor for geometry instancing;
884 * it's a direct translation of the Direct3D equivalent.
885 */
886typedef union {
887 struct {
888 /*
889 * For index data, this number represents the number of instances to draw.
890 * For instance data, this number represents the number of
891 * instances/vertex in this stream
892 */
893 uint32_t count : 30;
894
895 /*
896 * This is 1 if this is supposed to be the data that is repeated for
897 * every instance.
898 */
899 uint32_t indexedData : 1;
900
901 /*
902 * This is 1 if this is supposed to be the per-instance data.
903 */
904 uint32_t instanceData : 1;
905 } s;
906
907 uint32_t value;
908} SVGA3dVertexDivisor;
909
910typedef enum {
911 SVGA3D_PRIMITIVE_INVALID = 0,
912 SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
913 SVGA3D_PRIMITIVE_POINTLIST = 2,
914 SVGA3D_PRIMITIVE_LINELIST = 3,
915 SVGA3D_PRIMITIVE_LINESTRIP = 4,
916 SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
917 SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
918 SVGA3D_PRIMITIVE_MAX
919} SVGA3dPrimitiveType;
920
921typedef enum {
922 SVGA3D_COORDINATE_INVALID = 0,
923 SVGA3D_COORDINATE_LEFTHANDED = 1,
924 SVGA3D_COORDINATE_RIGHTHANDED = 2,
925 SVGA3D_COORDINATE_MAX
926} SVGA3dCoordinateType;
927
928typedef enum {
929 SVGA3D_TRANSFORM_INVALID = 0,
930 SVGA3D_TRANSFORM_WORLD = 1,
931 SVGA3D_TRANSFORM_VIEW = 2,
932 SVGA3D_TRANSFORM_PROJECTION = 3,
933 SVGA3D_TRANSFORM_TEXTURE0 = 4,
934 SVGA3D_TRANSFORM_TEXTURE1 = 5,
935 SVGA3D_TRANSFORM_TEXTURE2 = 6,
936 SVGA3D_TRANSFORM_TEXTURE3 = 7,
937 SVGA3D_TRANSFORM_TEXTURE4 = 8,
938 SVGA3D_TRANSFORM_TEXTURE5 = 9,
939 SVGA3D_TRANSFORM_TEXTURE6 = 10,
940 SVGA3D_TRANSFORM_TEXTURE7 = 11,
941 SVGA3D_TRANSFORM_WORLD1 = 12,
942 SVGA3D_TRANSFORM_WORLD2 = 13,
943 SVGA3D_TRANSFORM_WORLD3 = 14,
944 SVGA3D_TRANSFORM_MAX
945} SVGA3dTransformType;
946
947typedef enum {
948 SVGA3D_LIGHTTYPE_INVALID = 0,
949 SVGA3D_LIGHTTYPE_POINT = 1,
950 SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
951 SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
952 SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
953 SVGA3D_LIGHTTYPE_MAX
954} SVGA3dLightType;
955
956typedef enum {
957 SVGA3D_CUBEFACE_POSX = 0,
958 SVGA3D_CUBEFACE_NEGX = 1,
959 SVGA3D_CUBEFACE_POSY = 2,
960 SVGA3D_CUBEFACE_NEGY = 3,
961 SVGA3D_CUBEFACE_POSZ = 4,
962 SVGA3D_CUBEFACE_NEGZ = 5
963} SVGA3dCubeFace;
964
965typedef enum {
966 SVGA3D_SHADERTYPE_VS = 1,
967 SVGA3D_SHADERTYPE_PS = 2,
968 SVGA3D_SHADERTYPE_MAX
969} SVGA3dShaderType;
970
971typedef enum {
972 SVGA3D_CONST_TYPE_FLOAT = 0,
973 SVGA3D_CONST_TYPE_INT = 1,
974 SVGA3D_CONST_TYPE_BOOL = 2
975} SVGA3dShaderConstType;
976
977#define SVGA3D_MAX_SURFACE_FACES 6
978
979typedef enum {
980 SVGA3D_STRETCH_BLT_POINT = 0,
981 SVGA3D_STRETCH_BLT_LINEAR = 1,
982 SVGA3D_STRETCH_BLT_MAX
983} SVGA3dStretchBltMode;
984
985typedef enum {
986 SVGA3D_QUERYTYPE_OCCLUSION = 0,
987 SVGA3D_QUERYTYPE_MAX
988} SVGA3dQueryType;
989
990typedef enum {
991 SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
992 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
993 SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
994 SVGA3D_QUERYSTATE_NEW = 3 /* Never submitted (For guest use only) */
995} SVGA3dQueryState;
996
997typedef enum {
998 SVGA3D_WRITE_HOST_VRAM = 1,
999 SVGA3D_READ_HOST_VRAM = 2
1000} SVGA3dTransferType;
1001
1002/*
1003 * The maximum number of vertex arrays we're guaranteed to support in
1004 * SVGA_3D_CMD_DRAWPRIMITIVES.
1005 */
1006#define SVGA3D_MAX_VERTEX_ARRAYS 32
1007
1008/*
1009 * The maximum number of primitive ranges we're guaranteed to support
1010 * in SVGA_3D_CMD_DRAWPRIMITIVES.
1011 */
1012#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
1013
1014/*
1015 * Identifiers for commands in the command FIFO.
1016 *
1017 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
1018 * the SVGA3D protocol and remain reserved; they should not be used in the
1019 * future.
1020 *
1021 * IDs between 1040 and 1999 (inclusive) are available for use by the
1022 * current SVGA3D protocol.
1023 *
1024 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
1025 * and up.
1026 */
1027
1028#define SVGA_3D_CMD_LEGACY_BASE 1000
1029#define SVGA_3D_CMD_BASE 1040
1030
1031#define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 // Deprecated
1032#define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
1033#define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
1034#define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
1035#define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
1036#define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
1037#define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
1038#define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
1039#define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8
1040#define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
1041#define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
1042#define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
1043#define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
1044#define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
1045#define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
1046#define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
1047#define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
1048#define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17
1049#define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 // Deprecated
1050#define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
1051#define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
1052#define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
1053#define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
1054#define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
1055#define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
1056#define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
1057#define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26
1058#define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
1059#define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 // Deprecated
1060#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
1061#define SVGA_3D_CMD_SURFACE_DEFINE_V2 SVGA_3D_CMD_BASE + 30
1062#define SVGA_3D_CMD_GENERATE_MIPMAPS SVGA_3D_CMD_BASE + 31
1063#define SVGA_3D_CMD_ACTIVATE_SURFACE SVGA_3D_CMD_BASE + 40
1064#define SVGA_3D_CMD_DEACTIVATE_SURFACE SVGA_3D_CMD_BASE + 41
1065#define SVGA_3D_CMD_MAX SVGA_3D_CMD_BASE + 42
1066
1067#define SVGA_3D_CMD_FUTURE_MAX 2000
1068
1069/*
1070 * Common substructures used in multiple FIFO commands:
1071 */
1072
1073typedef struct {
1074 union {
1075 struct {
1076 uint16_t function; // SVGA3dFogFunction
1077 uint8_t type; // SVGA3dFogType
1078 uint8_t base; // SVGA3dFogBase
1079 } s;
1080 uint32_t uintValue;
1081 };
1082} SVGA3dFogMode;
1083
1084/*
1085 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1086 * is a surface ID as well as face/mipmap indices.
1087 */
1088
1089typedef
1090struct SVGA3dSurfaceImageId {
1091 uint32_t sid;
1092 uint32_t face;
1093 uint32_t mipmap;
1094} SVGA3dSurfaceImageId;
1095
1096typedef
1097struct SVGA3dGuestImage {
1098 SVGAGuestPtr ptr;
1099
1100 /*
1101 * A note on interpretation of pitch: This value of pitch is the
1102 * number of bytes between vertically adjacent image
1103 * blocks. Normally this is the number of bytes between the first
1104 * pixel of two adjacent scanlines. With compressed textures,
1105 * however, this may represent the number of bytes between
1106 * compression blocks rather than between rows of pixels.
1107 *
1108 * XXX: Compressed textures currently must be tightly packed in guest memory.
1109 *
1110 * If the image is 1-dimensional, pitch is ignored.
1111 *
1112 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
1113 * assuming each row of blocks is tightly packed.
1114 */
1115 uint32_t pitch;
1116} SVGA3dGuestImage;
1117
1118
1119/*
1120 * FIFO command format definitions:
1121 */
1122
1123/*
1124 * The data size header following cmdNum for every 3d command
1125 */
1126typedef
1127struct {
1128 /* uint32_t id; duplicate*/
1129 uint32_t size;
1130} SVGA3dCmdHeader;
1131
1132/*
1133 * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
1134 * optional mipmaps and cube faces.
1135 */
1136
1137typedef
1138struct {
1139 uint32_t width;
1140 uint32_t height;
1141 uint32_t depth;
1142} SVGA3dSize;
1143
1144typedef enum {
1145 SVGA3D_SURFACE_CUBEMAP = (1 << 0),
1146 SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
1147 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
1148 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
1149 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
1150 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
1151 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
1152 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
1153 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
1154 SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
1155 SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10)
1156} SVGA3dSurfaceFlags;
1157
1158typedef
1159struct {
1160 uint32_t numMipLevels;
1161} SVGA3dSurfaceFace;
1162
1163typedef
1164struct {
1165 uint32_t sid;
1166 SVGA3dSurfaceFlags surfaceFlags;
1167 SVGA3dSurfaceFormat format;
1168 /*
1169 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1170 * structures must have the same value of numMipLevels field.
1171 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1172 * numMipLevels set to 0.
1173 */
1174 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1175 /*
1176 * Followed by an SVGA3dSize structure for each mip level in each face.
1177 *
1178 * A note on surface sizes: Sizes are always specified in pixels,
1179 * even if the true surface size is not a multiple of the minimum
1180 * block size of the surface's format. For example, a 3x3x1 DXT1
1181 * compressed texture would actually be stored as a 4x4x1 image in
1182 * memory.
1183 */
1184} SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
1185
1186typedef
1187struct {
1188 uint32_t sid;
1189 SVGA3dSurfaceFlags surfaceFlags;
1190 SVGA3dSurfaceFormat format;
1191 /*
1192 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1193 * structures must have the same value of numMipLevels field.
1194 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1195 * numMipLevels set to 0.
1196 */
1197 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1198 uint32_t multisampleCount;
1199 SVGA3dTextureFilter autogenFilter;
1200 /*
1201 * Followed by an SVGA3dSize structure for each mip level in each face.
1202 *
1203 * A note on surface sizes: Sizes are always specified in pixels,
1204 * even if the true surface size is not a multiple of the minimum
1205 * block size of the surface's format. For example, a 3x3x1 DXT1
1206 * compressed texture would actually be stored as a 4x4x1 image in
1207 * memory.
1208 */
1209} SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
1210
1211typedef
1212struct {
1213 uint32_t sid;
1214} SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
1215
1216typedef
1217struct {
1218 uint32_t cid;
1219} SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
1220
1221typedef
1222struct {
1223 uint32_t cid;
1224} SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
1225
1226typedef
1227struct {
1228 uint32_t cid;
1229 SVGA3dClearFlag clearFlag;
1230 uint32_t color;
1231 float depth;
1232 uint32_t stencil;
1233 /* Followed by variable number of SVGA3dRect structures */
1234} SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
1235
1236typedef
1237struct SVGA3dCopyRect {
1238 uint32_t x;
1239 uint32_t y;
1240 uint32_t w;
1241 uint32_t h;
1242 uint32_t srcx;
1243 uint32_t srcy;
1244} SVGA3dCopyRect;
1245
1246typedef
1247struct SVGA3dCopyBox {
1248 uint32_t x;
1249 uint32_t y;
1250 uint32_t z;
1251 uint32_t w;
1252 uint32_t h;
1253 uint32_t d;
1254 uint32_t srcx;
1255 uint32_t srcy;
1256 uint32_t srcz;
1257} SVGA3dCopyBox;
1258
1259typedef
1260struct {
1261 uint32_t x;
1262 uint32_t y;
1263 uint32_t w;
1264 uint32_t h;
1265} SVGA3dRect;
1266
1267typedef
1268struct {
1269 uint32_t x;
1270 uint32_t y;
1271 uint32_t z;
1272 uint32_t w;
1273 uint32_t h;
1274 uint32_t d;
1275} SVGA3dBox;
1276
1277typedef
1278struct {
1279 uint32_t x;
1280 uint32_t y;
1281 uint32_t z;
1282} SVGA3dPoint;
1283
1284typedef
1285struct {
1286 SVGA3dLightType type;
1287 SVGA3dBool inWorldSpace;
1288 float diffuse[4];
1289 float specular[4];
1290 float ambient[4];
1291 float position[4];
1292 float direction[4];
1293 float range;
1294 float falloff;
1295 float attenuation0;
1296 float attenuation1;
1297 float attenuation2;
1298 float theta;
1299 float phi;
1300} SVGA3dLightData;
1301
1302typedef
1303struct {
1304 uint32_t sid;
1305 /* Followed by variable number of SVGA3dCopyRect structures */
1306} SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
1307
1308typedef
1309struct {
1310 SVGA3dRenderStateName state;
1311 union {
1312 uint32_t uintValue;
1313 float floatValue;
1314 };
1315} SVGA3dRenderState;
1316
1317typedef
1318struct {
1319 uint32_t cid;
1320 /* Followed by variable number of SVGA3dRenderState structures */
1321} SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
1322
1323typedef
1324struct {
1325 uint32_t cid;
1326 SVGA3dRenderTargetType type;
1327 SVGA3dSurfaceImageId target;
1328} SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
1329
1330typedef
1331struct {
1332 SVGA3dSurfaceImageId src;
1333 SVGA3dSurfaceImageId dest;
1334 /* Followed by variable number of SVGA3dCopyBox structures */
1335} SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
1336
1337typedef
1338struct {
1339 SVGA3dSurfaceImageId src;
1340 SVGA3dSurfaceImageId dest;
1341 SVGA3dBox boxSrc;
1342 SVGA3dBox boxDest;
1343 SVGA3dStretchBltMode mode;
1344} SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
1345
1346typedef
1347struct {
1348 /*
1349 * If the discard flag is present in a surface DMA operation, the host may
1350 * discard the contents of the current mipmap level and face of the target
1351 * surface before applying the surface DMA contents.
1352 */
1353 uint32_t discard : 1;
1354
1355 /*
1356 * If the unsynchronized flag is present, the host may perform this upload
1357 * without syncing to pending reads on this surface.
1358 */
1359 uint32_t unsynchronized : 1;
1360
1361 /*
1362 * Guests *MUST* set the reserved bits to 0 before submitting the command
1363 * suffix as future flags may occupy these bits.
1364 */
1365 uint32_t reserved : 30;
1366} SVGA3dSurfaceDMAFlags;
1367
1368typedef
1369struct {
1370 SVGA3dGuestImage guest;
1371 SVGA3dSurfaceImageId host;
1372 SVGA3dTransferType transfer;
1373 /*
1374 * Followed by variable number of SVGA3dCopyBox structures. For consistency
1375 * in all clipping logic and coordinate translation, we define the
1376 * "source" in each copyBox as the guest image and the
1377 * "destination" as the host image, regardless of transfer
1378 * direction.
1379 *
1380 * For efficiency, the SVGA3D device is free to copy more data than
1381 * specified. For example, it may round copy boxes outwards such
1382 * that they lie on particular alignment boundaries.
1383 */
1384} SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
1385
1386/*
1387 * SVGA3dCmdSurfaceDMASuffix --
1388 *
1389 * This is a command suffix that will appear after a SurfaceDMA command in
1390 * the FIFO. It contains some extra information that hosts may use to
1391 * optimize performance or protect the guest. This suffix exists to preserve
1392 * backwards compatibility while also allowing for new functionality to be
1393 * implemented.
1394 */
1395
1396typedef
1397struct {
1398 uint32_t suffixSize;
1399
1400 /*
1401 * The maximum offset is used to determine the maximum offset from the
1402 * guestPtr base address that will be accessed or written to during this
1403 * surfaceDMA. If the suffix is supported, the host will respect this
1404 * boundary while performing surface DMAs.
1405 *
1406 * Defaults to MAX_uint32_t
1407 */
1408 uint32_t maximumOffset;
1409
1410 /*
1411 * A set of flags that describes optimizations that the host may perform
1412 * while performing this surface DMA operation. The guest should never rely
1413 * on behaviour that is different when these flags are set for correctness.
1414 *
1415 * Defaults to 0
1416 */
1417 SVGA3dSurfaceDMAFlags flags;
1418} SVGA3dCmdSurfaceDMASuffix;
1419
1420/*
1421 * SVGA_3D_CMD_DRAW_PRIMITIVES --
1422 *
1423 * This command is the SVGA3D device's generic drawing entry point.
1424 * It can draw multiple ranges of primitives, optionally using an
1425 * index buffer, using an arbitrary collection of vertex buffers.
1426 *
1427 * Each SVGA3dVertexDecl defines a distinct vertex array to bind
1428 * during this draw call. The declarations specify which surface
1429 * the vertex data lives in, what that vertex data is used for,
1430 * and how to interpret it.
1431 *
1432 * Each SVGA3dPrimitiveRange defines a collection of primitives
1433 * to render using the same vertex arrays. An index buffer is
1434 * optional.
1435 */
1436
1437typedef
1438struct {
1439 /*
1440 * A range hint is an optional specification for the range of indices
1441 * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
1442 * that the entire array will be used.
1443 *
1444 * These are only hints. The SVGA3D device may use them for
1445 * performance optimization if possible, but it's also allowed to
1446 * ignore these values.
1447 */
1448 uint32_t first;
1449 uint32_t last;
1450} SVGA3dArrayRangeHint;
1451
1452typedef
1453struct {
1454 /*
1455 * Define the origin and shape of a vertex or index array. Both
1456 * 'offset' and 'stride' are in bytes. The provided surface will be
1457 * reinterpreted as a flat array of bytes in the same format used
1458 * by surface DMA operations. To avoid unnecessary conversions, the
1459 * surface should be created with the SVGA3D_BUFFER format.
1460 *
1461 * Index 0 in the array starts 'offset' bytes into the surface.
1462 * Index 1 begins at byte 'offset + stride', etc. Array indices may
1463 * not be negative.
1464 */
1465 uint32_t surfaceId;
1466 uint32_t offset;
1467 uint32_t stride;
1468} SVGA3dArray;
1469
1470typedef
1471struct {
1472 /*
1473 * Describe a vertex array's data type, and define how it is to be
1474 * used by the fixed function pipeline or the vertex shader. It
1475 * isn't useful to have two VertexDecls with the same
1476 * VertexArrayIdentity in one draw call.
1477 */
1478 SVGA3dDeclType type;
1479 SVGA3dDeclMethod method;
1480 SVGA3dDeclUsage usage;
1481 uint32_t usageIndex;
1482} SVGA3dVertexArrayIdentity;
1483
1484typedef
1485struct {
1486 SVGA3dVertexArrayIdentity identity;
1487 SVGA3dArray array;
1488 SVGA3dArrayRangeHint rangeHint;
1489} SVGA3dVertexDecl;
1490
1491typedef
1492struct {
1493 /*
1494 * Define a group of primitives to render, from sequential indices.
1495 *
1496 * The value of 'primitiveType' and 'primitiveCount' imply the
1497 * total number of vertices that will be rendered.
1498 */
1499 SVGA3dPrimitiveType primType;
1500 uint32_t primitiveCount;
1501
1502 /*
1503 * Optional index buffer. If indexArray.surfaceId is
1504 * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
1505 * without an index buffer is identical to rendering with an index
1506 * buffer containing the sequence [0, 1, 2, 3, ...].
1507 *
1508 * If an index buffer is in use, indexWidth specifies the width in
1509 * bytes of each index value. It must be less than or equal to
1510 * indexArray.stride.
1511 *
1512 * (Currently, the SVGA3D device requires index buffers to be tightly
1513 * packed. In other words, indexWidth == indexArray.stride)
1514 */
1515 SVGA3dArray indexArray;
1516 uint32_t indexWidth;
1517
1518 /*
1519 * Optional index bias. This number is added to all indices from
1520 * indexArray before they are used as vertex array indices. This
1521 * can be used in multiple ways:
1522 *
1523 * - When not using an indexArray, this bias can be used to
1524 * specify where in the vertex arrays to begin rendering.
1525 *
1526 * - A positive number here is equivalent to increasing the
1527 * offset in each vertex array.
1528 *
1529 * - A negative number can be used to render using a small
1530 * vertex array and an index buffer that contains large
1531 * values. This may be used by some applications that
1532 * crop a vertex buffer without modifying their index
1533 * buffer.
1534 *
1535 * Note that rendering with a negative bias value may be slower and
1536 * use more memory than rendering with a positive or zero bias.
1537 */
1538 int32_t indexBias;
1539} SVGA3dPrimitiveRange;
1540
1541typedef
1542struct {
1543 uint32_t cid;
1544 uint32_t numVertexDecls;
1545 uint32_t numRanges;
1546
1547 /*
1548 * There are two variable size arrays after the
1549 * SVGA3dCmdDrawPrimitives structure. In order,
1550 * they are:
1551 *
1552 * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
1553 * SVGA3D_MAX_VERTEX_ARRAYS;
1554 * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
1555 * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
1556 * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
1557 * the frequency divisor for the corresponding vertex decl).
1558 */
1559} SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
1560
1561typedef
1562struct {
1563 uint32_t stage;
1564 SVGA3dTextureStateName name;
1565 union {
1566 uint32_t value;
1567 float floatValue;
1568 };
1569} SVGA3dTextureState;
1570
1571typedef
1572struct {
1573 uint32_t cid;
1574 /* Followed by variable number of SVGA3dTextureState structures */
1575} SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
1576
1577typedef
1578struct {
1579 uint32_t cid;
1580 SVGA3dTransformType type;
1581 float matrix[16];
1582} SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
1583
1584typedef
1585struct {
1586 float min;
1587 float max;
1588} SVGA3dZRange;
1589
1590typedef
1591struct {
1592 uint32_t cid;
1593 SVGA3dZRange zRange;
1594} SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
1595
1596typedef
1597struct {
1598 float diffuse[4];
1599 float ambient[4];
1600 float specular[4];
1601 float emissive[4];
1602 float shininess;
1603} SVGA3dMaterial;
1604
1605typedef
1606struct {
1607 uint32_t cid;
1608 SVGA3dFace face;
1609 SVGA3dMaterial material;
1610} SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
1611
1612typedef
1613struct {
1614 uint32_t cid;
1615 uint32_t index;
1616 SVGA3dLightData data;
1617} SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
1618
1619typedef
1620struct {
1621 uint32_t cid;
1622 uint32_t index;
1623 uint32_t enabled;
1624} SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
1625
1626typedef
1627struct {
1628 uint32_t cid;
1629 SVGA3dRect rect;
1630} SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
1631
1632typedef
1633struct {
1634 uint32_t cid;
1635 SVGA3dRect rect;
1636} SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
1637
1638typedef
1639struct {
1640 uint32_t cid;
1641 uint32_t index;
1642 float plane[4];
1643} SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
1644
1645typedef
1646struct {
1647 uint32_t cid;
1648 uint32_t shid;
1649 SVGA3dShaderType type;
1650 /* Followed by variable number of DWORDs for shader bycode */
1651} SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
1652
1653typedef
1654struct {
1655 uint32_t cid;
1656 uint32_t shid;
1657 SVGA3dShaderType type;
1658} SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
1659
1660typedef
1661struct {
1662 uint32_t cid;
1663 uint32_t reg; /* register number */
1664 SVGA3dShaderType type;
1665 SVGA3dShaderConstType ctype;
1666 uint32_t values[4];
1667} SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
1668
1669typedef
1670struct {
1671 uint32_t cid;
1672 SVGA3dShaderType type;
1673 uint32_t shid;
1674} SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
1675
1676typedef
1677struct {
1678 uint32_t cid;
1679 SVGA3dQueryType type;
1680} SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
1681
1682typedef
1683struct {
1684 uint32_t cid;
1685 SVGA3dQueryType type;
1686 SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1687} SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
1688
1689typedef
1690struct {
1691 uint32_t cid; /* Same parameters passed to END_QUERY */
1692 SVGA3dQueryType type;
1693 SVGAGuestPtr guestResult;
1694} SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
1695
1696typedef
1697struct {
1698 uint32_t totalSize; /* Set by guest before query is ended. */
1699 SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1700 union { /* Set by host on exit from PENDING state */
1701 uint32_t result32;
1702 };
1703} SVGA3dQueryResult;
1704
1705/*
1706 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1707 *
1708 * This is a blit from an SVGA3D surface to a Screen Object. Just
1709 * like GMR-to-screen blits, this blit may be directed at a
1710 * specific screen or to the virtual coordinate space.
1711 *
1712 * The blit copies from a rectangular region of an SVGA3D surface
1713 * image to a rectangular region of a screen or screens.
1714 *
1715 * This command takes an optional variable-length list of clipping
1716 * rectangles after the body of the command. If no rectangles are
1717 * specified, there is no clipping region. The entire destRect is
1718 * drawn to. If one or more rectangles are included, they describe
1719 * a clipping region. The clip rectangle coordinates are measured
1720 * relative to the top-left corner of destRect.
1721 *
1722 * This clipping region serves multiple purposes:
1723 *
1724 * - It can be used to perform an irregularly shaped blit more
1725 * efficiently than by issuing many separate blit commands.
1726 *
1727 * - It is equivalent to allowing blits with non-integer
1728 * source coordinates. You could blit just one half-pixel
1729 * of a source, for example, by specifying a larger
1730 * destination rectangle than you need, then removing
1731 * part of it using a clip rectangle.
1732 *
1733 * Availability:
1734 * SVGA_FIFO_CAP_SCREEN_OBJECT
1735 *
1736 * Limitations:
1737 *
1738 * - Currently, no backend supports blits from a mipmap or face
1739 * other than the first one.
1740 */
1741
1742typedef
1743struct {
1744 SVGA3dSurfaceImageId srcImage;
1745 SVGASignedRect srcRect;
1746 uint32_t destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
1747 SVGASignedRect destRect; /* Supports scaling if src/rest different size */
1748 /* Clipping: zero or more SVGASignedRects follow */
1749} SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
1750
1751typedef
1752struct {
1753 uint32_t sid;
1754 SVGA3dTextureFilter filter;
1755} SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
1756
1757
1758/*
1759 * Capability query index.
1760 *
1761 * Notes:
1762 *
1763 * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
1764 * fixed-function texture units available. Each of these units
1765 * work in both FFP and Shader modes, and they support texture
1766 * transforms and texture coordinates. The host may have additional
1767 * texture image units that are only usable with shaders.
1768 *
1769 * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
1770 * return TRUE. Even on physical hardware that does not support
1771 * these formats natively, the SVGA3D device will provide an emulation
1772 * which should be invisible to the guest OS.
1773 *
1774 * In general, the SVGA3D device should support any operation on
1775 * any surface format, it just may perform some of these
1776 * operations in software depending on the capabilities of the
1777 * available physical hardware.
1778 *
1779 * XXX: In the future, we will add capabilities that describe in
1780 * detail what formats are supported in hardware for what kinds
1781 * of operations.
1782 */
1783
1784typedef enum {
1785 SVGA3D_DEVCAP_3D = 0,
1786 SVGA3D_DEVCAP_MAX_LIGHTS = 1,
1787 SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */
1788 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
1789 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
1790 SVGA3D_DEVCAP_VERTEX_SHADER = 5,
1791 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
1792 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
1793 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
1794 SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
1795 SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
1796 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
1797 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
1798 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
1799 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
1800 SVGA3D_DEVCAP_QUERY_TYPES = 15,
1801 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
1802 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
1803 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
1804 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
1805 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
1806 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
1807 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
1808 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
1809 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
1810 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
1811 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
1812 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
1813 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
1814 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
1815 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
1816 SVGA3D_DEVCAP_TEXTURE_OPS = 31,
1817 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
1818 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
1819 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
1820 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
1821 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
1822 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
1823 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
1824 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
1825 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
1826 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
1827 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
1828 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
1829 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
1830 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
1831 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
1832 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
1833 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
1834 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
1835 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
1836 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
1837 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
1838 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
1839 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
1840 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
1841 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
1842 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
1843 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
1844 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
1845 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
1846 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
1847 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
1848
1849 /*
1850 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
1851 * render targets. This does no include the depth or stencil targets.
1852 */
1853 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
1854
1855 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
1856 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
1857 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
1858 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
1859 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
1860 SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
1861 SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
1862 SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
1863 SVGA3D_DEVCAP_SUPERSAMPLE = 73,
1864 SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
1865 SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
1866 SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
1867
1868 /*
1869 * This is the maximum number of SVGA context IDs that the guest
1870 * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
1871 */
1872 SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
1873
1874 /*
1875 * This is the maximum number of SVGA surface IDs that the guest
1876 * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
1877 */
1878 SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
1879
1880 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
1881 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
1882 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
1883
1884 SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = 82,
1885 SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = 83,
1886
1887 /*
1888 * Don't add new caps into the previous section; the values in this
1889 * enumeration must not change. You can put new values right before
1890 * SVGA3D_DEVCAP_MAX.
1891 */
1892 SVGA3D_DEVCAP_MAX /* This must be the last index. */
1893} SVGA3dDevCapIndex;
1894
1895typedef union {
1896 bool b;
1897 uint32_t u;
1898 int32_t i;
1899 float f;
1900} SVGA3dDevCapResult;
1901
1902#endif /* _SVGA3D_REG_H_ */
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