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source: vbox/trunk/src/VBox/Devices/Graphics/vmsvga/svga3d_shaderdefs.h@ 58436

最後變更 在這個檔案從58436是 52970,由 vboxsync 提交於 10 年 前

Devices/Graphics: added original vmsvga and vmsvga_glext headers (2009-04)
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1/**********************************************************
2 * Copyright 2007-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_shaderdefs.h --
28 *
29 * SVGA3D byte code format and limit definitions.
30 *
31 * The format of the byte code directly corresponds to that defined
32 * by Microsoft DirectX SDK 9.0c (file d3d9types.h). The format can
33 * also be extended so that different shader formats can be supported
34 * for example GLSL, ARB vp/fp, NV/ATI shader formats, etc.
35 *
36 */
37
38#ifndef __SVGA3D_SHADER_DEFS__
39#define __SVGA3D_SHADER_DEFS__
40
41/* SVGA3D shader hardware limits. */
42
43#define SVGA3D_INPUTREG_MAX 16
44#define SVGA3D_OUTPUTREG_MAX 12
45#define SVGA3D_VERTEX_SAMPLERREG_MAX 4
46#define SVGA3D_PIXEL_SAMPLERREG_MAX 16
47#define SVGA3D_SAMPLERREG_MAX (SVGA3D_PIXEL_SAMPLERREG_MAX+\
48 SVGA3D_VERTEX_SAMPLERREG_MAX)
49#define SVGA3D_TEMPREG_MAX 32
50#define SVGA3D_CONSTREG_MAX 256
51#define SVGA3D_CONSTINTREG_MAX 16
52#define SVGA3D_CONSTBOOLREG_MAX 16
53#define SVGA3D_ADDRREG_MAX 1
54#define SVGA3D_PREDREG_MAX 1
55
56/* SVGA3D byte code specific limits */
57
58#define SVGA3D_MAX_SRC_REGS 4
59#define SVGA3D_MAX_NESTING_LEVEL 32
60
61/* SVGA3D version information. */
62
63#define SVGA3D_VS_TYPE 0xFFFE
64#define SVGA3D_PS_TYPE 0xFFFF
65
66typedef struct {
67 union {
68 struct {
69 uint32_t minor : 8;
70 uint32_t major : 8;
71 uint32_t type : 16;
72 } s;
73
74 uint32_t value;
75 };
76} SVGA3dShaderVersion;
77
78#define SVGA3D_VS_10 ((SVGA3D_VS_TYPE << 16) | 1 << 8)
79#define SVGA3D_VS_11 (SVGA3D_VS_10 | 1)
80#define SVGA3D_VS_20 ((SVGA3D_VS_TYPE << 16) | 2 << 8)
81#define SVGA3D_VS_30 ((SVGA3D_VS_TYPE << 16) | 3 << 8)
82
83#define SVGA3D_PS_10 ((SVGA3D_PS_TYPE << 16) | 1 << 8)
84#define SVGA3D_PS_11 (SVGA3D_PS_10 | 1)
85#define SVGA3D_PS_12 (SVGA3D_PS_10 | 2)
86#define SVGA3D_PS_13 (SVGA3D_PS_10 | 3)
87#define SVGA3D_PS_14 (SVGA3D_PS_10 | 4)
88#define SVGA3D_PS_20 ((SVGA3D_PS_TYPE << 16) | 2 << 8)
89#define SVGA3D_PS_30 ((SVGA3D_PS_TYPE << 16) | 3 << 8)
90
91/* The *_ENABLED are for backwards compatibility with old drivers */
92typedef enum {
93 SVGA3DPSVERSION_NONE = 0,
94 SVGA3DPSVERSION_ENABLED = 1,
95 SVGA3DPSVERSION_11 = 3,
96 SVGA3DPSVERSION_12 = 5,
97 SVGA3DPSVERSION_13 = 7,
98 SVGA3DPSVERSION_14 = 9,
99 SVGA3DPSVERSION_20 = 11,
100 SVGA3DPSVERSION_30 = 13,
101 SVGA3DPSVERSION_40 = 15,
102 SVGA3DPSVERSION_MAX
103} SVGA3dPixelShaderVersion;
104
105typedef enum {
106 SVGA3DVSVERSION_NONE = 0,
107 SVGA3DVSVERSION_ENABLED = 1,
108 SVGA3DVSVERSION_11 = 3,
109 SVGA3DVSVERSION_20 = 5,
110 SVGA3DVSVERSION_30 = 7,
111 SVGA3DVSVERSION_40 = 9,
112 SVGA3DVSVERSION_MAX
113} SVGA3dVertexShaderVersion;
114
115/* SVGA3D instruction op codes. */
116
117typedef enum {
118 SVGA3DOP_NOP = 0,
119 SVGA3DOP_MOV,
120 SVGA3DOP_ADD,
121 SVGA3DOP_SUB,
122 SVGA3DOP_MAD,
123 SVGA3DOP_MUL,
124 SVGA3DOP_RCP,
125 SVGA3DOP_RSQ,
126 SVGA3DOP_DP3,
127 SVGA3DOP_DP4,
128 SVGA3DOP_MIN,
129 SVGA3DOP_MAX,
130 SVGA3DOP_SLT,
131 SVGA3DOP_SGE,
132 SVGA3DOP_EXP,
133 SVGA3DOP_LOG,
134 SVGA3DOP_LIT,
135 SVGA3DOP_DST,
136 SVGA3DOP_LRP,
137 SVGA3DOP_FRC,
138 SVGA3DOP_M4x4,
139 SVGA3DOP_M4x3,
140 SVGA3DOP_M3x4,
141 SVGA3DOP_M3x3,
142 SVGA3DOP_M3x2,
143 SVGA3DOP_CALL,
144 SVGA3DOP_CALLNZ,
145 SVGA3DOP_LOOP,
146 SVGA3DOP_RET,
147 SVGA3DOP_ENDLOOP,
148 SVGA3DOP_LABEL,
149 SVGA3DOP_DCL,
150 SVGA3DOP_POW,
151 SVGA3DOP_CRS,
152 SVGA3DOP_SGN,
153 SVGA3DOP_ABS,
154 SVGA3DOP_NRM,
155 SVGA3DOP_SINCOS,
156 SVGA3DOP_REP,
157 SVGA3DOP_ENDREP,
158 SVGA3DOP_IF,
159 SVGA3DOP_IFC,
160 SVGA3DOP_ELSE,
161 SVGA3DOP_ENDIF,
162 SVGA3DOP_BREAK,
163 SVGA3DOP_BREAKC,
164 SVGA3DOP_MOVA,
165 SVGA3DOP_DEFB,
166 SVGA3DOP_DEFI,
167 SVGA3DOP_TEXCOORD = 64,
168 SVGA3DOP_TEXKILL,
169 SVGA3DOP_TEX,
170 SVGA3DOP_TEXBEM,
171 SVGA3DOP_TEXBEML,
172 SVGA3DOP_TEXREG2AR,
173 SVGA3DOP_TEXREG2GB = 70,
174 SVGA3DOP_TEXM3x2PAD,
175 SVGA3DOP_TEXM3x2TEX,
176 SVGA3DOP_TEXM3x3PAD,
177 SVGA3DOP_TEXM3x3TEX,
178 SVGA3DOP_RESERVED0,
179 SVGA3DOP_TEXM3x3SPEC,
180 SVGA3DOP_TEXM3x3VSPEC,
181 SVGA3DOP_EXPP,
182 SVGA3DOP_LOGP,
183 SVGA3DOP_CND = 80,
184 SVGA3DOP_DEF,
185 SVGA3DOP_TEXREG2RGB,
186 SVGA3DOP_TEXDP3TEX,
187 SVGA3DOP_TEXM3x2DEPTH,
188 SVGA3DOP_TEXDP3,
189 SVGA3DOP_TEXM3x3,
190 SVGA3DOP_TEXDEPTH,
191 SVGA3DOP_CMP,
192 SVGA3DOP_BEM,
193 SVGA3DOP_DP2ADD = 90,
194 SVGA3DOP_DSX,
195 SVGA3DOP_DSY,
196 SVGA3DOP_TEXLDD,
197 SVGA3DOP_SETP,
198 SVGA3DOP_TEXLDL,
199 SVGA3DOP_BREAKP = 96,
200 SVGA3DOP_LAST_INST,
201 SVGA3DOP_PHASE = 0xFFFD,
202 SVGA3DOP_COMMENT = 0xFFFE,
203 SVGA3DOP_END = 0xFFFF
204} SVGA3dShaderOpCodeType;
205
206/* SVGA3D operation control/comparison function types */
207
208typedef enum {
209 SVGA3DOPCONT_NONE,
210 SVGA3DOPCONT_PROJECT, /* Projective texturing */
211 SVGA3DOPCONT_BIAS /* Texturing with a LOD bias */
212} SVGA3dShaderOpCodeControlFnType;
213
214typedef enum {
215 SVGA3DOPCOMP_RESERVED0 = 0,
216 SVGA3DOPCOMP_GT,
217 SVGA3DOPCOMP_EQ,
218 SVGA3DOPCOMP_GE,
219 SVGA3DOPCOMP_LT,
220 SVGA3DOPCOMPC_NE,
221 SVGA3DOPCOMP_LE,
222 SVGA3DOPCOMP_RESERVED1
223} SVGA3dShaderOpCodeCompFnType;
224
225/* SVGA3D register types */
226
227typedef enum {
228 SVGA3DREG_TEMP = 0, /* Temporary register file */
229 SVGA3DREG_INPUT, /* Input register file */
230 SVGA3DREG_CONST, /* Constant register file */
231 SVGA3DREG_ADDR, /* Address register for VS */
232 SVGA3DREG_TEXTURE = 3, /* Texture register file for PS */
233 SVGA3DREG_RASTOUT, /* Rasterizer register file */
234 SVGA3DREG_ATTROUT, /* Attribute output register file */
235 SVGA3DREG_TEXCRDOUT, /* Texture coordinate output register file */
236 SVGA3DREG_OUTPUT = 6, /* Output register file for VS 3.0+ */
237 SVGA3DREG_CONSTINT, /* Constant integer vector register file */
238 SVGA3DREG_COLOROUT, /* Color output register file */
239 SVGA3DREG_DEPTHOUT, /* Depth output register file */
240 SVGA3DREG_SAMPLER, /* Sampler state register file */
241 SVGA3DREG_CONST2, /* Constant register file 2048 - 4095 */
242 SVGA3DREG_CONST3, /* Constant register file 4096 - 6143 */
243 SVGA3DREG_CONST4, /* Constant register file 6144 - 8191 */
244 SVGA3DREG_CONSTBOOL, /* Constant boolean register file */
245 SVGA3DREG_LOOP, /* Loop counter register file */
246 SVGA3DREG_TEMPFLOAT16, /* 16-bit float temp register file */
247 SVGA3DREG_MISCTYPE, /* Miscellaneous (single) registers */
248 SVGA3DREG_LABEL, /* Label */
249 SVGA3DREG_PREDICATE /* Predicate register */
250} SVGA3dShaderRegType;
251
252/* SVGA3D rasterizer output register types */
253
254typedef enum {
255 SVGA3DRASTOUT_POSITION = 0,
256 SVGA3DRASTOUT_FOG,
257 SVGA3DRASTOUT_PSIZE
258} SVGA3dShaderRastOutRegType;
259
260/* SVGA3D miscellaneous register types */
261
262typedef enum {
263 SVGA3DMISCREG_POSITION = 0, /* Input position x,y,z,rhw (PS) */
264 SVGA3DMISCREG_FACE /* Floating point primitive area (PS) */
265} SVGA3DShaderMiscRegType;
266
267/* SVGA3D sampler types */
268
269typedef enum {
270 SVGA3DSAMP_UNKNOWN = 0, /* Uninitialized value */
271 SVGA3DSAMP_2D = 2, /* dcl_2d s# (for declaring a 2-D texture) */
272 SVGA3DSAMP_CUBE, /* dcl_cube s# (for declaring a cube texture) */
273 SVGA3DSAMP_VOLUME /* dcl_volume s# (for declaring a volume texture) */
274} SVGA3dShaderSamplerType;
275
276/* SVGA3D sampler format classes */
277
278typedef enum {
279 SVGA3DSAMPFORMAT_ARGB, /* ARGB formats */
280 SVGA3DSAMPFORMAT_V8U8, /* Sign and normalize (SNORM) V & U */
281 SVGA3DSAMPFORMAT_Q8W8V8U8, /* SNORM all */
282 SVGA3DSAMPFORMAT_CxV8U8, /* SNORM V & U, C=SQRT(1-U^2-V^2) */
283 SVGA3DSAMPFORMAT_X8L8V8U8, /* SNORM V & U */
284 SVGA3DSAMPFORMAT_A2W10V10U10, /* SNORM W, V & U */
285 SVGA3DSAMPFORMAT_DXT_PMA, /* DXT pre-multiplied alpha */
286 SVGA3DSAMPFORMAT_YUV, /* YUV video format */
287 SVGA3DSAMPFORMAT_UYVY, /* UYVY video format */
288 SVGA3DSAMPFORMAT_Rx, /* R16F/32F */
289 SVGA3DSAMPFORMAT_RxGx, /* R16FG16F, R32FG32F */
290 SVGA3DSAMPFORMAT_V16U16 /* SNORM all */
291} SVGA3DShaderSamplerFormatClass;
292
293/* SVGA3D write mask */
294
295#define SVGA3DWRITEMASK_0 1 /* Component 0 (X;Red) */
296#define SVGA3DWRITEMASK_1 2 /* Component 1 (Y;Green) */
297#define SVGA3DWRITEMASK_2 4 /* Component 2 (Z;Blue) */
298#define SVGA3DWRITEMASK_3 8 /* Component 3 (W;Alpha) */
299#define SVGA3DWRITEMASK_ALL 15 /* All components */
300
301/* SVGA3D destination modifiers */
302
303#define SVGA3DDSTMOD_NONE 0 /* nop */
304#define SVGA3DDSTMOD_SATURATE 1 /* clamp to [0, 1] */
305#define SVGA3DDSTMOD_PARTIALPRECISION 2 /* Partial precision hint */
306
307/*
308 * Relevant to multisampling only:
309 * When the pixel center is not covered, sample
310 * attribute or compute gradients/LOD
311 * using multisample "centroid" location.
312 * "Centroid" is some location within the covered
313 * region of the pixel.
314 */
315
316#define SVGA3DDSTMOD_MSAMPCENTROID 4
317
318/* SVGA3D source swizzle */
319
320#define SVGA3DSWIZZLE_REPLICATEX 0x00
321#define SVGA3DSWIZZLE_REPLICATEY 0x55
322#define SVGA3DSWIZZLE_REPLICATEZ 0xAA
323#define SVGA3DSWIZZLE_REPLICATEW 0xFF
324#define SVGA3DSWIZZLE_NONE 0xE4
325#define SVGA3DSWIZZLE_YZXW 0xC9
326#define SVGA3DSWIZZLE_ZXYW 0xD2
327#define SVGA3DSWIZZLE_WXYZ 0x1B
328
329/* SVGA3D source modifiers */
330
331typedef enum {
332 SVGA3DSRCMOD_NONE = 0, /* nop */
333 SVGA3DSRCMOD_NEG, /* negate */
334 SVGA3DSRCMOD_BIAS, /* bias */
335 SVGA3DSRCMOD_BIASNEG, /* bias and negate */
336 SVGA3DSRCMOD_SIGN, /* sign */
337 SVGA3DSRCMOD_SIGNNEG, /* sign and negate */
338 SVGA3DSRCMOD_COMP, /* complement */
339 SVGA3DSRCMOD_X2, /* x2 */
340 SVGA3DSRCMOD_X2NEG, /* x2 and negate */
341 SVGA3DSRCMOD_DZ, /* divide through by z component */
342 SVGA3DSRCMOD_DW, /* divide through by w component */
343 SVGA3DSRCMOD_ABS, /* abs() */
344 SVGA3DSRCMOD_ABSNEG, /* -abs() */
345 SVGA3DSRCMOD_NOT /* ! (for predicate register) */
346} SVGA3dShaderSrcModType;
347
348/* SVGA3D instruction token */
349
350typedef struct {
351 union {
352 struct {
353 uint32_t comment_op : 16;
354 uint32_t comment_size : 16;
355 } s;
356
357 struct {
358 uint32_t op : 16;
359 uint32_t control : 3;
360 uint32_t reserved2 : 5;
361 uint32_t size : 4;
362 uint32_t predicated : 1;
363 uint32_t reserved1 : 1;
364 uint32_t coissue : 1;
365 uint32_t reserved0 : 1;
366 } s1;
367
368 uint32_t value;
369 };
370} SVGA3dShaderInstToken;
371
372/* SVGA3D destination parameter token */
373
374typedef struct {
375 union {
376 struct {
377 uint32_t num : 11;
378 uint32_t type_upper : 2;
379 uint32_t relAddr : 1;
380 uint32_t reserved1 : 2;
381 uint32_t mask : 4;
382 uint32_t dstMod : 4;
383 uint32_t shfScale : 4;
384 uint32_t type_lower : 3;
385 uint32_t reserved0 : 1;
386 } s;
387
388 uint32_t value;
389 };
390} SVGA3dShaderDestToken;
391
392/* SVGA3D source parameter token */
393
394typedef struct {
395 union {
396 struct {
397 uint32_t num : 11;
398 uint32_t type_upper : 2;
399 uint32_t relAddr : 1;
400 uint32_t reserved1 : 2;
401 uint32_t swizzle : 8;
402 uint32_t srcMod : 4;
403 uint32_t type_lower : 3;
404 uint32_t reserved0 : 1;
405 } s;
406
407 uint32_t value;
408 };
409} SVGA3dShaderSrcToken;
410
411/* SVGA3DOP_DCL parameter tokens */
412
413typedef struct {
414 union {
415 struct {
416 union {
417 struct {
418 uint32_t usage : 5;
419 uint32_t reserved1 : 11;
420 uint32_t index : 4;
421 uint32_t reserved0 : 12;
422 } s; /* input / output declaration */
423
424 struct {
425 uint32_t reserved3 : 27;
426 uint32_t type : 4;
427 uint32_t reserved2 : 1;
428 } s1; /* sampler declaration */
429 };
430
431 SVGA3dShaderDestToken dst;
432 } s2;
433
434 uint32_t values[2];
435 };
436} SVGA3DOpDclArgs;
437
438/* SVGA3DOP_DEF parameter tokens */
439
440typedef struct {
441 union {
442 struct {
443 SVGA3dShaderDestToken dst;
444
445 union {
446 float constValues[4];
447 int constIValues[4];
448 bool constBValue;
449 };
450 } s;
451
452 uint32_t values[5];
453 };
454} SVGA3DOpDefArgs;
455
456/* SVGA3D shader token */
457
458typedef union {
459 uint32_t value;
460 SVGA3dShaderInstToken inst;
461 SVGA3dShaderDestToken dest;
462 SVGA3dShaderSrcToken src;
463} SVGA3dShaderToken;
464
465/* SVGA3D shader program */
466
467typedef struct {
468 SVGA3dShaderVersion version;
469 /* SVGA3dShaderToken stream */
470} SVGA3dShaderProgram;
471
472
473#if 0
474/* SVGA3D version specific register assignments */
475
476static const uint32_t SVGA3D_INPUT_REG_POSITION_VS11 = 0;
477static const uint32_t SVGA3D_INPUT_REG_PSIZE_VS11 = 1;
478static const uint32_t SVGA3D_INPUT_REG_FOG_VS11 = 3;
479static const uint32_t SVGA3D_INPUT_REG_FOG_MASK_VS11 = SVGA3DWRITEMASK_3;
480static const uint32_t SVGA3D_INPUT_REG_COLOR_BASE_VS11 = 2;
481static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_BASE_VS11 = 4;
482
483static const uint32_t SVGA3D_INPUT_REG_COLOR_BASE_PS11 = 0;
484static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_BASE_PS11 = 2;
485static const uint32_t SVGA3D_OUTPUT_REG_DEPTH_PS11 = 0;
486static const uint32_t SVGA3D_OUTPUT_REG_COLOR_PS11 = 1;
487
488static const uint32_t SVGA3D_INPUT_REG_COLOR_BASE_PS20 = 0;
489static const uint32_t SVGA3D_INPUT_REG_COLOR_NUM_PS20 = 2;
490static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_BASE_PS20 = 2;
491static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_NUM_PS20 = 8;
492static const uint32_t SVGA3D_OUTPUT_REG_COLOR_BASE_PS20 = 1;
493static const uint32_t SVGA3D_OUTPUT_REG_COLOR_NUM_PS20 = 4;
494static const uint32_t SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20 = 0;
495static const uint32_t SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20 = 1;
496
497/*
498 *----------------------------------------------------------------------
499 *
500 * SVGA3dShaderGetRegType --
501 *
502 * As the register type is split into two non sequential fields,
503 * this function provides an useful way of accessing the actual
504 * register type without having to manually concatenate the
505 * type_upper and type_lower fields.
506 *
507 * Results:
508 * Returns the register type.
509 *
510 *----------------------------------------------------------------------
511 */
512
513static INLINE SVGA3dShaderRegType
514SVGA3dShaderGetRegType(uint32_t token)
515{
516 SVGA3dShaderSrcToken src;
517 src.value = token;
518 return (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
519}
520#endif
521
522#endif /* __SVGA3D_SHADER_DEFS__ */
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