pcnet32.c@ 3542

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1	/**************************************************************************
2	*
3	* pcnet32.c -- Etherboot device driver for the AMD PCnet32
4	* Written 2003-2003 by Timothy Legge <[email protected]>
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	*
20	* Portions of this code based on:
21	* pcnet32.c: An AMD PCnet32 ethernet driver for linux:
22	*
23	* (C) 1996-1999 Thomas Bogendoerfer
24	* See Linux Driver for full information
25	*
26	* The transmit and poll functions were written with reference to:
27	* lance.c - LANCE NIC driver for Etherboot written by Ken Yap
28	*
29	* Linux Driver Version 1.27a, 10.02.2002
30	*
31	*
32	* REVISION HISTORY:
33	* ================
34	* v1.0 08-06-2003 timlegge Initial port of Linux driver
35	* v1.1 08-23-2003 timlegge Add multicast support
36	* v1.2 01-17-2004 timlegge Initial driver output cleanup
37	* v1.3 03-29-2004 timlegge More driver cleanup
38	*
39	* Indent Options: indent -kr -i8
40	***************************************************************************/
41
42	/* to get some global routines like printf */
43	#include "etherboot.h"
44	/* to get the interface to the body of the program */
45	#include "nic.h"
46	/* to get the PCI support functions, if this is a PCI NIC */
47	#include "pci.h"
48	/* Include the time functions */
49	#include "timer.h"
50	#include "mii.h"
51	/* void hex_dump(const char data, const unsigned int len); /
52
53	/* Etherboot Specific definations */
54	#define drv_version "v1.3"
55	#define drv_date "03-29-2004"
56
57	static u32 ioaddr; /* Globally used for the card's io address */
58
59	#ifdef EDEBUG
60	#define dprintf(x) printf x
61	#else
62	#define dprintf(x)
63	#endif
64
65	/* Condensed operations for readability. */
66	#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
67	#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
68
69	/* End Etherboot Specific */
70
71	int cards_found /* __initdata */ ;
72
73	#ifdef REMOVE
74	/* FIXME: Remove these they are probably pointless */
75
76	/*
77	* VLB I/O addresses
78	*/
79	static unsigned int pcnet32_portlist[] /__initdata / =
80	{ 0x300, 0x320, 0x340, 0x360, 0 };
81
82	static int pcnet32_debug = 1;
83	static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
84	static int pcnet32vlb; /* check for VLB cards ? */
85
86	static struct net_device *pcnet32_dev;
87
88	static int max_interrupt_work = 80;
89	static int rx_copybreak = 200;
90	#endif
91	#define PCNET32_PORT_AUI 0x00
92	#define PCNET32_PORT_10BT 0x01
93	#define PCNET32_PORT_GPSI 0x02
94	#define PCNET32_PORT_MII 0x03
95
96	#define PCNET32_PORT_PORTSEL 0x03
97	#define PCNET32_PORT_ASEL 0x04
98	#define PCNET32_PORT_100 0x40
99	#define PCNET32_PORT_FD 0x80
100
101	#define PCNET32_DMA_MASK 0xffffffff
102
103	/*
104	* table to translate option values from tulip
105	* to internal options
106	*/
107	static unsigned char options_mapping[] = {
108	PCNET32_PORT_ASEL, /* 0 Auto-select */
109	PCNET32_PORT_AUI, /* 1 BNC/AUI */
110	PCNET32_PORT_AUI, /* 2 AUI/BNC */
111	PCNET32_PORT_ASEL, /* 3 not supported */
112	PCNET32_PORT_10BT \| PCNET32_PORT_FD, /* 4 10baseT-FD */
113	PCNET32_PORT_ASEL, /* 5 not supported */
114	PCNET32_PORT_ASEL, /* 6 not supported */
115	PCNET32_PORT_ASEL, /* 7 not supported */
116	PCNET32_PORT_ASEL, /* 8 not supported */
117	PCNET32_PORT_MII, /* 9 MII 10baseT */
118	PCNET32_PORT_MII \| PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
119	PCNET32_PORT_MII, /* 11 MII (autosel) */
120	PCNET32_PORT_10BT, /* 12 10BaseT */
121	PCNET32_PORT_MII \| PCNET32_PORT_100, /* 13 MII 100BaseTx */
122	PCNET32_PORT_MII \| PCNET32_PORT_100 \| PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
123	PCNET32_PORT_ASEL /* 15 not supported */
124	};
125
126	#define MAX_UNITS 8 /* More are supported, limit only on options */
127	static int options[MAX_UNITS];
128	static int full_duplex[MAX_UNITS];
129
130	/*
131	* Theory of Operation
132	*
133	* This driver uses the same software structure as the normal lance
134	* driver. So look for a verbose description in lance.c. The differences
135	* to the normal lance driver is the use of the 32bit mode of PCnet32
136	* and PCnetPCI chips. Because these chips are 32bit chips, there is no
137	* 16MB limitation and we don't need bounce buffers.
138	*/
139
140
141
142	/*
143	* Set the number of Tx and Rx buffers, using Log_2(# buffers).
144	* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
145	* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
146	*/
147	#ifndef PCNET32_LOG_TX_BUFFERS
148	#define PCNET32_LOG_TX_BUFFERS 1
149	#define PCNET32_LOG_RX_BUFFERS 2
150	#endif
151
152	#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
153	#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
154	/* FIXME: Fix this to allow multiple tx_ring descriptors */
155	#define TX_RING_LEN_BITS 0x0000 /PCNET32_LOG_TX_BUFFERS) << 12) /
156
157	#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
158	#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
159	#define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
160
161	#define PKT_BUF_SZ 1544
162
163	/* Offsets from base I/O address. */
164	#define PCNET32_WIO_RDP 0x10
165	#define PCNET32_WIO_RAP 0x12
166	#define PCNET32_WIO_RESET 0x14
167	#define PCNET32_WIO_BDP 0x16
168
169	#define PCNET32_DWIO_RDP 0x10
170	#define PCNET32_DWIO_RAP 0x14
171	#define PCNET32_DWIO_RESET 0x18
172	#define PCNET32_DWIO_BDP 0x1C
173
174	#define PCNET32_TOTAL_SIZE 0x20
175
176	/* Buffers for the tx and Rx */
177
178	/* Create a static buffer of size PKT_BUF_SZ for each
179	TX Descriptor. All descriptors point to a
180	part of this buffer */
181	static unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
182	// __attribute__ ((aligned(16)));
183
184	/* Create a static buffer of size PKT_BUF_SZ for each
185	RX Descriptor All descriptors point to a
186	part of this buffer */
187	static unsigned char rxb[RX_RING_SIZE * PKT_BUF_SZ];
188	// __attribute__ ((aligned(16)));
189
190	/* The PCNET32 Rx and Tx ring descriptors. */
191	struct pcnet32_rx_head {
192	u32 base;
193	s16 buf_length;
194	s16 status;
195	u32 msg_length;
196	u32 reserved;
197	};
198
199	struct pcnet32_tx_head {
200	u32 base;
201	s16 length;
202	s16 status;
203	u32 misc;
204	u32 reserved;
205	};
206
207	/* The PCNET32 32-Bit initialization block, described in databook. */
208	struct pcnet32_init_block {
209	u16 mode;
210	u16 tlen_rlen;
211	u8 phys_addr[6];
212	u16 reserved;
213	u32 filter[2];
214	/* Receive and transmit ring base, along with extra bits. */
215	u32 rx_ring;
216	u32 tx_ring;
217	};
218	/* PCnet32 access functions */
219	struct pcnet32_access {
220	u16(*read_csr) (unsigned long, int);
221	void (*write_csr) (unsigned long, int, u16);
222	u16(*read_bcr) (unsigned long, int);
223	void (*write_bcr) (unsigned long, int, u16);
224	u16(*read_rap) (unsigned long);
225	void (*write_rap) (unsigned long, u16);
226	void (*reset) (unsigned long);
227	};
228
229	/* Define the TX Descriptor */
230	static struct pcnet32_tx_head tx_ring[TX_RING_SIZE]
231	__attribute__ ((aligned(16)));
232
233
234	/* Define the RX Descriptor */
235	static struct pcnet32_rx_head rx_ring[RX_RING_SIZE]
236	__attribute__ ((aligned(16)));
237
238	/* May need to be moved to mii.h */
239	struct mii_if_info {
240	int phy_id;
241	int advertising;
242	unsigned int full_duplex:1; /* is full duplex? */
243	};
244
245	/*
246	* The first three fields of pcnet32_private are read by the ethernet device
247	* so we allocate the structure should be allocated by pci_alloc_consistent().
248	*/
249	#define MII_CNT 4
250	struct pcnet32_private {
251	struct pcnet32_init_block init_block;
252	struct pci_dev pci_dev; / Pointer to the associated pci device structure */
253	const char *name;
254	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
255	struct sk_buff *tx_skbuff[TX_RING_SIZE];
256	struct sk_buff *rx_skbuff[RX_RING_SIZE];
257	struct pcnet32_access a;
258	unsigned int cur_rx, cur_tx; /* The next free ring entry */
259	char tx_full;
260	int options;
261	int shared_irq:1, /* shared irq possible */
262	ltint:1, /* enable TxDone-intr inhibitor */
263	dxsuflo:1, /* disable transmit stop on uflo */
264	mii:1; /* mii port available */
265	struct mii_if_info mii_if;
266	unsigned char phys[MII_CNT];
267	struct net_device *next;
268	int full_duplex:1;
269	} lpx;
270
271	static struct pcnet32_private *lp;
272
273	static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num);
274	#if 0
275	static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
276	int val);
277	#endif
278	enum pci_flags_bit {
279	PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
280	PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 =
281	0x10 << 2, PCI_ADDR3 = 0x10 << 3,
282	};
283
284
285	static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
286	{
287	outw(index, addr + PCNET32_WIO_RAP);
288	return inw(addr + PCNET32_WIO_RDP);
289	}
290
291	static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
292	{
293	outw(index, addr + PCNET32_WIO_RAP);
294	outw(val, addr + PCNET32_WIO_RDP);
295	}
296
297	static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
298	{
299	outw(index, addr + PCNET32_WIO_RAP);
300	return inw(addr + PCNET32_WIO_BDP);
301	}
302
303	static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
304	{
305	outw(index, addr + PCNET32_WIO_RAP);
306	outw(val, addr + PCNET32_WIO_BDP);
307	}
308
309	static u16 pcnet32_wio_read_rap(unsigned long addr)
310	{
311	return inw(addr + PCNET32_WIO_RAP);
312	}
313
314	static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
315	{
316	outw(val, addr + PCNET32_WIO_RAP);
317	}
318
319	static void pcnet32_wio_reset(unsigned long addr)
320	{
321	inw(addr + PCNET32_WIO_RESET);
322	}
323
324	static int pcnet32_wio_check(unsigned long addr)
325	{
326	outw(88, addr + PCNET32_WIO_RAP);
327	return (inw(addr + PCNET32_WIO_RAP) == 88);
328	}
329
330	static struct pcnet32_access pcnet32_wio = {
331	read_csr:pcnet32_wio_read_csr,
332	write_csr:pcnet32_wio_write_csr,
333	read_bcr:pcnet32_wio_read_bcr,
334	write_bcr:pcnet32_wio_write_bcr,
335	read_rap:pcnet32_wio_read_rap,
336	write_rap:pcnet32_wio_write_rap,
337	reset:pcnet32_wio_reset
338	};
339
340	static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
341	{
342	outl(index, addr + PCNET32_DWIO_RAP);
343	return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
344	}
345
346	static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
347	{
348	outl(index, addr + PCNET32_DWIO_RAP);
349	outl(val, addr + PCNET32_DWIO_RDP);
350	}
351
352	static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
353	{
354	outl(index, addr + PCNET32_DWIO_RAP);
355	return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
356	}
357
358	static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
359	{
360	outl(index, addr + PCNET32_DWIO_RAP);
361	outl(val, addr + PCNET32_DWIO_BDP);
362	}
363
364	static u16 pcnet32_dwio_read_rap(unsigned long addr)
365	{
366	return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
367	}
368
369	static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
370	{
371	outl(val, addr + PCNET32_DWIO_RAP);
372	}
373
374	static void pcnet32_dwio_reset(unsigned long addr)
375	{
376	inl(addr + PCNET32_DWIO_RESET);
377	}
378
379	static int pcnet32_dwio_check(unsigned long addr)
380	{
381	outl(88, addr + PCNET32_DWIO_RAP);
382	return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
383	}
384
385	static struct pcnet32_access pcnet32_dwio = {
386	read_csr:pcnet32_dwio_read_csr,
387	write_csr:pcnet32_dwio_write_csr,
388	read_bcr:pcnet32_dwio_read_bcr,
389	write_bcr:pcnet32_dwio_write_bcr,
390	read_rap:pcnet32_dwio_read_rap,
391	write_rap:pcnet32_dwio_write_rap,
392	reset:pcnet32_dwio_reset
393	};
394
395
396	/* Initialize the PCNET32 Rx and Tx rings. */
397	static int pcnet32_init_ring(struct nic *nic)
398	{
399	int i;
400
401	lp->tx_full = 0;
402	lp->cur_rx = lp->cur_tx = 0;
403
404	for (i = 0; i < RX_RING_SIZE; i++) {
405	rx_ring[i].base = (u32) virt_to_le32desc(&rxb[i * PKT_BUF_SZ]);
406	rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
407	rx_ring[i].status = le16_to_cpu(0x8000);
408	}
409
410	/* The Tx buffer address is filled in as needed, but we do need to clear
411	the upper ownership bit. */
412	for (i = 0; i < TX_RING_SIZE; i++) {
413	tx_ring[i].base = 0;
414	tx_ring[i].status = 0;
415	}
416
417
418	lp->init_block.tlen_rlen =
419	le16_to_cpu(TX_RING_LEN_BITS \| RX_RING_LEN_BITS);
420	for (i = 0; i < 6; i++)
421	lp->init_block.phys_addr[i] = nic->node_addr[i];
422	lp->init_block.rx_ring = (u32) virt_to_le32desc(&rx_ring[0]);
423	lp->init_block.tx_ring = (u32) virt_to_le32desc(&tx_ring[0]);
424	return 0;
425	}
426
427	/**************************************************************************
428	RESET - Reset adapter
429	***************************************************************************/
430	static void pcnet32_reset(struct nic *nic)
431	{
432	/* put the card in its initial state */
433	u16 val;
434	int i;
435
436	/* Reset the PCNET32 */
437	lp->a.reset(ioaddr);
438
439	/* switch pcnet32 to 32bit mode */
440	lp->a.write_bcr(ioaddr, 20, 2);
441
442	/* set/reset autoselect bit */
443	val = lp->a.read_bcr(ioaddr, 2) & ~2;
444	if (lp->options & PCNET32_PORT_ASEL)
445	val \|= 2;
446	lp->a.write_bcr(ioaddr, 2, val);
447
448	/* handle full duplex setting */
449	if (lp->full_duplex) {
450	val = lp->a.read_bcr(ioaddr, 9) & ~3;
451	if (lp->options & PCNET32_PORT_FD) {
452	val \|= 1;
453	if (lp->options ==
454	(PCNET32_PORT_FD \| PCNET32_PORT_AUI))
455	val \|= 2;
456	} else if (lp->options & PCNET32_PORT_ASEL) {
457	/* workaround of xSeries250, turn on for 79C975 only */
458	i = ((lp->a.
459	read_csr(ioaddr,
460	88) \| (lp->a.read_csr(ioaddr,
461	89) << 16)) >>
462	12) & 0xffff;
463	if (i == 0x2627)
464	val \|= 3;
465	}
466	lp->a.write_bcr(ioaddr, 9, val);
467	}
468
469	/* set/reset GPSI bit in test register */
470	val = lp->a.read_csr(ioaddr, 124) & ~0x10;
471	if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
472	val \|= 0x10;
473	lp->a.write_csr(ioaddr, 124, val);
474
475	if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
476	val = lp->a.read_bcr(ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
477	if (lp->options & PCNET32_PORT_FD)
478	val \|= 0x10;
479	if (lp->options & PCNET32_PORT_100)
480	val \|= 0x08;
481	lp->a.write_bcr(ioaddr, 32, val);
482	} else {
483	if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */
484	val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
485	val \|= 0x20;
486	lp->a.write_bcr(ioaddr, 32, val);
487	}
488	}
489
490	#ifdef DO_DXSUFLO
491	if (lp->dxsuflo) { /* Disable transmit stop on underflow */
492	val = lp->a.read_csr(ioaddr, 3);
493	val \|= 0x40;
494	lp->a.write_csr(ioaddr, 3, val);
495	}
496	#endif
497	if (1)
498	{
499	//disable interrupts
500	val = lp->a.read_csr(ioaddr, 3);
501	val = val
502	\| (1 << 14) //BABLM intr disabled
503	\| (1 << 12) //MISSM missed frame mask intr disabled
504	\| (1 << 10) //RINTM receive intr disabled
505	\| (1 << 9) //TINTM transmit intr disabled
506	\| (1 << 8) //IDONM init done intr disabled
507	;
508	lp->a.write_csr(ioaddr, 3, val);
509	}
510
511	if (lp->ltint) { /* Enable TxDone-intr inhibitor */
512	val = lp->a.read_csr(ioaddr, 5);
513	val \|= (1 << 14);
514	lp->a.write_csr(ioaddr, 5, val);
515	}
516	lp->init_block.mode =
517	le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
518	lp->init_block.filter[0] = 0xffffffff;
519	lp->init_block.filter[1] = 0xffffffff;
520
521	pcnet32_init_ring(nic);
522
523
524	/* Re-initialize the PCNET32, and start it when done. */
525	lp->a.write_csr(ioaddr, 1,
526	(virt_to_bus(&lp->init_block)) & 0xffff);
527	lp->a.write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
528	lp->a.write_csr(ioaddr, 4, 0x0915);
529	lp->a.write_csr(ioaddr, 0, 0x0001);
530
531
532	i = 0;
533	while (i++ < 100)
534	if (lp->a.read_csr(ioaddr, 0) & 0x0100)
535	break;
536	/*
537	* We used to clear the InitDone bit, 0x0100, here but Mark Stockton
538	* reports that doing so triggers a bug in the '974.
539	*/
540	lp->a.write_csr(ioaddr, 0, 0x0042);
541
542	dprintf(("pcnet32 open, csr0 %hX.\n", lp->a.read_csr(ioaddr, 0)));
543
544	}
545
546	/**************************************************************************
547	POLL - Wait for a frame
548	***************************************************************************/
549	static int pcnet32_poll(struct nic *nic __unused, int retrieve)
550	{
551	/* return true if there's an ethernet packet ready to read */
552	/* nic->packet should contain data on return */
553	/* nic->packetlen should contain length of data */
554
555	int status;
556	int entry;
557
558	#ifdef VBOX
559	/* Check if there is any interrupt pending. */
560	status = lp->a.read_csr(ioaddr, 0) & (1 << 7);
561	/** @todo the following line is a workaround for the pcnet device implementation in VBox, it unsets the INTR bit in CSR0 way too early for UINT. Remove when the pcnet device is fixed*/
562	status \|= lp->a.read_csr(ioaddr, 4) & (1 << 6);
563	/* Acknowledge all extended2 interrupts. */
564	lp->a.write_csr(ioaddr, 7, lp->a.read_csr(ioaddr, 7));
565	/* Acknowledge all extended interrupts. */
566	lp->a.write_csr(ioaddr, 5, lp->a.read_csr(ioaddr, 5));
567	/* Acknowledge all test and feature control interrupts (we use UINT). */
568	lp->a.write_csr(ioaddr, 4, lp->a.read_csr(ioaddr, 4));
569	/* Acknowledge all normal interrupts. */
570	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0));
571	if (status && !retrieve)
572	return 1;
573	#endif /* VBOX */
574
575	entry = lp->cur_rx & RX_RING_MOD_MASK;
576	status = ((short) le16_to_cpu(rx_ring[entry].status) >> 8);
577
578	#ifdef VBOX
579	if (status != 0x03)
580	#else /* !VBOX */
581	if (status < 0)
582	#endif /* !VBOX */
583	return 0;
584
585	if ( ! retrieve ) return 1;
586
587	if (status == 0x03) {
588	nic->packetlen =
589	(le32_to_cpu(rx_ring[entry].msg_length) & 0xfff) - 4;
590	memcpy(nic->packet, &rxb[entry * PKT_BUF_SZ], nic->packetlen);
591
592	/* Andrew Boyd of QNX reports that some revs of the 79C765
593	* clear the buffer length */
594	rx_ring[entry].buf_length = le16_to_cpu(-PKT_BUF_SZ);
595	rx_ring[entry].status \|= le16_to_cpu(0x8000); /* prime for next receive */
596	/* Switch to the next Rx ring buffer */
597	lp->cur_rx++;
598
599	} else {
600	return 0;
601	}
602
603	return 1;
604	}
605
606	/**************************************************************************
607	TRANSMIT - Transmit a frame
608	***************************************************************************/
609	static void pcnet32_transmit(struct nic nic __unused, const char d, /* Destination */
610	unsigned int t, /* Type */
611	unsigned int s, /* size */
612	const char *p)
613	{ /* Packet */
614	/* send the packet to destination */
615	unsigned long time;
616	u8 *ptxb;
617	u16 nstype;
618	u16 status;
619	int entry = 0; /lp->cur_tx & TX_RING_MOD_MASK; /
620
621	status = 0x8300;
622	/* point to the current txb incase multiple tx_rings are used */
623	ptxb = txb + (lp->cur_tx * PKT_BUF_SZ);
624
625	/* copy the packet to ring buffer */
626	memcpy(ptxb, d, ETH_ALEN); /* dst */
627	memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
628	nstype = htons((u16) t); /* type */
629	memcpy(ptxb + 2 * ETH_ALEN, (u8 ) & nstype, 2); / type */
630	memcpy(ptxb + ETH_HLEN, p, s);
631
632	s += ETH_HLEN;
633	while (s < ETH_ZLEN) /* pad to min length */
634	ptxb[s++] = '\0';
635
636	tx_ring[entry].length = le16_to_cpu(-s);
637	tx_ring[entry].misc = 0x00000000;
638	tx_ring[entry].base = (u32) virt_to_le32desc(ptxb);
639
640	/* we set the top byte as the very last thing */
641	tx_ring[entry].status = le16_to_cpu(status);
642
643
644	/* Trigger an immediate send poll */
645	lp->a.write_csr(ioaddr, 0, 0x0048);
646
647	/* wait for transmit complete */
648	lp->cur_tx = 0; /* (lp->cur_tx + 1); */
649	time = currticks() + TICKS_PER_SEC; /* wait one second */
650	while (currticks() < time &&
651	((short) le16_to_cpu(tx_ring[entry].status) < 0));
652
653	if ((short) le16_to_cpu(tx_ring[entry].status) < 0)
654	printf("PCNET32 timed out on transmit\n");
655
656	/* Stop pointing at the current txb
657	* otherwise the card continues to send the packet */
658	tx_ring[entry].base = 0;
659
660	}
661
662	/**************************************************************************
663	DISABLE - Turn off ethernet interface
664	***************************************************************************/
665	static void pcnet32_disable(struct dev *dev __unused)
666	{
667	/* Stop the PCNET32 here -- it ocassionally polls memory if we don't */
668	lp->a.write_csr(ioaddr, 0, 0x0004);
669
670	/*
671	* Switch back to 16-bit mode to avoid problems with dumb
672	* DOS packet driver after a warm reboot
673	*/
674	lp->a.write_bcr(ioaddr, 20, 0);
675	}
676
677	/**************************************************************************
678	IRQ - Enable, Disable, or Force interrupts
679	***************************************************************************/
680	#ifdef VBOX
681	static void pcnet32_irq(struct nic *nic __unused, irq_action_t action)
682	{
683	u16 val;
684	switch ( action ) {
685	case DISABLE :
686	val = lp->a.read_csr(ioaddr, 3);
687	val = val
688	\| (1 << 14) //BABLM intr disabled
689	\| (1 << 12) //MISSM missed frame mask intr disabled
690	\| (1 << 10) //RINTM receive intr disabled
691	\| (1 << 9) //TINTM transmit intr disabled
692	\| (1 << 8) //IDONM init done intr disabled
693	;
694	lp->a.write_csr(ioaddr, 3, val);
695	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0) & ~0x0040);
696	break;
697	case ENABLE :
698	val = lp->a.read_csr(ioaddr, 3);
699	val = val & ~(1 << 10); //RINTM receive intr enabled
700	lp->a.write_csr(ioaddr, 3, val);
701	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0) \| 0x0040);
702	break;
703	case FORCE :
704	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0) \| 0x0040);
705	lp->a.write_csr(ioaddr, 4, 1 << 7); /* Trigger a "UINT" = user interrupt */
706	break;
707	}
708	}
709	#else /* !VBOX */
710	static void pcnet32_irq(struct nic *nic __unused, irq_action_t action __unused)
711	{
712	switch ( action ) {
713	case DISABLE :
714	break;
715	case ENABLE :
716	break;
717	case FORCE :
718	break;
719	}
720	}
721	#endif /* VBOX */
722
723	/**************************************************************************
724	PROBE - Look for an adapter, this routine's visible to the outside
725	You should omit the last argument struct pci_device * for a non-PCI NIC
726	***************************************************************************/
727	static int pcnet32_probe(struct dev dev, struct pci_device pci)
728	{
729	struct nic nic = (struct nic ) dev;
730	int i, media;
731	int fdx, mii, fset, dxsuflo, ltint;
732	int chip_version;
733	char *chipname;
734	struct pcnet32_access *a = NULL;
735	u8 promaddr[6];
736
737	int shared = 1;
738	if (pci->ioaddr == 0)
739	return 0;
740
741	/* BASE is used throughout to address the card */
742	ioaddr = pci->ioaddr;
743	#ifndef VBOX
744	printf("pcnet32.c: Found %s, Vendor=0x%hX Device=0x%hX\n",
745	pci->name, pci->vendor, pci->dev_id);
746	#endif /* !VBOX */
747
748	#ifdef VBOX
749	nic->irqno = pci->irq;
750	#else /* !VBOX */
751	nic->irqno = 0;
752	#endif /* !VBOX */
753	nic->ioaddr = pci->ioaddr & ~3;
754
755	/* reset the chip */
756	pcnet32_wio_reset(ioaddr);
757
758	/* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
759	if (pcnet32_wio_read_csr(ioaddr, 0) == 4
760	&& pcnet32_wio_check(ioaddr)) {
761	a = &pcnet32_wio;
762	} else {
763	pcnet32_dwio_reset(ioaddr);
764	if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
765	&& pcnet32_dwio_check(ioaddr)) {
766	a = &pcnet32_dwio;
767	} else
768	return 0;
769	}
770
771	chip_version =
772	a->read_csr(ioaddr, 88) \| (a->read_csr(ioaddr, 89) << 16);
773
774	dprintf(("PCnet chip version is 0x%X\n", chip_version));
775	if ((chip_version & 0xfff) != 0x003)
776	return 0;
777
778	/* initialize variables */
779	fdx = mii = fset = dxsuflo = ltint = 0;
780	chip_version = (chip_version >> 12) & 0xffff;
781
782	switch (chip_version) {
783	case 0x2420:
784	chipname = "PCnet/PCI 79C970"; /* PCI */
785	break;
786	case 0x2430:
787	if (shared)
788	chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
789	else
790	chipname = "PCnet/32 79C965"; /* 486/VL bus */
791	break;
792	case 0x2621:
793	chipname = "PCnet/PCI II 79C970A"; /* PCI */
794	fdx = 1;
795	break;
796	case 0x2623:
797	chipname = "PCnet/FAST 79C971"; /* PCI */
798	fdx = 1;
799	mii = 1;
800	fset = 1;
801	ltint = 1;
802	break;
803	case 0x2624:
804	chipname = "PCnet/FAST+ 79C972"; /* PCI */
805	fdx = 1;
806	mii = 1;
807	fset = 1;
808	break;
809	case 0x2625:
810	chipname = "PCnet/FAST III 79C973"; /* PCI */
811	fdx = 1;
812	mii = 1;
813	break;
814	case 0x2626:
815	chipname = "PCnet/Home 79C978"; /* PCI */
816	fdx = 1;
817	/*
818	* This is based on specs published at www.amd.com. This section
819	* assumes that a card with a 79C978 wants to go into 1Mb HomePNA
820	* mode. The 79C978 can also go into standard ethernet, and there
821	* probably should be some sort of module option to select the
822	* mode by which the card should operate
823	*/
824	/* switch to home wiring mode */
825	media = a->read_bcr(ioaddr, 49);
826
827	printf("media reset to %#x.\n", media);
828	a->write_bcr(ioaddr, 49, media);
829	break;
830	case 0x2627:
831	chipname = "PCnet/FAST III 79C975"; /* PCI */
832	fdx = 1;
833	mii = 1;
834	break;
835	default:
836	chipname = "UNKNOWN";
837	printf("PCnet version %#x, no PCnet32 chip.\n",
838	chip_version);
839	return 0;
840	}
841
842	/*
843	* On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
844	* starting until the packet is loaded. Strike one for reliability, lose
845	* one for latency - although on PCI this isnt a big loss. Older chips
846	* have FIFO's smaller than a packet, so you can't do this.
847	*/
848
849	if (fset) {
850	a->write_bcr(ioaddr, 18,
851	(a->read_bcr(ioaddr, 18) \| 0x0800));
852	a->write_csr(ioaddr, 80,
853	(a->read_csr(ioaddr, 80) & 0x0C00) \| 0x0c00);
854	dxsuflo = 1;
855	ltint = 1;
856	}
857
858	dprintf(("%s at %hX,", chipname, ioaddr));
859
860	/* read PROM address */
861	for (i = 0; i < 6; i++)
862	promaddr[i] = inb(ioaddr + i);
863
864	/* Update the nic structure with the MAC Address */
865	for (i = 0; i < ETH_ALEN; i++) {
866	nic->node_addr[i] = promaddr[i];
867	}
868	#ifndef VBOX
869	/* Print out some hardware info */
870	printf("%s: %! at ioaddr 0x%hX, ", chipname, nic->node_addr,
871	ioaddr);
872	#endif /* VBOX */
873
874	/* Set to pci bus master */
875	adjust_pci_device(pci);
876
877	/* point to private storage */
878	lp = &lpx;
879
880	#if EBDEBUG
881	if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
882	i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
883	dprintf((" tx_start_pt(0x%hX):", i));
884	switch (i >> 10) {
885	case 0:
886	dprintf((" 20 bytes,"));
887	break;
888	case 1:
889	dprintf((" 64 bytes,"));
890	break;
891	case 2:
892	dprintf((" 128 bytes,"));
893	break;
894	case 3:
895	dprintf(("~220 bytes,"));
896	break;
897	}
898	i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
899	dprintf((" BCR18(%hX):", i & 0xffff));
900	if (i & (1 << 5))
901	dprintf(("BurstWrEn "));
902	if (i & (1 << 6))
903	dprintf(("BurstRdEn "));
904	if (i & (1 << 7))
905	dprintf(("DWordIO "));
906	if (i & (1 << 11))
907	dprintf(("NoUFlow "));
908	i = a->read_bcr(ioaddr, 25);
909	dprintf((" SRAMSIZE=0x%hX,", i << 8));
910	i = a->read_bcr(ioaddr, 26);
911	dprintf((" SRAM_BND=0x%hX,", i << 8));
912	i = a->read_bcr(ioaddr, 27);
913	if (i & (1 << 14))
914	dprintf(("LowLatRx"));
915	}
916	#endif
917	lp->name = chipname;
918	lp->shared_irq = shared;
919	lp->full_duplex = fdx;
920	lp->dxsuflo = dxsuflo;
921	lp->ltint = ltint;
922	lp->mii = mii;
923	/* FIXME: Fix Options for only one card */
924	if ((cards_found >= MAX_UNITS)
925	\|\| ((unsigned int) options[cards_found] > sizeof(options_mapping)))
926	lp->options = PCNET32_PORT_ASEL;
927	else
928	lp->options = options_mapping[options[cards_found]];
929
930	if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
931	((cards_found >= MAX_UNITS) \|\| full_duplex[cards_found]))
932	lp->options \|= PCNET32_PORT_FD;
933
934	if (!a) {
935	printf("No access methods\n");
936	return 0;
937	}
938	lp->a = *a;
939
940	/* detect special T1/E1 WAN card by checking for MAC address */
941	if (nic->node_addr[0] == 0x00 && nic->node_addr[1] == 0xe0
942	&& nic->node_addr[2] == 0x75)
943	lp->options = PCNET32_PORT_FD \| PCNET32_PORT_GPSI;
944
945	lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
946	lp->init_block.tlen_rlen =
947	le16_to_cpu(TX_RING_LEN_BITS \| RX_RING_LEN_BITS);
948	for (i = 0; i < 6; i++)
949	lp->init_block.phys_addr[i] = nic->node_addr[i];
950	lp->init_block.filter[0] = 0xffffffff;
951	lp->init_block.filter[1] = 0xffffffff;
952	lp->init_block.rx_ring = virt_to_bus(&rx_ring);
953	lp->init_block.tx_ring = virt_to_bus(&tx_ring);
954
955	/* switch pcnet32 to 32bit mode */
956	a->write_bcr(ioaddr, 20, 2);
957
958	a->write_csr(ioaddr, 1, (virt_to_bus(&lp->init_block)) & 0xffff);
959	a->write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
960
961	/*
962	* To auto-IRQ we enable the initialization-done and DMA error
963	* interrupts. For ISA boards we get a DMA error, but VLB and PCI
964	* boards will work.
965	*/
966	/* Trigger an initialization just for the interrupt. */
967
968
969	// a->write_csr(ioaddr, 0, 0x41);
970	// mdelay(1);
971
972	cards_found++;
973
974	/* point to NIC specific routines */
975	pcnet32_reset(nic);
976	if (mii) {
977	int tmp;
978	int phy, phy_idx = 0;
979	u16 mii_lpa;
980	lp->phys[0] = 1; /* Default Setting */
981	#ifdef VBOX
982	for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
983	#else /* !VBOX */
984	for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
985	#endif /* !VBOX */
986	int mii_status = mdio_read(nic, phy, MII_BMSR);
987	if (mii_status != 0xffff && mii_status != 0x0000) {
988	lp->phys[phy_idx++] = phy;
989	lp->mii_if.advertising =
990	mdio_read(nic, phy, MII_ADVERTISE);
991	if ((mii_status & 0x0040) == 0) {
992	tmp = phy;
993	dprintf (("MII PHY found at address %d, status "
994	"%hX advertising %hX\n", phy, mii_status,
995	lp->mii_if.advertising));
996	}
997	}
998	}
999	if (phy_idx == 0)
1000	printf("No MII transceiver found!\n");
1001	lp->mii_if.phy_id = lp->phys[0];
1002
1003	lp->mii_if.advertising =
1004	mdio_read(nic, lp->phys[0], MII_ADVERTISE);
1005
1006	mii_lpa = mdio_read(nic, lp->phys[0], MII_LPA);
1007	lp->mii_if.advertising &= mii_lpa;
1008	#ifndef VBOX
1009	if (lp->mii_if.advertising & ADVERTISE_100FULL)
1010	printf("100Mbps Full-Duplex\n");
1011	else if (lp->mii_if.advertising & ADVERTISE_100HALF)
1012	printf("100Mbps Half-Duplex\n");
1013	else if (lp->mii_if.advertising & ADVERTISE_10FULL)
1014	printf("10Mbps Full-Duplex\n");
1015	else if (lp->mii_if.advertising & ADVERTISE_10HALF)
1016	printf("10Mbps Half-Duplex\n");
1017	else
1018	printf("No Link?\n");
1019	#endif /* !VBOX */
1020	} else {
1021	/* The older chips are fixed 10Mbps, and some support full duplex,
1022	* although not via autonegotiation, but only via configuration. */
1023	#ifndef VBOX
1024	if (fdx)
1025	printf("10Mbps Full-Duplex\n");
1026	else
1027	printf("10Mbps Half-Duplex\n");
1028	#endif /* !VBOX */
1029	}
1030
1031	nic->poll = pcnet32_poll;
1032	nic->transmit = pcnet32_transmit;
1033	dev->disable = pcnet32_disable;
1034	nic->irq = pcnet32_irq;
1035
1036	return 1;
1037	}
1038	static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num)
1039	{
1040	u16 val_out;
1041	int phyaddr;
1042
1043	if (!lp->mii)
1044	return 0;
1045
1046	phyaddr = lp->a.read_bcr(ioaddr, 33);
1047
1048	lp->a.write_bcr(ioaddr, 33,
1049	((phy_id & 0x1f) << 5) \| (reg_num & 0x1f));
1050	val_out = lp->a.read_bcr(ioaddr, 34);
1051	lp->a.write_bcr(ioaddr, 33, phyaddr);
1052
1053	return val_out;
1054	}
1055
1056	#if 0
1057	static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
1058	int val)
1059	{
1060	int phyaddr;
1061
1062	if (!lp->mii)
1063	return;
1064
1065	phyaddr = lp->a.read_bcr(ioaddr, 33);
1066
1067	lp->a.write_bcr(ioaddr, 33,
1068	((phy_id & 0x1f) << 5) \| (reg_num & 0x1f));
1069	lp->a.write_bcr(ioaddr, 34, val);
1070	lp->a.write_bcr(ioaddr, 33, phyaddr);
1071	}
1072	#endif
1073
1074	static struct pci_id pcnet32_nics[] = {
1075	PCI_ROM(0x1022, 0x2000, "pcnet32", "AMD PCnet/PCI"),
1076	PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD PCNet FAST III"),
1077	PCI_ROM(0x1022, 0x2001, "amdhomepna", "AMD PCnet/HomePNA"),
1078	};
1079
1080	static struct pci_driver pcnet32_driver __pci_driver = {
1081	.type = NIC_DRIVER,
1082	.name = "PCNET32/PCI",
1083	.probe = pcnet32_probe,
1084	.ids = pcnet32_nics,
1085	.id_count = sizeof(pcnet32_nics) / sizeof(pcnet32_nics[0]),
1086	.class = 0,
1087	};

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/pcnet32.c@ 3542

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