| 1 | #ifndef PCI_H
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| 2 | #define PCI_H
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| 3 |
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| 4 | /*
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| 5 | ** Support for NE2000 PCI clones added David Monro June 1997
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| 6 | ** Generalised for other PCI NICs by Ken Yap July 1997
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| 7 | **
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| 8 | ** Most of this is taken from:
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| 9 | **
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| 10 | ** /usr/src/linux/drivers/pci/pci.c
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| 11 | ** /usr/src/linux/include/linux/pci.h
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| 12 | ** /usr/src/linux/arch/i386/bios32.c
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| 13 | ** /usr/src/linux/include/linux/bios32.h
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| 14 | ** /usr/src/linux/drivers/net/ne.c
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| 15 | */
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| 16 |
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| 17 | /*
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| 18 | * This program is free software; you can redistribute it and/or
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| 19 | * modify it under the terms of the GNU General Public License as
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| 20 | * published by the Free Software Foundation; either version 2, or (at
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| 21 | * your option) any later version.
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| 22 | */
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| 23 |
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| 24 | /*
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| 25 | * Sun GPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 26 | * other than GPL or LGPL is available it will apply instead, Sun elects to use only
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| 27 | * the General Public License version 2 (GPLv2) at this time for any software where
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| 28 | * a choice of GPL license versions is made available with the language indicating
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| 29 | * that GPLv2 or any later version may be used, or where a choice of which version
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| 30 | * of the GPL is applied is otherwise unspecified.
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| 31 | */
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| 32 |
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| 33 | #include "pci_ids.h"
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| 34 |
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| 35 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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| 36 | #define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */
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| 37 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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| 38 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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| 39 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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| 40 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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| 41 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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| 42 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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| 43 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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| 44 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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| 45 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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| 46 |
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| 47 | #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
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| 48 | #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
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| 49 | #define PCIBIOS_FIND_PCI_DEVICE 0xb102
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| 50 | #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
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| 51 | #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
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| 52 | #define PCIBIOS_READ_CONFIG_BYTE 0xb108
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| 53 | #define PCIBIOS_READ_CONFIG_WORD 0xb109
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| 54 | #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
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| 55 | #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
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| 56 | #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
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| 57 | #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
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| 58 |
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| 59 | #define PCI_VENDOR_ID 0x00 /* 16 bits */
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| 60 | #define PCI_DEVICE_ID 0x02 /* 16 bits */
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| 61 | #define PCI_COMMAND 0x04 /* 16 bits */
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| 62 |
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| 63 | #define PCI_STATUS 0x06 /* 16 bits */
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| 64 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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| 65 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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| 66 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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| 67 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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| 68 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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| 69 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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| 70 | #define PCI_STATUS_DEVSEL_FAST 0x000
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| 71 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200
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| 72 | #define PCI_STATUS_DEVSEL_SLOW 0x400
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| 73 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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| 74 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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| 75 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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| 76 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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| 77 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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| 78 |
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| 79 | #define PCI_REVISION 0x08 /* 8 bits */
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| 80 | #define PCI_REVISION_ID 0x08 /* 8 bits */
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| 81 | #define PCI_CLASS_REVISION 0x08 /* 32 bits */
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| 82 | #define PCI_CLASS_CODE 0x0b /* 8 bits */
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| 83 | #define PCI_SUBCLASS_CODE 0x0a /* 8 bits */
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| 84 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */
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| 85 | #define PCI_HEADER_TYPE_NORMAL 0
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| 86 | #define PCI_HEADER_TYPE_BRIDGE 1
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| 87 | #define PCI_HEADER_TYPE_CARDBUS 2
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| 88 |
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| 89 |
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| 90 | /* Header type 0 (normal devices) */
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| 91 | #define PCI_CARDBUS_CIS 0x28
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| 92 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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| 93 | #define PCI_SUBSYSTEM_ID 0x2e
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| 94 |
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| 95 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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| 96 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
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| 97 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
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| 98 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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| 99 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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| 100 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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| 101 |
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| 102 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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| 103 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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| 104 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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| 105 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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| 106 |
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| 107 | #ifndef PCI_BASE_ADDRESS_IO_MASK
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| 108 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03)
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| 109 | #endif
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| 110 | #ifndef PCI_BASE_ADDRESS_MEM_MASK
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| 111 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
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| 112 | #endif
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| 113 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01
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| 114 | #define PCI_ROM_ADDRESS 0x30 /* 32 bits */
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| 115 | #define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM,
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| 116 | bits 31..11 are address,
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| 117 | 10..2 are reserved */
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| 118 |
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| 119 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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| 120 |
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| 121 | #define PCI_INTERRUPT_LINE 0x3c /* IRQ number (0-15) */
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| 122 | #define PCI_INTERRUPT_PIN 0x3d /* IRQ pin on PCI bus (A-D) */
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| 123 |
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| 124 | /* Header type 1 (PCI-to-PCI bridges) */
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| 125 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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| 126 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
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| 127 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
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| 128 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
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| 129 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
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| 130 | #define PCI_IO_LIMIT 0x1d
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| 131 | #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
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| 132 | #define PCI_IO_RANGE_TYPE_16 0x00
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| 133 | #define PCI_IO_RANGE_TYPE_32 0x01
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| 134 | #define PCI_IO_RANGE_MASK ~0x0f
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| 135 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
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| 136 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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| 137 | #define PCI_MEMORY_LIMIT 0x22
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| 138 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
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| 139 | #define PCI_MEMORY_RANGE_MASK ~0x0f
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| 140 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
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| 141 | #define PCI_PREF_MEMORY_LIMIT 0x26
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| 142 | #define PCI_PREF_RANGE_TYPE_MASK 0x0f
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| 143 | #define PCI_PREF_RANGE_TYPE_32 0x00
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| 144 | #define PCI_PREF_RANGE_TYPE_64 0x01
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| 145 | #define PCI_PREF_RANGE_MASK ~0x0f
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| 146 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
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| 147 | #define PCI_PREF_LIMIT_UPPER32 0x2c
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| 148 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
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| 149 | #define PCI_IO_LIMIT_UPPER16 0x32
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| 150 | /* 0x34 same as for htype 0 */
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| 151 | /* 0x35-0x3b is reserved */
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| 152 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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| 153 | /* 0x3c-0x3d are same as for htype 0 */
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| 154 | #define PCI_BRIDGE_CONTROL 0x3e
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| 155 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
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| 156 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
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| 157 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
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| 158 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
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| 159 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
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| 160 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
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| 161 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
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| 162 |
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| 163 | #define PCI_CB_CAPABILITY_LIST 0x14
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| 164 |
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| 165 | /* Capability lists */
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| 166 |
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| 167 | #define PCI_CAP_LIST_ID 0 /* Capability ID */
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| 168 | #define PCI_CAP_ID_PM 0x01 /* Power Management */
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| 169 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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| 170 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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| 171 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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| 172 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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| 173 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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| 174 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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| 175 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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| 176 | #define PCI_CAP_SIZEOF 4
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| 177 |
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| 178 | /* Power Management Registers */
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| 179 |
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| 180 | #define PCI_PM_PMC 2 /* PM Capabilities Register */
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| 181 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
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| 182 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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| 183 | #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
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| 184 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
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| 185 | #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
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| 186 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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| 187 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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| 188 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
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| 189 | #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
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| 190 | #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
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| 191 | #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
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| 192 | #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
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| 193 | #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
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| 194 | #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
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| 195 | #define PCI_PM_CTRL 4 /* PM control and status register */
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| 196 | #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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| 197 | #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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| 198 | #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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| 199 | #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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| 200 | #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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| 201 | #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
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| 202 | #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
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| 203 | #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
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| 204 | #define PCI_PM_DATA_REGISTER 7 /* (??) */
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| 205 | #define PCI_PM_SIZEOF 8
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| 206 |
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| 207 | /* AGP registers */
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| 208 |
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| 209 | #define PCI_AGP_VERSION 2 /* BCD version number */
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| 210 | #define PCI_AGP_RFU 3 /* Rest of capability flags */
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| 211 | #define PCI_AGP_STATUS 4 /* Status register */
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| 212 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
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| 213 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
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| 214 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
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| 215 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
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| 216 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
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| 217 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
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| 218 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
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| 219 | #define PCI_AGP_COMMAND 8 /* Control register */
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| 220 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
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| 221 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
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| 222 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
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| 223 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
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| 224 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
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| 225 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
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| 226 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
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| 227 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
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| 228 | #define PCI_AGP_SIZEOF 12
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| 229 |
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| 230 | /* Slot Identification */
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| 231 |
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| 232 | #define PCI_SID_ESR 2 /* Expansion Slot Register */
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| 233 | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
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| 234 | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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| 235 | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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| 236 |
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| 237 | /* Message Signalled Interrupts registers */
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| 238 |
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| 239 | #define PCI_MSI_FLAGS 2 /* Various flags */
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| 240 | #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
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| 241 | #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
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| 242 | #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
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| 243 | #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
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| 244 | #define PCI_MSI_RFU 3 /* Rest of capability flags */
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| 245 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
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| 246 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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| 247 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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| 248 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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| 249 |
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| 250 | #define PCI_SLOT(devfn) ((devfn) >> 3)
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| 251 | #define PCI_FUNC(devfn) ((devfn) & 0x07)
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| 252 |
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| 253 | #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
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| 254 |
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| 255 | /* PCI signature: "PCI " */
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| 256 | #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
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| 257 |
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| 258 | /* PCI service signature: "$PCI" */
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| 259 | #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
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| 260 |
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| 261 | union bios32 {
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| 262 | struct {
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| 263 | unsigned long signature; /* _32_ */
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| 264 | unsigned long entry; /* 32 bit physical address */
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| 265 | unsigned char revision; /* Revision level, 0 */
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| 266 | unsigned char length; /* Length in paragraphs should be 01 */
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| 267 | unsigned char checksum; /* All bytes must add up to zero */
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| 268 | unsigned char reserved[5]; /* Must be zero */
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| 269 | } fields;
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| 270 | char chars[16];
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| 271 | };
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| 272 |
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| 273 | struct pci_device;
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| 274 | struct dev;
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| 275 | typedef int (*pci_probe_t)(struct dev *, struct pci_device *);
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| 276 |
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| 277 | struct pci_device {
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| 278 | uint32_t class;
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| 279 | uint16_t vendor, dev_id;
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| 280 | const char *name;
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| 281 | /* membase and ioaddr are silly and depricated */
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| 282 | unsigned int membase;
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| 283 | unsigned int ioaddr;
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| 284 | unsigned int romaddr;
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| 285 | unsigned char irq;
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| 286 | unsigned char devfn;
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| 287 | unsigned char bus;
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| 288 | unsigned char use_specified;
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| 289 | const struct pci_driver *driver;
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| 290 | };
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| 291 |
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| 292 | extern void scan_pci_bus(int type, struct pci_device *dev);
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| 293 | extern void find_pci(int type, struct pci_device *dev);
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| 294 |
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| 295 | extern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t *value);
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| 296 | extern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t value);
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| 297 | extern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t *value);
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| 298 | extern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t value);
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| 299 | extern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t *value);
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| 300 | extern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t value);
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| 301 | extern unsigned long pcibios_bus_base(unsigned int bus);
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| 302 | extern void adjust_pci_device(struct pci_device *p);
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| 303 |
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| 304 |
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| 305 | static inline int
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| 306 | pci_read_config_byte(struct pci_device *dev, unsigned int where, uint8_t *value)
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| 307 | {
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| 308 | return pcibios_read_config_byte(dev->bus, dev->devfn, where, value);
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| 309 | }
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| 310 | static inline int
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| 311 | pci_write_config_byte(struct pci_device *dev, unsigned int where, uint8_t value)
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| 312 | {
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| 313 | return pcibios_write_config_byte(dev->bus, dev->devfn, where, value);
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| 314 | }
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| 315 | static inline int
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| 316 | pci_read_config_word(struct pci_device *dev, unsigned int where, uint16_t *value)
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| 317 | {
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| 318 | return pcibios_read_config_word(dev->bus, dev->devfn, where, value);
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| 319 | }
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| 320 | static inline int
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| 321 | pci_write_config_word(struct pci_device *dev, unsigned int where, uint16_t value)
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| 322 | {
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| 323 | return pcibios_write_config_word(dev->bus, dev->devfn, where, value);
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| 324 | }
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| 325 | static inline int
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| 326 | pci_read_config_dword(struct pci_device *dev, unsigned int where, uint32_t *value)
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| 327 | {
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| 328 | return pcibios_read_config_dword(dev->bus, dev->devfn, where, value);
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| 329 | }
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| 330 | static inline int
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| 331 | pci_write_config_dword(struct pci_device *dev, unsigned int where, uint32_t value)
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| 332 | {
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| 333 | return pcibios_write_config_dword(dev->bus, dev->devfn, where, value);
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| 334 | }
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| 335 |
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| 336 | /* Helper functions to find the size of a pci bar */
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| 337 | extern unsigned long pci_bar_start(struct pci_device *dev, unsigned int bar);
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| 338 | extern unsigned long pci_bar_size(struct pci_device *dev, unsigned int bar);
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| 339 | /* Helper function to find pci capabilities */
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| 340 | extern int pci_find_capability(struct pci_device *dev, int cap);
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| 341 | struct pci_id {
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| 342 | unsigned short vendor, dev_id;
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| 343 | const char *name;
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| 344 | };
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| 345 |
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| 346 | struct dev;
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| 347 | /* Most pci drivers will use this */
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| 348 | struct pci_driver {
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| 349 | int type;
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| 350 | const char *name;
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| 351 | pci_probe_t probe;
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| 352 | struct pci_id *ids;
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| 353 | int id_count;
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| 354 |
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| 355 | /* On a few occasions the hardware is standardized enough that
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| 356 | * we only need to know the class of the device and not the exact
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| 357 | * type to drive the device correctly. If this is the case
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| 358 | * set a class value other than 0.
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| 359 | */
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| 360 | unsigned short class;
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| 361 | };
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| 362 |
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| 363 | #define __pci_driver __attribute__ ((used,__section__(".drivers.pci")))
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| 364 | /* Defined by the linker... */
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| 365 | extern const struct pci_driver pci_drivers[];
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| 366 | extern const struct pci_driver pci_drivers_end[];
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| 367 |
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| 368 | #define PCI_ROM(VENDOR_ID, DEVICE_ID, IMAGE, DESCRIPTION) \
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| 369 | { VENDOR_ID, DEVICE_ID, IMAGE, }
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| 370 |
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| 371 | #endif /* PCI_H */
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