| 1 | /*
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| 2 | * Copyright 2011-2023 The OpenSSL Project Authors. All Rights Reserved.
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| 3 | *
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| 4 | * Licensed under the Apache License 2.0 (the "License"). You may not use
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| 5 | * this file except in compliance with the License. You can obtain a copy
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| 6 | * in the file LICENSE in the source distribution or at
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| 7 | * https://www.openssl.org/source/license.html
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| 8 | */
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| 9 |
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| 10 | #ifndef OSSL_CRYPTO_ARM_ARCH_H
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| 11 | # define OSSL_CRYPTO_ARM_ARCH_H
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| 12 |
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| 13 | # if !defined(__ARM_ARCH__)
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| 14 | # if defined(__CC_ARM)
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| 15 | # define __ARM_ARCH__ __TARGET_ARCH_ARM
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| 16 | # if defined(__BIG_ENDIAN)
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| 17 | # define __ARMEB__
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| 18 | # else
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| 19 | # define __ARMEL__
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| 20 | # endif
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| 21 | # elif defined(__GNUC__)
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| 22 | # if defined(__aarch64__)
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| 23 | # define __ARM_ARCH__ 8
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| 24 | /*
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| 25 | * Why doesn't gcc define __ARM_ARCH__? Instead it defines
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| 26 | * bunch of below macros. See all_architectures[] table in
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| 27 | * gcc/config/arm/arm.c. On a side note it defines
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| 28 | * __ARMEL__/__ARMEB__ for little-/big-endian.
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| 29 | */
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| 30 | # elif defined(__ARM_ARCH)
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| 31 | # define __ARM_ARCH__ __ARM_ARCH
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| 32 | # elif defined(__ARM_ARCH_8A__)
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| 33 | # define __ARM_ARCH__ 8
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| 34 | # elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \
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| 35 | defined(__ARM_ARCH_7R__)|| defined(__ARM_ARCH_7M__) || \
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| 36 | defined(__ARM_ARCH_7EM__)
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| 37 | # define __ARM_ARCH__ 7
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| 38 | # elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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| 39 | defined(__ARM_ARCH_6K__)|| defined(__ARM_ARCH_6M__) || \
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| 40 | defined(__ARM_ARCH_6Z__)|| defined(__ARM_ARCH_6ZK__) || \
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| 41 | defined(__ARM_ARCH_6T2__)
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| 42 | # define __ARM_ARCH__ 6
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| 43 | # elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) || \
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| 44 | defined(__ARM_ARCH_5E__)|| defined(__ARM_ARCH_5TE__) || \
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| 45 | defined(__ARM_ARCH_5TEJ__)
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| 46 | # define __ARM_ARCH__ 5
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| 47 | # elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
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| 48 | # define __ARM_ARCH__ 4
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| 49 | # else
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| 50 | # error "unsupported ARM architecture"
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| 51 | # endif
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| 52 | # endif
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| 53 | # endif
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| 54 |
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| 55 | # if !defined(__ARM_MAX_ARCH__)
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| 56 | # define __ARM_MAX_ARCH__ __ARM_ARCH__
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| 57 | # endif
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| 58 |
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| 59 | # if __ARM_MAX_ARCH__<__ARM_ARCH__
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| 60 | # error "__ARM_MAX_ARCH__ can't be less than __ARM_ARCH__"
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| 61 | # elif __ARM_MAX_ARCH__!=__ARM_ARCH__
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| 62 | # if __ARM_ARCH__<7 && __ARM_MAX_ARCH__>=7 && defined(__ARMEB__)
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| 63 | # error "can't build universal big-endian binary"
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| 64 | # endif
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| 65 | # endif
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| 66 |
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| 67 | # ifndef __ASSEMBLER__
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| 68 | extern unsigned int OPENSSL_armcap_P;
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| 69 | extern unsigned int OPENSSL_arm_midr;
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| 70 | extern unsigned int OPENSSL_armv8_rsa_neonized;
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| 71 | # endif
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| 72 |
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| 73 | # define ARMV7_NEON (1<<0)
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| 74 | # define ARMV7_TICK (1<<1)
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| 75 | # define ARMV8_AES (1<<2)
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| 76 | # define ARMV8_SHA1 (1<<3)
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| 77 | # define ARMV8_SHA256 (1<<4)
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| 78 | # define ARMV8_PMULL (1<<5)
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| 79 | # define ARMV8_SHA512 (1<<6)
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| 80 | # define ARMV8_CPUID (1<<7)
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| 81 | # define ARMV8_RNG (1<<8)
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| 82 | # define ARMV8_SM3 (1<<9)
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| 83 | # define ARMV8_SM4 (1<<10)
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| 84 | # define ARMV8_SHA3 (1<<11)
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| 85 | # define ARMV8_UNROLL8_EOR3 (1<<12)
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| 86 | # define ARMV8_SVE (1<<13)
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| 87 | # define ARMV8_SVE2 (1<<14)
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| 88 |
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| 89 | /*
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| 90 | * MIDR_EL1 system register
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| 91 | *
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| 92 | * 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
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| 93 | * | | | | | | |
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| 94 | * |RES0 | Implementer | Variant | Arch | PartNum |Revision|
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| 95 | * |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
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| 96 | *
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| 97 | */
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| 98 |
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| 99 | # define ARM_CPU_IMP_ARM 0x41
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| 100 |
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| 101 | # define ARM_CPU_PART_CORTEX_A72 0xD08
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| 102 | # define ARM_CPU_PART_N1 0xD0C
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| 103 | # define ARM_CPU_PART_V1 0xD40
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| 104 | # define ARM_CPU_PART_N2 0xD49
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| 105 | # define ARM_CPU_PART_V2 0xD4F
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| 106 |
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| 107 | # define MIDR_PARTNUM_SHIFT 4
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| 108 | # define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
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| 109 | # define MIDR_PARTNUM(midr) \
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| 110 | (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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| 111 |
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| 112 | # define MIDR_IMPLEMENTER_SHIFT 24
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| 113 | # define MIDR_IMPLEMENTER_MASK (0xffU << MIDR_IMPLEMENTER_SHIFT)
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| 114 | # define MIDR_IMPLEMENTER(midr) \
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| 115 | (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
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| 116 |
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| 117 | # define MIDR_ARCHITECTURE_SHIFT 16
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| 118 | # define MIDR_ARCHITECTURE_MASK (0xfU << MIDR_ARCHITECTURE_SHIFT)
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| 119 | # define MIDR_ARCHITECTURE(midr) \
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| 120 | (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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| 121 |
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| 122 | # define MIDR_CPU_MODEL_MASK \
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| 123 | (MIDR_IMPLEMENTER_MASK | \
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| 124 | MIDR_PARTNUM_MASK | \
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| 125 | MIDR_ARCHITECTURE_MASK)
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| 126 |
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| 127 | # define MIDR_CPU_MODEL(imp, partnum) \
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| 128 | (((imp) << MIDR_IMPLEMENTER_SHIFT) | \
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| 129 | (0xfU << MIDR_ARCHITECTURE_SHIFT) | \
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| 130 | ((partnum) << MIDR_PARTNUM_SHIFT))
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| 131 |
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| 132 | # define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
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| 133 | (((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
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| 134 |
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| 135 | #if defined(__ASSEMBLER__)
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| 136 |
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| 137 | /*
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| 138 | * Support macros for
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| 139 | * - Armv8.3-A Pointer Authentication and
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| 140 | * - Armv8.5-A Branch Target Identification
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| 141 | * features which require emitting a .note.gnu.property section with the
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| 142 | * appropriate architecture-dependent feature bits set.
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| 143 | * Read more: "ELF for the Arm® 64-bit Architecture"
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| 144 | */
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| 145 |
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| 146 | # if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1
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| 147 | # define GNU_PROPERTY_AARCH64_BTI (1 << 0) /* Has Branch Target Identification */
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| 148 | # define AARCH64_VALID_CALL_TARGET hint #34 /* BTI 'c' */
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| 149 | # else
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| 150 | # define GNU_PROPERTY_AARCH64_BTI 0 /* No Branch Target Identification */
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| 151 | # define AARCH64_VALID_CALL_TARGET
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| 152 | # endif
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| 153 |
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| 154 | # if defined(__ARM_FEATURE_PAC_DEFAULT) && \
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| 155 | (__ARM_FEATURE_PAC_DEFAULT & 1) == 1 /* Signed with A-key */
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| 156 | # define GNU_PROPERTY_AARCH64_POINTER_AUTH \
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| 157 | (1 << 1) /* Has Pointer Authentication */
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| 158 | # define AARCH64_SIGN_LINK_REGISTER hint #25 /* PACIASP */
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| 159 | # define AARCH64_VALIDATE_LINK_REGISTER hint #29 /* AUTIASP */
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| 160 | # elif defined(__ARM_FEATURE_PAC_DEFAULT) && \
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| 161 | (__ARM_FEATURE_PAC_DEFAULT & 2) == 2 /* Signed with B-key */
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| 162 | # define GNU_PROPERTY_AARCH64_POINTER_AUTH \
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| 163 | (1 << 1) /* Has Pointer Authentication */
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| 164 | # define AARCH64_SIGN_LINK_REGISTER hint #27 /* PACIBSP */
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| 165 | # define AARCH64_VALIDATE_LINK_REGISTER hint #31 /* AUTIBSP */
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| 166 | # else
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| 167 | # define GNU_PROPERTY_AARCH64_POINTER_AUTH 0 /* No Pointer Authentication */
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| 168 | # if GNU_PROPERTY_AARCH64_BTI != 0
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| 169 | # define AARCH64_SIGN_LINK_REGISTER AARCH64_VALID_CALL_TARGET
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| 170 | # else
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| 171 | # define AARCH64_SIGN_LINK_REGISTER
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| 172 | # endif
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| 173 | # define AARCH64_VALIDATE_LINK_REGISTER
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| 174 | # endif
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| 175 |
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| 176 | # if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
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| 177 | .pushsection .note.gnu.property, "a";
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| 178 | .balign 8;
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| 179 | .long 4;
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| 180 | .long 0x10;
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| 181 | .long 0x5;
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| 182 | .asciz "GNU";
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| 183 | .long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
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| 184 | .long 4;
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| 185 | .long (GNU_PROPERTY_AARCH64_POINTER_AUTH | GNU_PROPERTY_AARCH64_BTI);
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| 186 | .long 0;
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| 187 | .popsection;
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| 188 | # endif
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| 189 |
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| 190 | # endif /* defined __ASSEMBLER__ */
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| 191 |
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| 192 | # define IS_CPU_SUPPORT_UNROLL8_EOR3() \
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| 193 | (OPENSSL_armcap_P & ARMV8_UNROLL8_EOR3)
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| 194 |
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| 195 | #endif
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