VirtualBox

source: vbox/trunk/src/recompiler/cpu-all.h@ 3613

最後變更 在這個檔案從3613是 2422,由 vboxsync 提交於 18 年 前

Removed the old recompiler code.
  • 屬性 svn:eol-style 設為 native
檔案大小: 31.8 KB
行 
1/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef CPU_ALL_H
21#define CPU_ALL_H
22
23#ifdef VBOX
24# ifndef LOG_GROUP
25# include <VBox/log.h>
26# define LOG_GROUP LOG_GROUP_REM
27# endif
28# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
29#endif
30
31#if defined(__arm__) || defined(__sparc__)
32#define WORDS_ALIGNED
33#endif
34
35/* some important defines:
36 *
37 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
38 * memory accesses.
39 *
40 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
41 * otherwise little endian.
42 *
43 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
44 *
45 * TARGET_WORDS_BIGENDIAN : same for target cpu
46 */
47
48#include "bswap.h"
49
50#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
51#define BSWAP_NEEDED
52#endif
53
54#ifdef BSWAP_NEEDED
55
56static inline uint16_t tswap16(uint16_t s)
57{
58 return bswap16(s);
59}
60
61static inline uint32_t tswap32(uint32_t s)
62{
63 return bswap32(s);
64}
65
66static inline uint64_t tswap64(uint64_t s)
67{
68 return bswap64(s);
69}
70
71static inline void tswap16s(uint16_t *s)
72{
73 *s = bswap16(*s);
74}
75
76static inline void tswap32s(uint32_t *s)
77{
78 *s = bswap32(*s);
79}
80
81static inline void tswap64s(uint64_t *s)
82{
83 *s = bswap64(*s);
84}
85
86#else
87
88static inline uint16_t tswap16(uint16_t s)
89{
90 return s;
91}
92
93static inline uint32_t tswap32(uint32_t s)
94{
95 return s;
96}
97
98static inline uint64_t tswap64(uint64_t s)
99{
100 return s;
101}
102
103static inline void tswap16s(uint16_t *s)
104{
105}
106
107static inline void tswap32s(uint32_t *s)
108{
109}
110
111static inline void tswap64s(uint64_t *s)
112{
113}
114
115#endif
116
117#if TARGET_LONG_SIZE == 4
118#define tswapl(s) tswap32(s)
119#define tswapls(s) tswap32s((uint32_t *)(s))
120#define bswaptls(s) bswap32s(s)
121#else
122#define tswapl(s) tswap64(s)
123#define tswapls(s) tswap64s((uint64_t *)(s))
124#define bswaptls(s) bswap64s(s)
125#endif
126
127/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
128 endian ! */
129typedef union {
130 float64 d;
131#if defined(WORDS_BIGENDIAN) \
132 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
133 struct {
134 uint32_t upper;
135 uint32_t lower;
136 } l;
137#else
138 struct {
139 uint32_t lower;
140 uint32_t upper;
141 } l;
142#endif
143 uint64_t ll;
144} CPU_DoubleU;
145
146/* CPU memory access without any memory or io remapping */
147
148/*
149 * the generic syntax for the memory accesses is:
150 *
151 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
152 *
153 * store: st{type}{size}{endian}_{access_type}(ptr, val)
154 *
155 * type is:
156 * (empty): integer access
157 * f : float access
158 *
159 * sign is:
160 * (empty): for floats or 32 bit size
161 * u : unsigned
162 * s : signed
163 *
164 * size is:
165 * b: 8 bits
166 * w: 16 bits
167 * l: 32 bits
168 * q: 64 bits
169 *
170 * endian is:
171 * (empty): target cpu endianness or 8 bit access
172 * r : reversed target cpu endianness (not implemented yet)
173 * be : big endian (not implemented yet)
174 * le : little endian (not implemented yet)
175 *
176 * access_type is:
177 * raw : host memory access
178 * user : user mode access using soft MMU
179 * kernel : kernel mode access using soft MMU
180 */
181#ifdef VBOX
182
183void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb);
184uint8_t remR3PhysReadU8(RTGCPHYS SrcGCPhys);
185int8_t remR3PhysReadS8(RTGCPHYS SrcGCPhys);
186uint16_t remR3PhysReadU16(RTGCPHYS SrcGCPhys);
187int16_t remR3PhysReadS16(RTGCPHYS SrcGCPhys);
188uint32_t remR3PhysReadU32(RTGCPHYS SrcGCPhys);
189int32_t remR3PhysReadS32(RTGCPHYS SrcGCPhys);
190uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys);
191int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys);
192void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb);
193void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val);
194void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val);
195void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val);
196void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val);
197
198#ifndef REM_PHYS_ADDR_IN_TLB
199void remR3PhysReadHCPtr(uint8_t *pbSrcPhys, void *pvDst, unsigned cb);
200uint8_t remR3PhysReadHCPtrU8(uint8_t *pbSrcPhys);
201int8_t remR3PhysReadHCPtrS8(uint8_t *pbSrcPhys);
202uint16_t remR3PhysReadHCPtrU16(uint8_t *pbSrcPhys);
203int16_t remR3PhysReadHCPtrS16(uint8_t *pbSrcPhys);
204uint32_t remR3PhysReadHCPtrU32(uint8_t *pbSrcPhys);
205int32_t remR3PhysReadHCPtrS32(uint8_t *pbSrcPhys);
206uint64_t remR3PhysReadHCPtrU64(uint8_t *pbSrcPhys);
207int64_t remR3PhysReadHCPtrS64(uint8_t *pbSrcPhys);
208void remR3PhysWriteHCPtr(uint8_t *pbDstPhys, const void *pvSrc, unsigned cb);
209void remR3PhysWriteHCPtrU8(uint8_t *pbDstPhys, uint8_t val);
210void remR3PhysWriteHCPtrU16(uint8_t *pbDstPhys, uint16_t val);
211void remR3PhysWriteHCPtrU32(uint8_t *pbDstPhys, uint32_t val);
212void remR3PhysWriteHCPtrU64(uint8_t *pbDstPhys, uint64_t val);
213#endif
214
215#ifdef PGM_DYNAMIC_RAM_ALLOC
216# ifndef REM_PHYS_ADDR_IN_TLB
217void *remR3GCPhys2HCVirt(void *env, target_ulong addr);
218target_ulong remR3HCVirt2GCPhys(void *env, void *addr);
219# endif
220void remR3GrowDynRange(unsigned long physaddr);
221#endif
222#if 0 /*defined(__AMD64__) && defined(VBOX_STRICT)*/
223# define VBOX_CHECK_ADDR(ptr) do { if ((uintptr_t)(ptr) >= _4G) __asm__("int3"); } while (0)
224#else
225# define VBOX_CHECK_ADDR(ptr) do { } while (0)
226#endif
227
228static inline int ldub_p(void *ptr)
229{
230#ifdef REM_PHYS_ADDR_IN_TLB
231 VBOX_CHECK_ADDR(ptr);
232 return remR3PhysReadU8((uintptr_t)ptr);
233#else
234 return remR3PhysReadHCPtrU8(ptr);
235#endif
236}
237
238static inline int ldsb_p(void *ptr)
239{
240#ifdef REM_PHYS_ADDR_IN_TLB
241 VBOX_CHECK_ADDR(ptr);
242 return remR3PhysReadS8((uintptr_t)ptr);
243#else
244 return remR3PhysReadHCPtrS8(ptr);
245#endif
246}
247
248static inline void stb_p(void *ptr, int v)
249{
250#ifdef REM_PHYS_ADDR_IN_TLB
251 VBOX_CHECK_ADDR(ptr);
252 remR3PhysWriteU8((uintptr_t)ptr, v);
253#else
254 remR3PhysWriteHCPtrU8(ptr, v);
255#endif
256}
257
258static inline int lduw_le_p(void *ptr)
259{
260#ifdef REM_PHYS_ADDR_IN_TLB
261 VBOX_CHECK_ADDR(ptr);
262 return remR3PhysReadU16((uintptr_t)ptr);
263#else
264 return remR3PhysReadHCPtrU16(ptr);
265#endif
266}
267
268static inline int ldsw_le_p(void *ptr)
269{
270#ifdef REM_PHYS_ADDR_IN_TLB
271 VBOX_CHECK_ADDR(ptr);
272 return remR3PhysReadS16((uintptr_t)ptr);
273#else
274 return remR3PhysReadHCPtrS16(ptr);
275#endif
276}
277
278static inline void stw_le_p(void *ptr, int v)
279{
280#ifdef REM_PHYS_ADDR_IN_TLB
281 VBOX_CHECK_ADDR(ptr);
282 remR3PhysWriteU16((uintptr_t)ptr, v);
283#else
284 remR3PhysWriteHCPtrU16(ptr, v);
285#endif
286}
287
288static inline int ldl_le_p(void *ptr)
289{
290#ifdef REM_PHYS_ADDR_IN_TLB
291 VBOX_CHECK_ADDR(ptr);
292 return remR3PhysReadU32((uintptr_t)ptr);
293#else
294 return remR3PhysReadHCPtrU32(ptr);
295#endif
296}
297
298static inline void stl_le_p(void *ptr, int v)
299{
300#ifdef REM_PHYS_ADDR_IN_TLB
301 VBOX_CHECK_ADDR(ptr);
302 remR3PhysWriteU32((uintptr_t)ptr, v);
303#else
304 remR3PhysWriteHCPtrU32(ptr, v);
305#endif
306}
307
308static inline void stq_le_p(void *ptr, uint64_t v)
309{
310#ifdef REM_PHYS_ADDR_IN_TLB
311 VBOX_CHECK_ADDR(ptr);
312 remR3PhysWriteU64((uintptr_t)ptr, v);
313#else
314 remR3PhysWriteHCPtrU64(ptr, v);
315#endif
316}
317
318static inline uint64_t ldq_le_p(void *ptr)
319{
320#ifdef REM_PHYS_ADDR_IN_TLB
321 VBOX_CHECK_ADDR(ptr);
322 return remR3PhysReadU64((uintptr_t)ptr);
323#else
324 return remR3PhysReadHCPtrU64(ptr);
325#endif
326}
327
328#undef VBOX_CHECK_ADDR
329
330/* float access */
331
332static inline float32 ldfl_le_p(void *ptr)
333{
334 union {
335 float32 f;
336 uint32_t i;
337 } u;
338 u.i = ldl_le_p(ptr);
339 return u.f;
340}
341
342static inline void stfl_le_p(void *ptr, float32 v)
343{
344 union {
345 float32 f;
346 uint32_t i;
347 } u;
348 u.f = v;
349 stl_le_p(ptr, u.i);
350}
351
352static inline float64 ldfq_le_p(void *ptr)
353{
354 CPU_DoubleU u;
355 u.l.lower = ldl_le_p(ptr);
356 u.l.upper = ldl_le_p(ptr + 4);
357 return u.d;
358}
359
360static inline void stfq_le_p(void *ptr, float64 v)
361{
362 CPU_DoubleU u;
363 u.d = v;
364 stl_le_p(ptr, u.l.lower);
365 stl_le_p(ptr + 4, u.l.upper);
366}
367
368#else /* !VBOX */
369
370static inline int ldub_p(void *ptr)
371{
372 return *(uint8_t *)ptr;
373}
374
375static inline int ldsb_p(void *ptr)
376{
377 return *(int8_t *)ptr;
378}
379
380static inline void stb_p(void *ptr, int v)
381{
382 *(uint8_t *)ptr = v;
383}
384
385/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
386 kernel handles unaligned load/stores may give better results, but
387 it is a system wide setting : bad */
388#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
389
390/* conservative code for little endian unaligned accesses */
391static inline int lduw_le_p(void *ptr)
392{
393#ifdef __powerpc__
394 int val;
395 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
396 return val;
397#else
398 uint8_t *p = ptr;
399 return p[0] | (p[1] << 8);
400#endif
401}
402
403static inline int ldsw_le_p(void *ptr)
404{
405#ifdef __powerpc__
406 int val;
407 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
408 return (int16_t)val;
409#else
410 uint8_t *p = ptr;
411 return (int16_t)(p[0] | (p[1] << 8));
412#endif
413}
414
415static inline int ldl_le_p(void *ptr)
416{
417#ifdef __powerpc__
418 int val;
419 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
420 return val;
421#else
422 uint8_t *p = ptr;
423 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
424#endif
425}
426
427static inline uint64_t ldq_le_p(void *ptr)
428{
429 uint8_t *p = ptr;
430 uint32_t v1, v2;
431 v1 = ldl_le_p(p);
432 v2 = ldl_le_p(p + 4);
433 return v1 | ((uint64_t)v2 << 32);
434}
435
436static inline void stw_le_p(void *ptr, int v)
437{
438#ifdef __powerpc__
439 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
440#else
441 uint8_t *p = ptr;
442 p[0] = v;
443 p[1] = v >> 8;
444#endif
445}
446
447static inline void stl_le_p(void *ptr, int v)
448{
449#ifdef __powerpc__
450 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
451#else
452 uint8_t *p = ptr;
453 p[0] = v;
454 p[1] = v >> 8;
455 p[2] = v >> 16;
456 p[3] = v >> 24;
457#endif
458}
459
460static inline void stq_le_p(void *ptr, uint64_t v)
461{
462 uint8_t *p = ptr;
463 stl_le_p(p, (uint32_t)v);
464 stl_le_p(p + 4, v >> 32);
465}
466
467/* float access */
468
469static inline float32 ldfl_le_p(void *ptr)
470{
471 union {
472 float32 f;
473 uint32_t i;
474 } u;
475 u.i = ldl_le_p(ptr);
476 return u.f;
477}
478
479static inline void stfl_le_p(void *ptr, float32 v)
480{
481 union {
482 float32 f;
483 uint32_t i;
484 } u;
485 u.f = v;
486 stl_le_p(ptr, u.i);
487}
488
489static inline float64 ldfq_le_p(void *ptr)
490{
491 CPU_DoubleU u;
492 u.l.lower = ldl_le_p(ptr);
493 u.l.upper = ldl_le_p(ptr + 4);
494 return u.d;
495}
496
497static inline void stfq_le_p(void *ptr, float64 v)
498{
499 CPU_DoubleU u;
500 u.d = v;
501 stl_le_p(ptr, u.l.lower);
502 stl_le_p(ptr + 4, u.l.upper);
503}
504
505#else
506
507static inline int lduw_le_p(void *ptr)
508{
509 return *(uint16_t *)ptr;
510}
511
512static inline int ldsw_le_p(void *ptr)
513{
514 return *(int16_t *)ptr;
515}
516
517static inline int ldl_le_p(void *ptr)
518{
519 return *(uint32_t *)ptr;
520}
521
522static inline uint64_t ldq_le_p(void *ptr)
523{
524 return *(uint64_t *)ptr;
525}
526
527static inline void stw_le_p(void *ptr, int v)
528{
529 *(uint16_t *)ptr = v;
530}
531
532static inline void stl_le_p(void *ptr, int v)
533{
534 *(uint32_t *)ptr = v;
535}
536
537static inline void stq_le_p(void *ptr, uint64_t v)
538{
539 *(uint64_t *)ptr = v;
540}
541
542/* float access */
543
544static inline float32 ldfl_le_p(void *ptr)
545{
546 return *(float32 *)ptr;
547}
548
549static inline float64 ldfq_le_p(void *ptr)
550{
551 return *(float64 *)ptr;
552}
553
554static inline void stfl_le_p(void *ptr, float32 v)
555{
556 *(float32 *)ptr = v;
557}
558
559static inline void stfq_le_p(void *ptr, float64 v)
560{
561 *(float64 *)ptr = v;
562}
563#endif
564#endif /* !VBOX */
565
566#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
567
568static inline int lduw_be_p(void *ptr)
569{
570#if defined(__i386__)
571 int val;
572 asm volatile ("movzwl %1, %0\n"
573 "xchgb %b0, %h0\n"
574 : "=q" (val)
575 : "m" (*(uint16_t *)ptr));
576 return val;
577#else
578 uint8_t *b = (uint8_t *) ptr;
579 return ((b[0] << 8) | b[1]);
580#endif
581}
582
583static inline int ldsw_be_p(void *ptr)
584{
585#if defined(__i386__)
586 int val;
587 asm volatile ("movzwl %1, %0\n"
588 "xchgb %b0, %h0\n"
589 : "=q" (val)
590 : "m" (*(uint16_t *)ptr));
591 return (int16_t)val;
592#else
593 uint8_t *b = (uint8_t *) ptr;
594 return (int16_t)((b[0] << 8) | b[1]);
595#endif
596}
597
598static inline int ldl_be_p(void *ptr)
599{
600#if defined(__i386__) || defined(__x86_64__)
601 int val;
602 asm volatile ("movl %1, %0\n"
603 "bswap %0\n"
604 : "=r" (val)
605 : "m" (*(uint32_t *)ptr));
606 return val;
607#else
608 uint8_t *b = (uint8_t *) ptr;
609 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
610#endif
611}
612
613static inline uint64_t ldq_be_p(void *ptr)
614{
615 uint32_t a,b;
616 a = ldl_be_p(ptr);
617 b = ldl_be_p(ptr+4);
618 return (((uint64_t)a<<32)|b);
619}
620
621static inline void stw_be_p(void *ptr, int v)
622{
623#if defined(__i386__)
624 asm volatile ("xchgb %b0, %h0\n"
625 "movw %w0, %1\n"
626 : "=q" (v)
627 : "m" (*(uint16_t *)ptr), "0" (v));
628#else
629 uint8_t *d = (uint8_t *) ptr;
630 d[0] = v >> 8;
631 d[1] = v;
632#endif
633}
634
635static inline void stl_be_p(void *ptr, int v)
636{
637#if defined(__i386__) || defined(__x86_64__)
638 asm volatile ("bswap %0\n"
639 "movl %0, %1\n"
640 : "=r" (v)
641 : "m" (*(uint32_t *)ptr), "0" (v));
642#else
643 uint8_t *d = (uint8_t *) ptr;
644 d[0] = v >> 24;
645 d[1] = v >> 16;
646 d[2] = v >> 8;
647 d[3] = v;
648#endif
649}
650
651static inline void stq_be_p(void *ptr, uint64_t v)
652{
653 stl_be_p(ptr, v >> 32);
654 stl_be_p(ptr + 4, v);
655}
656
657/* float access */
658
659static inline float32 ldfl_be_p(void *ptr)
660{
661 union {
662 float32 f;
663 uint32_t i;
664 } u;
665 u.i = ldl_be_p(ptr);
666 return u.f;
667}
668
669static inline void stfl_be_p(void *ptr, float32 v)
670{
671 union {
672 float32 f;
673 uint32_t i;
674 } u;
675 u.f = v;
676 stl_be_p(ptr, u.i);
677}
678
679static inline float64 ldfq_be_p(void *ptr)
680{
681 CPU_DoubleU u;
682 u.l.upper = ldl_be_p(ptr);
683 u.l.lower = ldl_be_p(ptr + 4);
684 return u.d;
685}
686
687static inline void stfq_be_p(void *ptr, float64 v)
688{
689 CPU_DoubleU u;
690 u.d = v;
691 stl_be_p(ptr, u.l.upper);
692 stl_be_p(ptr + 4, u.l.lower);
693}
694
695#else
696
697static inline int lduw_be_p(void *ptr)
698{
699 return *(uint16_t *)ptr;
700}
701
702static inline int ldsw_be_p(void *ptr)
703{
704 return *(int16_t *)ptr;
705}
706
707static inline int ldl_be_p(void *ptr)
708{
709 return *(uint32_t *)ptr;
710}
711
712static inline uint64_t ldq_be_p(void *ptr)
713{
714 return *(uint64_t *)ptr;
715}
716
717static inline void stw_be_p(void *ptr, int v)
718{
719 *(uint16_t *)ptr = v;
720}
721
722static inline void stl_be_p(void *ptr, int v)
723{
724 *(uint32_t *)ptr = v;
725}
726
727static inline void stq_be_p(void *ptr, uint64_t v)
728{
729 *(uint64_t *)ptr = v;
730}
731
732/* float access */
733
734static inline float32 ldfl_be_p(void *ptr)
735{
736 return *(float32 *)ptr;
737}
738
739static inline float64 ldfq_be_p(void *ptr)
740{
741 return *(float64 *)ptr;
742}
743
744static inline void stfl_be_p(void *ptr, float32 v)
745{
746 *(float32 *)ptr = v;
747}
748
749static inline void stfq_be_p(void *ptr, float64 v)
750{
751 *(float64 *)ptr = v;
752}
753
754#endif
755
756/* target CPU memory access functions */
757#if defined(TARGET_WORDS_BIGENDIAN)
758#define lduw_p(p) lduw_be_p(p)
759#define ldsw_p(p) ldsw_be_p(p)
760#define ldl_p(p) ldl_be_p(p)
761#define ldq_p(p) ldq_be_p(p)
762#define ldfl_p(p) ldfl_be_p(p)
763#define ldfq_p(p) ldfq_be_p(p)
764#define stw_p(p, v) stw_be_p(p, v)
765#define stl_p(p, v) stl_be_p(p, v)
766#define stq_p(p, v) stq_be_p(p, v)
767#define stfl_p(p, v) stfl_be_p(p, v)
768#define stfq_p(p, v) stfq_be_p(p, v)
769#else
770#define lduw_p(p) lduw_le_p(p)
771#define ldsw_p(p) ldsw_le_p(p)
772#define ldl_p(p) ldl_le_p(p)
773#define ldq_p(p) ldq_le_p(p)
774#define ldfl_p(p) ldfl_le_p(p)
775#define ldfq_p(p) ldfq_le_p(p)
776#define stw_p(p, v) stw_le_p(p, v)
777#define stl_p(p, v) stl_le_p(p, v)
778#define stq_p(p, v) stq_le_p(p, v)
779#define stfl_p(p, v) stfl_le_p(p, v)
780#define stfq_p(p, v) stfq_le_p(p, v)
781#endif
782
783/* MMU memory access macros */
784
785#if defined(CONFIG_USER_ONLY)
786/* On some host systems the guest address space is reserved on the host.
787 * This allows the guest address space to be offset to a convenient location.
788 */
789//#define GUEST_BASE 0x20000000
790#define GUEST_BASE 0
791
792/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
793#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
794#define h2g(x) ((target_ulong)(x - GUEST_BASE))
795
796#define saddr(x) g2h(x)
797#define laddr(x) g2h(x)
798
799#else /* !CONFIG_USER_ONLY */
800/* NOTE: we use double casts if pointers and target_ulong have
801 different sizes */
802#define saddr(x) (uint8_t *)(long)(x)
803#define laddr(x) (uint8_t *)(long)(x)
804#endif
805
806#define ldub_raw(p) ldub_p(laddr((p)))
807#define ldsb_raw(p) ldsb_p(laddr((p)))
808#define lduw_raw(p) lduw_p(laddr((p)))
809#define ldsw_raw(p) ldsw_p(laddr((p)))
810#define ldl_raw(p) ldl_p(laddr((p)))
811#define ldq_raw(p) ldq_p(laddr((p)))
812#define ldfl_raw(p) ldfl_p(laddr((p)))
813#define ldfq_raw(p) ldfq_p(laddr((p)))
814#define stb_raw(p, v) stb_p(saddr((p)), v)
815#define stw_raw(p, v) stw_p(saddr((p)), v)
816#define stl_raw(p, v) stl_p(saddr((p)), v)
817#define stq_raw(p, v) stq_p(saddr((p)), v)
818#define stfl_raw(p, v) stfl_p(saddr((p)), v)
819#define stfq_raw(p, v) stfq_p(saddr((p)), v)
820
821
822#if defined(CONFIG_USER_ONLY)
823
824/* if user mode, no other memory access functions */
825#define ldub(p) ldub_raw(p)
826#define ldsb(p) ldsb_raw(p)
827#define lduw(p) lduw_raw(p)
828#define ldsw(p) ldsw_raw(p)
829#define ldl(p) ldl_raw(p)
830#define ldq(p) ldq_raw(p)
831#define ldfl(p) ldfl_raw(p)
832#define ldfq(p) ldfq_raw(p)
833#define stb(p, v) stb_raw(p, v)
834#define stw(p, v) stw_raw(p, v)
835#define stl(p, v) stl_raw(p, v)
836#define stq(p, v) stq_raw(p, v)
837#define stfl(p, v) stfl_raw(p, v)
838#define stfq(p, v) stfq_raw(p, v)
839
840#define ldub_code(p) ldub_raw(p)
841#define ldsb_code(p) ldsb_raw(p)
842#define lduw_code(p) lduw_raw(p)
843#define ldsw_code(p) ldsw_raw(p)
844#define ldl_code(p) ldl_raw(p)
845
846#define ldub_kernel(p) ldub_raw(p)
847#define ldsb_kernel(p) ldsb_raw(p)
848#define lduw_kernel(p) lduw_raw(p)
849#define ldsw_kernel(p) ldsw_raw(p)
850#define ldl_kernel(p) ldl_raw(p)
851#define ldfl_kernel(p) ldfl_raw(p)
852#define ldfq_kernel(p) ldfq_raw(p)
853#define stb_kernel(p, v) stb_raw(p, v)
854#define stw_kernel(p, v) stw_raw(p, v)
855#define stl_kernel(p, v) stl_raw(p, v)
856#define stq_kernel(p, v) stq_raw(p, v)
857#define stfl_kernel(p, v) stfl_raw(p, v)
858#define stfq_kernel(p, vt) stfq_raw(p, v)
859
860#endif /* defined(CONFIG_USER_ONLY) */
861
862/* page related stuff */
863
864#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
865#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
866#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
867
868/* ??? These should be the larger of unsigned long and target_ulong. */
869extern unsigned long qemu_real_host_page_size;
870extern unsigned long qemu_host_page_bits;
871extern unsigned long qemu_host_page_size;
872extern unsigned long qemu_host_page_mask;
873
874#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
875
876/* same as PROT_xxx */
877#define PAGE_READ 0x0001
878#define PAGE_WRITE 0x0002
879#define PAGE_EXEC 0x0004
880#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
881#define PAGE_VALID 0x0008
882/* original state of the write flag (used when tracking self-modifying
883 code */
884#define PAGE_WRITE_ORG 0x0010
885
886void page_dump(FILE *f);
887int page_get_flags(target_ulong address);
888void page_set_flags(target_ulong start, target_ulong end, int flags);
889void page_unprotect_range(target_ulong data, target_ulong data_size);
890
891#define SINGLE_CPU_DEFINES
892#ifdef SINGLE_CPU_DEFINES
893
894#if defined(TARGET_I386)
895
896#define CPUState CPUX86State
897#define cpu_init cpu_x86_init
898#define cpu_exec cpu_x86_exec
899#define cpu_gen_code cpu_x86_gen_code
900#define cpu_signal_handler cpu_x86_signal_handler
901
902#elif defined(TARGET_ARM)
903
904#define CPUState CPUARMState
905#define cpu_init cpu_arm_init
906#define cpu_exec cpu_arm_exec
907#define cpu_gen_code cpu_arm_gen_code
908#define cpu_signal_handler cpu_arm_signal_handler
909
910#elif defined(TARGET_SPARC)
911
912#define CPUState CPUSPARCState
913#define cpu_init cpu_sparc_init
914#define cpu_exec cpu_sparc_exec
915#define cpu_gen_code cpu_sparc_gen_code
916#define cpu_signal_handler cpu_sparc_signal_handler
917
918#elif defined(TARGET_PPC)
919
920#define CPUState CPUPPCState
921#define cpu_init cpu_ppc_init
922#define cpu_exec cpu_ppc_exec
923#define cpu_gen_code cpu_ppc_gen_code
924#define cpu_signal_handler cpu_ppc_signal_handler
925
926#elif defined(TARGET_M68K)
927#define CPUState CPUM68KState
928#define cpu_init cpu_m68k_init
929#define cpu_exec cpu_m68k_exec
930#define cpu_gen_code cpu_m68k_gen_code
931#define cpu_signal_handler cpu_m68k_signal_handler
932
933#elif defined(TARGET_MIPS)
934#define CPUState CPUMIPSState
935#define cpu_init cpu_mips_init
936#define cpu_exec cpu_mips_exec
937#define cpu_gen_code cpu_mips_gen_code
938#define cpu_signal_handler cpu_mips_signal_handler
939
940#elif defined(TARGET_SH4)
941#define CPUState CPUSH4State
942#define cpu_init cpu_sh4_init
943#define cpu_exec cpu_sh4_exec
944#define cpu_gen_code cpu_sh4_gen_code
945#define cpu_signal_handler cpu_sh4_signal_handler
946
947#else
948
949#error unsupported target CPU
950
951#endif
952
953#endif /* SINGLE_CPU_DEFINES */
954
955void cpu_dump_state(CPUState *env, FILE *f,
956 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
957 int flags);
958
959void cpu_abort(CPUState *env, const char *fmt, ...);
960extern CPUState *first_cpu;
961extern CPUState *cpu_single_env;
962extern int code_copy_enabled;
963
964#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
965#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
966#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
967#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
968#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
969#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
970#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
971
972#ifdef VBOX
973/** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
974#define CPU_INTERRUPT_SINGLE_INSTR 0x0200
975/** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
976#define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0400
977/** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
978#define CPU_INTERRUPT_RC 0x0800
979/** Exit current TB to process an external interrupt request (also in op.c!!) */
980#define CPU_INTERRUPT_EXTERNAL_EXIT 0x1000
981/** Exit current TB to process an external interrupt request (also in op.c!!) */
982#define CPU_INTERRUPT_EXTERNAL_HARD 0x2000
983/** Exit current TB to process an external interrupt request (also in op.c!!) */
984#define CPU_INTERRUPT_EXTERNAL_TIMER 0x4000
985/** Exit current TB to process an external interrupt request (also in op.c!!) */
986#define CPU_INTERRUPT_EXTERNAL_DMA 0x8000
987#endif /* VBOX */
988void cpu_interrupt(CPUState *s, int mask);
989void cpu_reset_interrupt(CPUState *env, int mask);
990
991int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
992int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
993void cpu_single_step(CPUState *env, int enabled);
994void cpu_reset(CPUState *s);
995
996/* Return the physical page corresponding to a virtual one. Use it
997 only for debugging because no protection checks are done. Return -1
998 if no page found. */
999target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
1000
1001#define CPU_LOG_TB_OUT_ASM (1 << 0)
1002#define CPU_LOG_TB_IN_ASM (1 << 1)
1003#define CPU_LOG_TB_OP (1 << 2)
1004#define CPU_LOG_TB_OP_OPT (1 << 3)
1005#define CPU_LOG_INT (1 << 4)
1006#define CPU_LOG_EXEC (1 << 5)
1007#define CPU_LOG_PCALL (1 << 6)
1008#define CPU_LOG_IOPORT (1 << 7)
1009#define CPU_LOG_TB_CPU (1 << 8)
1010
1011/* define log items */
1012typedef struct CPULogItem {
1013 int mask;
1014 const char *name;
1015 const char *help;
1016} CPULogItem;
1017
1018extern CPULogItem cpu_log_items[];
1019
1020void cpu_set_log(int log_flags);
1021void cpu_set_log_filename(const char *filename);
1022int cpu_str_to_log_mask(const char *str);
1023
1024/* IO ports API */
1025
1026/* NOTE: as these functions may be even used when there is an isa
1027 brige on non x86 targets, we always defined them */
1028#ifndef NO_CPU_IO_DEFS
1029void cpu_outb(CPUState *env, int addr, int val);
1030void cpu_outw(CPUState *env, int addr, int val);
1031void cpu_outl(CPUState *env, int addr, int val);
1032int cpu_inb(CPUState *env, int addr);
1033int cpu_inw(CPUState *env, int addr);
1034int cpu_inl(CPUState *env, int addr);
1035#endif
1036
1037/* memory API */
1038
1039#ifndef VBOX
1040extern int phys_ram_size;
1041extern int phys_ram_fd;
1042extern int phys_ram_size;
1043#else /* VBOX */
1044extern RTGCPHYS phys_ram_size;
1045/** This is required for bounds checking the phys_ram_dirty accesses. */
1046extern uint32_t phys_ram_dirty_size;
1047#endif /* VBOX */
1048#if !defined(VBOX) || !(defined(PGM_DYNAMIC_RAM_ALLOC) || defined(REM_PHYS_ADDR_IN_TLB))
1049extern uint8_t *phys_ram_base;
1050#endif
1051extern uint8_t *phys_ram_dirty;
1052
1053/* physical memory access */
1054#define TLB_INVALID_MASK (1 << 3)
1055#define IO_MEM_SHIFT 4
1056#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
1057
1058#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
1059#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
1060#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
1061#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
1062#if defined(VBOX) && defined(PGM_DYNAMIC_RAM_ALLOC)
1063#define IO_MEM_RAM_MISSING (5 << IO_MEM_SHIFT) /* used internally, never use directly */
1064#endif
1065/* acts like a ROM when read and like a device when written. As an
1066 exception, the write memory callback gets the ram offset instead of
1067 the physical address */
1068#define IO_MEM_ROMD (1)
1069
1070typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
1071typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
1072
1073void cpu_register_physical_memory(target_phys_addr_t start_addr,
1074 unsigned long size,
1075 unsigned long phys_offset);
1076uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
1077int cpu_register_io_memory(int io_index,
1078 CPUReadMemoryFunc **mem_read,
1079 CPUWriteMemoryFunc **mem_write,
1080 void *opaque);
1081CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
1082CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
1083
1084void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1085 int len, int is_write);
1086static inline void cpu_physical_memory_read(target_phys_addr_t addr,
1087 uint8_t *buf, int len)
1088{
1089 cpu_physical_memory_rw(addr, buf, len, 0);
1090}
1091static inline void cpu_physical_memory_write(target_phys_addr_t addr,
1092 const uint8_t *buf, int len)
1093{
1094 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
1095}
1096uint32_t ldub_phys(target_phys_addr_t addr);
1097uint32_t lduw_phys(target_phys_addr_t addr);
1098uint32_t ldl_phys(target_phys_addr_t addr);
1099uint64_t ldq_phys(target_phys_addr_t addr);
1100void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
1101void stb_phys(target_phys_addr_t addr, uint32_t val);
1102void stw_phys(target_phys_addr_t addr, uint32_t val);
1103void stl_phys(target_phys_addr_t addr, uint32_t val);
1104void stq_phys(target_phys_addr_t addr, uint64_t val);
1105
1106void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1107 const uint8_t *buf, int len);
1108int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1109 uint8_t *buf, int len, int is_write);
1110
1111#define VGA_DIRTY_FLAG 0x01
1112#define CODE_DIRTY_FLAG 0x02
1113
1114/* read dirty bit (return 0 or 1) */
1115static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1116{
1117#ifdef VBOX
1118 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1119 {
1120 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1121 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1122 return 0;
1123 }
1124#endif
1125 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1126}
1127
1128static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
1129 int dirty_flags)
1130{
1131#ifdef VBOX
1132 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1133 {
1134 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1135 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1136 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */
1137 }
1138#endif
1139 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1140}
1141
1142static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1143{
1144#ifdef VBOX
1145 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1146 {
1147 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1148 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1149 return;
1150 }
1151#endif
1152 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1153}
1154
1155void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1156 int dirty_flags);
1157void cpu_tlb_update_dirty(CPUState *env);
1158
1159void dump_exec_info(FILE *f,
1160 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1161
1162/*******************************************/
1163/* host CPU ticks (if available) */
1164
1165#if defined(__powerpc__)
1166
1167static inline uint32_t get_tbl(void)
1168{
1169 uint32_t tbl;
1170 asm volatile("mftb %0" : "=r" (tbl));
1171 return tbl;
1172}
1173
1174static inline uint32_t get_tbu(void)
1175{
1176 uint32_t tbl;
1177 asm volatile("mftbu %0" : "=r" (tbl));
1178 return tbl;
1179}
1180
1181static inline int64_t cpu_get_real_ticks(void)
1182{
1183 uint32_t l, h, h1;
1184 /* NOTE: we test if wrapping has occurred */
1185 do {
1186 h = get_tbu();
1187 l = get_tbl();
1188 h1 = get_tbu();
1189 } while (h != h1);
1190 return ((int64_t)h << 32) | l;
1191}
1192
1193#elif defined(__i386__)
1194
1195static inline int64_t cpu_get_real_ticks(void)
1196{
1197 int64_t val;
1198 asm volatile ("rdtsc" : "=A" (val));
1199 return val;
1200}
1201
1202#elif defined(__x86_64__)
1203
1204static inline int64_t cpu_get_real_ticks(void)
1205{
1206 uint32_t low,high;
1207 int64_t val;
1208 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1209 val = high;
1210 val <<= 32;
1211 val |= low;
1212 return val;
1213}
1214
1215#elif defined(__ia64)
1216
1217static inline int64_t cpu_get_real_ticks(void)
1218{
1219 int64_t val;
1220 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1221 return val;
1222}
1223
1224#elif defined(__s390__)
1225
1226static inline int64_t cpu_get_real_ticks(void)
1227{
1228 int64_t val;
1229 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1230 return val;
1231}
1232
1233#elif defined(__sparc_v9__)
1234
1235static inline int64_t cpu_get_real_ticks (void)
1236{
1237#if defined(_LP64)
1238 uint64_t rval;
1239 asm volatile("rd %%tick,%0" : "=r"(rval));
1240 return rval;
1241#else
1242 union {
1243 uint64_t i64;
1244 struct {
1245 uint32_t high;
1246 uint32_t low;
1247 } i32;
1248 } rval;
1249 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1250 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1251 return rval.i64;
1252#endif
1253}
1254#else
1255/* The host CPU doesn't have an easily accessible cycle counter.
1256 Just return a monotonically increasing vlue. This will be totally wrong,
1257 but hopefully better than nothing. */
1258static inline int64_t cpu_get_real_ticks (void)
1259{
1260 static int64_t ticks = 0;
1261 return ticks++;
1262}
1263#endif
1264
1265/* profiling */
1266#ifdef CONFIG_PROFILER
1267static inline int64_t profile_getclock(void)
1268{
1269 return cpu_get_real_ticks();
1270}
1271
1272extern int64_t kqemu_time, kqemu_time_start;
1273extern int64_t qemu_time, qemu_time_start;
1274extern int64_t tlb_flush_time;
1275extern int64_t kqemu_exec_count;
1276extern int64_t dev_time;
1277extern int64_t kqemu_ret_int_count;
1278extern int64_t kqemu_ret_excp_count;
1279extern int64_t kqemu_ret_intr_count;
1280
1281#endif
1282
1283#ifdef VBOX
1284void tb_invalidate_virt(CPUState *env, uint32_t eip);
1285#endif /* VBOX */
1286
1287#endif /* CPU_ALL_H */
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