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source: vbox/trunk/src/recompiler/cpu-common.h@ 75569

最後變更 在這個檔案從75569是 42601,由 vboxsync 提交於 12 年 前

REM: Initial changes to make it work (seemingly) with MinGW-w64.

  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 5.1 KB
 
1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H 1
3
4/* CPU interfaces that are target indpendent. */
5
6#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
7#define WORDS_ALIGNED
8#endif
9
10#ifdef TARGET_PHYS_ADDR_BITS
11#include "targphys.h"
12#endif
13
14#ifndef NEED_CPU_H
15#include "poison.h"
16#endif
17
18#include "bswap.h"
19#include "qemu-queue.h"
20
21#if !defined(CONFIG_USER_ONLY)
22
23/* address in the RAM (different from a physical address) */
24typedef uintptr_t ram_addr_t;
25
26/* memory API */
27
28typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
29typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
30
31void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
32 ram_addr_t size,
33 ram_addr_t phys_offset,
34 ram_addr_t region_offset);
35static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
36 ram_addr_t size,
37 ram_addr_t phys_offset)
38{
39 cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
40}
41
42ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
43#ifndef VBOX
44ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
45 ram_addr_t size, void *host);
46ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
47void qemu_ram_free(ram_addr_t addr);
48/* This should only be used for ram local to a device. */
49void *qemu_get_ram_ptr(ram_addr_t addr);
50/* This should not be used by devices. */
51ram_addr_t qemu_ram_addr_from_host(void *ptr);
52#endif /* !VBOX */
53
54int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
55 CPUWriteMemoryFunc * const *mem_write,
56 void *opaque);
57void cpu_unregister_io_memory(int table_address);
58
59void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
60 int len, int is_write);
61static inline void cpu_physical_memory_read(target_phys_addr_t addr,
62 uint8_t *buf, int len)
63{
64 cpu_physical_memory_rw(addr, buf, len, 0);
65}
66static inline void cpu_physical_memory_write(target_phys_addr_t addr,
67 const uint8_t *buf, int len)
68{
69 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
70}
71void *cpu_physical_memory_map(target_phys_addr_t addr,
72 target_phys_addr_t *plen,
73 int is_write);
74void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
75 int is_write, target_phys_addr_t access_len);
76void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
77void cpu_unregister_map_client(void *cookie);
78
79struct CPUPhysMemoryClient;
80typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
81struct CPUPhysMemoryClient {
82 void (*set_memory)(struct CPUPhysMemoryClient *client,
83 target_phys_addr_t start_addr,
84 ram_addr_t size,
85 ram_addr_t phys_offset);
86 int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
87 target_phys_addr_t start_addr,
88 target_phys_addr_t end_addr);
89 int (*migration_log)(struct CPUPhysMemoryClient *client,
90 int enable);
91 QLIST_ENTRY(CPUPhysMemoryClient) list;
92};
93
94void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
95void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
96
97/* Coalesced MMIO regions are areas where write operations can be reordered.
98 * This usually implies that write operations are side-effect free. This allows
99 * batching which can make a major impact on performance when using
100 * virtualization.
101 */
102void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
103
104void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
105
106void qemu_flush_coalesced_mmio_buffer(void);
107
108uint32_t ldub_phys(target_phys_addr_t addr);
109uint32_t lduw_phys(target_phys_addr_t addr);
110uint32_t ldl_phys(target_phys_addr_t addr);
111uint64_t ldq_phys(target_phys_addr_t addr);
112void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
113void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
114void stb_phys(target_phys_addr_t addr, uint32_t val);
115void stw_phys(target_phys_addr_t addr, uint32_t val);
116void stl_phys(target_phys_addr_t addr, uint32_t val);
117void stq_phys(target_phys_addr_t addr, uint64_t val);
118
119void cpu_physical_memory_write_rom(target_phys_addr_t addr,
120 const uint8_t *buf, int len);
121
122#define IO_MEM_SHIFT 3
123
124#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
125#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
126#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
127#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
128
129/* Acts like a ROM when read and like a device when written. */
130#define IO_MEM_ROMD (1)
131#define IO_MEM_SUBPAGE (2)
132
133#endif
134
135#endif /* !CPU_COMMON_H */
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