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source: vbox/trunk/src/recompiler/cpu-defs.h@ 75569

最後變更 在這個檔案從75569是 69465,由 vboxsync 提交於 7 年 前

recompiler: scm updates

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檔案大小: 9.9 KB
 
1/*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20/*
21 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
22 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
23 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
24 * a choice of LGPL license versions is made available with the language indicating
25 * that LGPLv2 or any later version may be used, or where a choice of which version
26 * of the LGPL is applied is otherwise unspecified.
27 */
28
29#ifndef CPU_DEFS_H
30#define CPU_DEFS_H
31
32#ifndef NEED_CPU_H
33#error cpu.h included from common code
34#endif
35
36#include "config.h"
37#include <setjmp.h>
38#include <inttypes.h>
39#ifndef VBOX
40#include <signal.h>
41#else /* VBOX */
42# define sig_atomic_t int32_t
43#endif /* VBOX */
44#include "osdep.h"
45#include "qemu-queue.h"
46#include "targphys.h"
47
48#ifndef TARGET_LONG_BITS
49#error TARGET_LONG_BITS must be defined before including this header
50#endif
51
52#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
53
54/* target_ulong is the type of a virtual address */
55#if TARGET_LONG_SIZE == 4
56typedef int32_t target_long;
57typedef uint32_t target_ulong;
58#define TARGET_FMT_lx "%08x"
59#define TARGET_FMT_ld "%d"
60#define TARGET_FMT_lu "%u"
61#elif TARGET_LONG_SIZE == 8
62typedef int64_t target_long;
63typedef uint64_t target_ulong;
64#define TARGET_FMT_lx "%016" PRIx64
65#define TARGET_FMT_ld "%" PRId64
66#define TARGET_FMT_lu "%" PRIu64
67#else
68#error TARGET_LONG_SIZE undefined
69#endif
70
71#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
72
73#define EXCP_INTERRUPT 0x10000 /* async interruption */
74#define EXCP_HLT 0x10001 /* hlt instruction reached */
75#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
76#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
77#ifdef VBOX
78# define EXCP_EXECUTE_RAW 0x11024 /**< execute raw mode. */
79# define EXCP_EXECUTE_HM 0x11025 /**< execute hardware accelerated raw mode. */
80# define EXCP_SINGLE_INSTR 0x11026 /**< executed single instruction. */
81# define EXCP_RC 0x11027 /**< a EM rc was raised (VMR3Reset/Suspend/PowerOff). */
82#endif /* VBOX */
83
84#define TB_JMP_CACHE_BITS 12
85#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
86
87/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
88 addresses on the same page. The top bits are the same. This allows
89 TLB invalidation to quickly clear a subset of the hash table. */
90#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
91#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
92#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
93#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
94
95#if !defined(CONFIG_USER_ONLY)
96#define CPU_TLB_BITS 8
97#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
98
99#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
100#define CPU_TLB_ENTRY_BITS 4
101#else
102#define CPU_TLB_ENTRY_BITS 5
103#endif
104
105typedef struct CPUTLBEntry {
106 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
107 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
108 go directly to ram.
109 bit 3 : indicates that the entry is invalid
110 bit 2..0 : zero
111 */
112 target_ulong addr_read;
113 target_ulong addr_write;
114 target_ulong addr_code;
115 /* Addend to virtual address to get host address. IO accesses
116 use the corresponding iotlb value. */
117 uintptr_t addend;
118 /* padding to get a power of two size */
119 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
120 (sizeof(target_ulong) * 3 +
121 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
122 sizeof(uintptr_t))];
123} CPUTLBEntry;
124
125extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
126
127#define CPU_COMMON_TLB \
128 /* The meaning of the MMU modes is defined in the target code. */ \
129 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
130 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
131 target_ulong tlb_flush_addr; \
132 target_ulong tlb_flush_mask;
133
134#else
135
136#define CPU_COMMON_TLB
137
138#endif
139
140
141#ifdef HOST_WORDS_BIGENDIAN
142typedef struct icount_decr_u16 {
143 uint16_t high;
144 uint16_t low;
145} icount_decr_u16;
146#else
147typedef struct icount_decr_u16 {
148 uint16_t low;
149 uint16_t high;
150} icount_decr_u16;
151#endif
152
153struct kvm_run;
154struct KVMState;
155struct qemu_work_item;
156
157typedef struct CPUBreakpoint {
158 target_ulong pc;
159 int flags; /* BP_* */
160 QTAILQ_ENTRY(CPUBreakpoint) entry;
161} CPUBreakpoint;
162
163typedef struct CPUWatchpoint {
164 target_ulong vaddr;
165 target_ulong len_mask;
166 int flags; /* BP_* */
167 QTAILQ_ENTRY(CPUWatchpoint) entry;
168} CPUWatchpoint;
169
170#define CPU_TEMP_BUF_NLONGS 128
171#define CPU_COMMON \
172 struct TranslationBlock *current_tb; /* currently executing TB */ \
173 /* soft mmu support */ \
174 /* in order to avoid passing too many arguments to the MMIO \
175 helpers, we store some rarely used information in the CPU \
176 context) */ \
177 uintptr_t mem_io_pc; /* host pc at which the memory was \
178 accessed */ \
179 target_ulong mem_io_vaddr; /* target virtual addr at which the \
180 memory was accessed */ \
181 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
182 uint32_t interrupt_request; \
183 volatile sig_atomic_t exit_request; \
184 CPU_COMMON_TLB \
185 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
186 /* buffer for temporaries in the code generator */ \
187 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
188 \
189 int64_t icount_extra; /* Instructions until next timer event. */ \
190 /* Number of cycles left, with interrupt flag in high bit. \
191 This allows a single read-compare-cbranch-write sequence to test \
192 for both decrementer underflow and exceptions. */ \
193 union { \
194 uint32_t u32; \
195 icount_decr_u16 u16; \
196 } icount_decr; \
197 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
198 \
199 /* from this point: preserved by CPU reset */ \
200 /* ice debug support */ \
201 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
202 int singlestep_enabled; \
203 \
204 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
205 CPUWatchpoint *watchpoint_hit; \
206 \
207 struct GDBRegisterState *gdb_regs; \
208 \
209 /* Core interrupt code */ \
210 jmp_buf jmp_env; \
211 int exception_index; \
212 \
213 CPUState *next_cpu; /* next CPU sharing TB cache */ \
214 int cpu_index; /* CPU index (informative) */ \
215 uint32_t host_tid; /* host thread ID */ \
216 int numa_node; /* NUMA node this cpu is belonging to */ \
217 int nr_cores; /* number of cores within this CPU package */ \
218 int nr_threads;/* number of threads within this CPU */ \
219 int running; /* Nonzero if cpu is currently running(usermode). */ \
220 /* user data */ \
221 void *opaque; \
222 \
223 uint32_t created; \
224 uint32_t stop; /* Stop request */ \
225 uint32_t stopped; /* Artificially stopped */ \
226 struct QemuThread *thread; \
227 struct QemuCond *halt_cond; \
228 struct qemu_work_item *queued_work_first, *queued_work_last; \
229 const char *cpu_model_str; \
230 struct KVMState *kvm_state; \
231 struct kvm_run *kvm_run; \
232 int kvm_fd; \
233 int kvm_vcpu_dirty;
234
235#endif
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