exec-all.h@ 1005

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1	/*
2	* internal execution defines for qemu
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20
21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
22	#ifndef VBOX
23	#define DEBUG_DISAS
24	#endif
25
26	#ifdef VBOX
27	#include <VBox/tm.h>
28	#ifndef LOG_GROUP
29	#define LOG_GROUP LOG_GROUP_REM
30	#endif
31	#include <VBox/log.h>
32	#include "REMInternal.h"
33	#endif /* VBOX */
34
35	#ifndef glue
36	#define xglue(x, y) x ## y
37	#define glue(x, y) xglue(x, y)
38	#define stringify(s) tostring(s)
39	#define tostring(s) #s
40	#endif
41
42	#if GCC_MAJOR < 3
43	#define __builtin_expect(x, n) (x)
44	#endif
45
46	#ifdef __i386__
47	#define REGPARM(n) __attribute((regparm(n)))
48	#else
49	#define REGPARM(n)
50	#endif
51
52	/* is_jmp field values */
53	#define DISAS_NEXT 0 /* next instruction can be analyzed */
54	#define DISAS_JUMP 1 /* only pc was modified dynamically */
55	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
56	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
57
58	struct TranslationBlock;
59
60	/* XXX: make safe guess about sizes */
61	#define MAX_OP_PER_INSTR 32
62	#define OPC_BUF_SIZE 512
63	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
64
65	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
66
67	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
68	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
69	extern long gen_labels[OPC_BUF_SIZE];
70	extern int nb_gen_labels;
71	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
72	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
73	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
74	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
75
76	typedef void (GenOpFunc)(void);
77	typedef void (GenOpFunc1)(long);
78	typedef void (GenOpFunc2)(long, long);
79	typedef void (GenOpFunc3)(long, long, long);
80
81	#if defined(TARGET_I386)
82
83	void optimize_flags_init(void);
84
85	#endif
86
87	extern FILE *logfile;
88	extern int loglevel;
89
90	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
91	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
92	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
93	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
94	int max_code_size, int *gen_code_size_ptr);
95	int cpu_restore_state(struct TranslationBlock *tb,
96	CPUState *env, unsigned long searched_pc,
97	void *puc);
98	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
99	int max_code_size, int *gen_code_size_ptr);
100	int cpu_restore_state_copy(struct TranslationBlock *tb,
101	CPUState *env, unsigned long searched_pc,
102	void *puc);
103	void cpu_resume_from_signal(CPUState env1, void puc);
104	void cpu_exec_init(void);
105	int page_unprotect(unsigned long address, unsigned long pc, void *puc);
106	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
107	int is_cpu_write_access);
108	void tb_invalidate_page_range(target_ulong start, target_ulong end);
109	void tlb_flush_page(CPUState *env, target_ulong addr);
110	void tlb_flush(CPUState *env, int flush_global);
111	int tlb_set_page(CPUState *env, target_ulong vaddr,
112	target_phys_addr_t paddr, int prot,
113	int is_user, int is_softmmu);
114
115
116	#define CODE_GEN_MAX_SIZE 65536
117	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
118
119	#define CODE_GEN_HASH_BITS 15
120	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
121
122	#define CODE_GEN_PHYS_HASH_BITS 15
123	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
124
125	/* maximum total translate dcode allocated */
126
127	/* NOTE: the translated code area cannot be too big because on some
128	archs the range of "fast" function calls is limited. Here is a
129	summary of the ranges:
130
131	i386 : signed 32 bits
132	arm : signed 26 bits
133	ppc : signed 24 bits
134	sparc : signed 32 bits
135	alpha : signed 23 bits
136	*/
137
138	#if defined(__alpha__)
139	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
140	#elif defined(__powerpc__)
141	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
142	#else
143	#define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
144	#endif
145
146	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
147
148	/* estimated block size for TB allocation */
149	/* XXX: use a per code average code fragment size and modulate it
150	according to the host CPU */
151	#if defined(CONFIG_SOFTMMU)
152	#define CODE_GEN_AVG_BLOCK_SIZE 128
153	#else
154	#define CODE_GEN_AVG_BLOCK_SIZE 64
155	#endif
156
157	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
158
159	#if defined(__powerpc__)
160	#define USE_DIRECT_JUMP
161	#endif
162	#if defined(__i386__) && !defined(_WIN32)
163	#define USE_DIRECT_JUMP
164	#endif
165	#ifdef VBOX /* bird: not safe in next step because of threading & cpu_interrupt. */
166	#undef USE_DIRECT_JUMP
167	#endif /* VBOX */
168
169	typedef struct TranslationBlock {
170	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
171	target_ulong cs_base; /* CS base for this block */
172	unsigned int flags; /* flags defining in which context the code was generated */
173	uint16_t size; /* size of target code for this block (1 <=
174	size <= TARGET_PAGE_SIZE) */
175	uint16_t cflags; /* compile flags */
176	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
177	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
178	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
179	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
180	#ifdef VBOX
181	#define CF_RAW_MODE 0x0010 /* block was generated in raw mode */
182	#endif
183
184	uint8_t tc_ptr; / pointer to the translated code */
185	struct TranslationBlock hash_next; / next matching tb for virtual address */
186	/* next matching tb for physical address. */
187	struct TranslationBlock *phys_hash_next;
188	/* first and second physical page containing code. The lower bit
189	of the pointer tells the index in page_next[] */
190	struct TranslationBlock *page_next[2];
191	target_ulong page_addr[2];
192
193	/* the following data are used to directly call another TB from
194	the code of this one. */
195	uint16_t tb_next_offset[2]; /* offset of original jump target */
196	#ifdef USE_DIRECT_JUMP
197	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
198	#else
199	uint32_t tb_next[2]; /* address of jump generated code */
200	#endif
201	/* list of TBs jumping to this one. This is a circular list using
202	the two least significant bits of the pointers to tell what is
203	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
204	jmp_first */
205	struct TranslationBlock *jmp_next[2];
206	struct TranslationBlock *jmp_first;
207	} TranslationBlock;
208
209	static inline unsigned int tb_hash_func(target_ulong pc)
210	{
211	return pc & (CODE_GEN_HASH_SIZE - 1);
212	}
213
214	static inline unsigned int tb_phys_hash_func(unsigned long pc)
215	{
216	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
217	}
218
219	TranslationBlock *tb_alloc(target_ulong pc);
220	void tb_flush(CPUState *env);
221	void tb_link(TranslationBlock *tb);
222	void tb_link_phys(TranslationBlock *tb,
223	target_ulong phys_pc, target_ulong phys_page2);
224
225	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
226	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
227
228	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
229	extern uint8_t *code_gen_ptr;
230
231	/* find a translation block in the translation cache. If not found,
232	return NULL and the pointer to the last element of the list in pptb */
233	static inline TranslationBlock tb_find(TranslationBlock **pptb,
234	target_ulong pc,
235	target_ulong cs_base,
236	unsigned int flags)
237	{
238	TranslationBlock *ptb, tb;
239	unsigned int h;
240
241	h = tb_hash_func(pc);
242	ptb = &tb_hash[h];
243	for(;;) {
244	tb = *ptb;
245	if (!tb)
246	break;
247	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
248	return tb;
249	ptb = &tb->hash_next;
250	}
251	*pptb = ptb;
252	return NULL;
253	}
254
255
256	#if defined(USE_DIRECT_JUMP)
257
258	#if defined(__powerpc__)
259	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
260	{
261	uint32_t val, *ptr;
262
263	/* patch the branch destination */
264	ptr = (uint32_t *)jmp_addr;
265	val = *ptr;
266	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
267	*ptr = val;
268	/* flush icache */
269	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
270	asm volatile ("sync" : : : "memory");
271	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
272	asm volatile ("sync" : : : "memory");
273	asm volatile ("isync" : : : "memory");
274	}
275	#elif defined(__i386__)
276	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
277	{
278	/* patch the branch destination */
279	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
280	/* no need to flush icache explicitely */
281	}
282	#endif
283
284	static inline void tb_set_jmp_target(TranslationBlock *tb,
285	int n, unsigned long addr)
286	{
287	unsigned long offset;
288
289	offset = tb->tb_jmp_offset[n];
290	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
291	offset = tb->tb_jmp_offset[n + 2];
292	if (offset != 0xffff)
293	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
294	}
295
296	#else
297
298	/* set the jump target */
299	static inline void tb_set_jmp_target(TranslationBlock *tb,
300	int n, unsigned long addr)
301	{
302	tb->tb_next[n] = addr;
303	}
304
305	#endif
306
307	static inline void tb_add_jump(TranslationBlock *tb, int n,
308	TranslationBlock *tb_next)
309	{
310	/* NOTE: this test is only needed for thread safety */
311	if (!tb->jmp_next[n]) {
312	/* patch the native jump address */
313	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
314
315	/* add in TB jmp circular list */
316	tb->jmp_next[n] = tb_next->jmp_first;
317	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
318	}
319	}
320
321	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
322
323	#ifndef offsetof
324	#define offsetof(type, field) ((size_t) &((type *)0)->field)
325	#endif
326
327	#if defined(_WIN32)
328	#define ASM_DATA_SECTION ".section \".data\"\n"
329	#define ASM_PREVIOUS_SECTION ".section .text\n"
330	#elif defined(__APPLE__)
331	#define ASM_DATA_SECTION ".data\n"
332	#define ASM_PREVIOUS_SECTION ".text\n"
333	#else
334	#define ASM_DATA_SECTION ".section \".data\"\n"
335	#define ASM_PREVIOUS_SECTION ".previous\n"
336	#endif
337
338	#if defined(__powerpc__)
339
340	/* we patch the jump instruction directly */
341	#define GOTO_TB(opname, tbparam, n)\
342	do {\
343	asm volatile (ASM_DATA_SECTION\
344	ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
345	".long 1f\n"\
346	ASM_PREVIOUS_SECTION \
347	"b " ASM_NAME(__op_jmp) #n "\n"\
348	"1:\n");\
349	} while (0)
350
351	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
352
353	/* we patch the jump instruction directly */
354	#define GOTO_TB(opname, tbparam, n)\
355	do {\
356	asm volatile (".section .data\n"\
357	ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
358	".long 1f\n"\
359	ASM_PREVIOUS_SECTION \
360	"jmp " ASM_NAME(__op_jmp) #n "\n"\
361	"1:\n");\
362	} while (0)
363
364	#else
365
366	/* jump to next block operations (more portable code, does not need
367	cache flushing, but slower because of indirect jump) */
368	#define GOTO_TB(opname, tbparam, n)\
369	do {\
370	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
371	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
372	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
373	label ## n: ;\
374	dummy_label ## n: ;\
375	} while (0)
376
377	#endif
378
379	/* XXX: will be suppressed */
380	#define JUMP_TB(opname, tbparam, n, eip)\
381	do {\
382	GOTO_TB(opname, tbparam, n);\
383	T0 = (long)(tbparam) + (n);\
384	EIP = (int32_t)eip;\
385	EXIT_TB();\
386	} while (0)
387
388	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
389	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
390	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
391
392	#ifdef __powerpc__
393	static inline int testandset (int *p)
394	{
395	int ret;
396	__asm__ __volatile__ (
397	"0: lwarx %0,0,%1\n"
398	" xor. %0,%3,%0\n"
399	" bne 1f\n"
400	" stwcx. %2,0,%1\n"
401	" bne- 0b\n"
402	"1: "
403	: "=&r" (ret)
404	: "r" (p), "r" (1), "r" (0)
405	: "cr0", "memory");
406	return ret;
407	}
408	#endif
409
410	#ifdef __i386__
411	static inline int testandset (int *p)
412	{
413	long int readval = 0;
414
415	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
416	: "+m" (*p), "+a" (readval)
417	: "r" (1)
418	: "cc");
419	return readval;
420	}
421	#endif
422
423	#ifdef __x86_64__
424	static inline int testandset (int *p)
425	{
426	long int readval = 0;
427
428	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
429	: "+m" (*p), "+a" (readval)
430	: "r" (1)
431	: "cc");
432	return readval;
433	}
434	#endif
435
436	#ifdef __s390__
437	static inline int testandset (int *p)
438	{
439	int ret;
440
441	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
442	" jl 0b"
443	: "=&d" (ret)
444	: "r" (1), "a" (p), "0" (*p)
445	: "cc", "memory" );
446	return ret;
447	}
448	#endif
449
450	#ifdef __alpha__
451	static inline int testandset (int *p)
452	{
453	int ret;
454	unsigned long one;
455
456	__asm__ __volatile__ ("0: mov 1,%2\n"
457	" ldl_l %0,%1\n"
458	" stl_c %2,%1\n"
459	" beq %2,1f\n"
460	".subsection 2\n"
461	"1: br 0b\n"
462	".previous"
463	: "=r" (ret), "=m" (*p), "=r" (one)
464	: "m" (*p));
465	return ret;
466	}
467	#endif
468
469	#ifdef __sparc__
470	static inline int testandset (int *p)
471	{
472	int ret;
473
474	__asm__ __volatile__("ldstub [%1], %0"
475	: "=r" (ret)
476	: "r" (p)
477	: "memory");
478
479	return (ret ? 1 : 0);
480	}
481	#endif
482
483	#ifdef __arm__
484	static inline int testandset (int *spinlock)
485	{
486	register unsigned int ret;
487	__asm__ __volatile__("swp %0, %1, [%2]"
488	: "=r"(ret)
489	: "0"(1), "r"(spinlock));
490
491	return ret;
492	}
493	#endif
494
495	#ifdef __mc68000
496	static inline int testandset (int *p)
497	{
498	char ret;
499	__asm__ __volatile__("tas %1; sne %0"
500	: "=r" (ret)
501	: "m" (p)
502	: "cc","memory");
503	return ret;
504	}
505	#endif
506
507	typedef int spinlock_t;
508
509	#define SPIN_LOCK_UNLOCKED 0
510
511	#if defined(CONFIG_USER_ONLY)
512	static inline void spin_lock(spinlock_t *lock)
513	{
514	while (testandset(lock));
515	}
516
517	static inline void spin_unlock(spinlock_t *lock)
518	{
519	*lock = 0;
520	}
521
522	static inline int spin_trylock(spinlock_t *lock)
523	{
524	return !testandset(lock);
525	}
526	#else
527	static inline void spin_lock(spinlock_t *lock)
528	{
529	}
530
531	static inline void spin_unlock(spinlock_t *lock)
532	{
533	}
534
535	static inline int spin_trylock(spinlock_t *lock)
536	{
537	return 1;
538	}
539	#endif
540
541	extern spinlock_t tb_lock;
542
543	extern int tb_invalidated_flag;
544
545	#if !defined(CONFIG_USER_ONLY)
546
547	void tlb_fill(target_ulong addr, int is_write, int is_user,
548	void *retaddr);
549
550	#define ACCESS_TYPE 3
551	#define MEMSUFFIX _code
552	#define env cpu_single_env
553
554	#define DATA_SIZE 1
555	#include "softmmu_header.h"
556
557	#define DATA_SIZE 2
558	#include "softmmu_header.h"
559
560	#define DATA_SIZE 4
561	#include "softmmu_header.h"
562
563	#define DATA_SIZE 8
564	#include "softmmu_header.h"
565
566	#undef ACCESS_TYPE
567	#undef MEMSUFFIX
568	#undef env
569
570	#endif
571
572	#if defined(CONFIG_USER_ONLY)
573	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
574	{
575	return addr;
576	}
577	#else
578	# ifdef VBOX
579	target_ulong remR3PhysGetPhysicalAddressCode(CPUState env, target_ulong addr, CPUTLBEntry pTLBEntry);
580	target_ulong remR3HCVirt2GCPhys(void env, void addr);
581	# endif
582	/* NOTE: this function can trigger an exception */
583	/* NOTE2: the returned address is not exactly the physical address: it
584	is the offset relative to phys_ram_base */
585	/* XXX: i386 target specific */
586	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
587	{
588	int is_user, index, pd;
589
590	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
591	#if defined(TARGET_I386)
592	is_user = ((env->hflags & HF_CPL_MASK) == 3);
593	#elif defined (TARGET_PPC)
594	is_user = msr_pr;
595	#elif defined (TARGET_SPARC)
596	is_user = (env->psrs == 0);
597	#else
598	#error "Unimplemented !"
599	#endif
600	if (__builtin_expect(env->tlb_read[is_user][index].address !=
601	(addr & TARGET_PAGE_MASK), 0)) {
602	ldub_code(addr);
603	}
604	pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
605	if (pd > IO_MEM_ROM) {
606	#ifdef VBOX
607	/* deal with non-MMIO access handlers. */
608	return remR3PhysGetPhysicalAddressCode(env, addr, &env->tlb_read[is_user][index]);
609	#else
610	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
611	#endif
612	}
613	#ifdef VBOX
614	return remR3HCVirt2GCPhys(env, (void *)(addr + env->tlb_read[is_user][index].addend));
615	#else
616	return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
617	#endif
618	}
619	#endif

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