| 1 | /*
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| 2 | * internal execution defines for qemu
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| 3 | *
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| 4 | * Copyright (c) 2003 Fabrice Bellard
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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| 18 | */
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| 19 |
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| 20 | /*
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| 21 | * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 22 | * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
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| 23 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 24 | * a choice of LGPL license versions is made available with the language indicating
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| 25 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 26 | * of the LGPL is applied is otherwise unspecified.
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| 27 | */
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| 28 |
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| 29 | #ifndef _EXEC_ALL_H_
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| 30 | #define _EXEC_ALL_H_
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| 31 |
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| 32 | #include "qemu-common.h"
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| 33 | #ifdef VBOX
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| 34 | # include <VBox/vmm/tm.h>
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| 35 | # include <VBox/vmm/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
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| 36 | # include <VBox/vmm/em.h> /* EMRemIsLockOwner */
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| 37 | # ifndef LOG_GROUP
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| 38 | # define LOG_GROUP LOG_GROUP_REM
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| 39 | # endif
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| 40 | # include <VBox/log.h>
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| 41 | # include "REMInternal.h"
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| 42 | # include <VBox/vmm/vm.h>
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| 43 | #endif /* VBOX */
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| 44 |
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| 45 | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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| 46 | #ifndef VBOX
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| 47 | #define DEBUG_DISAS
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| 48 | #endif /* !VBOX */
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| 49 |
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| 50 | /* Page tracking code uses ram addresses in system mode, and virtual
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| 51 | addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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| 52 | type. */
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| 53 | #if defined(CONFIG_USER_ONLY)
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| 54 | typedef abi_ulong tb_page_addr_t;
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| 55 | #else
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| 56 | typedef ram_addr_t tb_page_addr_t;
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| 57 | #endif
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| 58 |
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| 59 | /* is_jmp field values */
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| 60 | #define DISAS_NEXT 0 /* next instruction can be analyzed */
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| 61 | #define DISAS_JUMP 1 /* only pc was modified dynamically */
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| 62 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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| 63 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */
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| 64 |
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| 65 | typedef struct TranslationBlock TranslationBlock;
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| 66 |
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| 67 | /* XXX: make safe guess about sizes */
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| 68 | #define MAX_OP_PER_INSTR 96
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| 69 |
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| 70 | #if HOST_LONG_BITS == 32
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| 71 | #define MAX_OPC_PARAM_PER_ARG 2
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| 72 | #else
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| 73 | #define MAX_OPC_PARAM_PER_ARG 1
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| 74 | #endif
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| 75 | #define MAX_OPC_PARAM_IARGS 4
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| 76 | #define MAX_OPC_PARAM_OARGS 1
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| 77 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
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| 78 |
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| 79 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
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| 80 | * and up to 4 + N parameters on 64-bit archs
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| 81 | * (N = number of input arguments + output arguments). */
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| 82 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
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| 83 | #define OPC_BUF_SIZE 640
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| 84 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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| 85 |
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| 86 | /* Maximum size a TCG op can expand to. This is complicated because a
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| 87 | single op may require several host instructions and register reloads.
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| 88 | For now take a wild guess at 192 bytes, which should allow at least
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| 89 | a couple of fixup instructions per argument. */
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| 90 | #define TCG_MAX_OP_SIZE 192
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| 91 |
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| 92 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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| 93 |
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| 94 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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| 95 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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| 96 | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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| 97 |
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| 98 | #include "qemu-log.h"
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| 99 |
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| 100 | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
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| 101 | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
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| 102 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
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| 103 | uintptr_t searched_pc, int pc_pos, void *puc);
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| 104 |
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| 105 | void cpu_gen_init(void);
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| 106 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
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| 107 | int *gen_code_size_ptr);
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| 108 | int cpu_restore_state(struct TranslationBlock *tb,
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| 109 | CPUState *env, uintptr_t searched_pc,
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| 110 | void *puc);
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| 111 | void cpu_resume_from_signal(CPUState *env1, void *puc);
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| 112 | void cpu_io_recompile(CPUState *env, void *retaddr);
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| 113 | TranslationBlock *tb_gen_code(CPUState *env,
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| 114 | target_ulong pc, target_ulong cs_base, int flags,
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| 115 | int cflags);
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| 116 | void cpu_exec_init(CPUState *env);
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| 117 | void QEMU_NORETURN cpu_loop_exit(void);
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| 118 | int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
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| 119 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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| 120 | int is_cpu_write_access);
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| 121 | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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| 122 | void tlb_flush_page(CPUState *env, target_ulong addr);
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| 123 | void tlb_flush(CPUState *env, int flush_global);
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| 124 | #if !defined(CONFIG_USER_ONLY)
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| 125 | void tlb_set_page(CPUState *env, target_ulong vaddr,
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| 126 | target_phys_addr_t paddr, int prot,
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| 127 | int mmu_idx, target_ulong size);
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| 128 | #endif
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| 129 |
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| 130 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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| 131 |
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| 132 | #define CODE_GEN_PHYS_HASH_BITS 15
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| 133 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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| 134 |
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| 135 | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
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| 136 |
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| 137 | /* estimated block size for TB allocation */
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| 138 | /* XXX: use a per code average code fragment size and modulate it
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| 139 | according to the host CPU */
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| 140 | #if defined(CONFIG_SOFTMMU)
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| 141 | #define CODE_GEN_AVG_BLOCK_SIZE 128
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| 142 | #else
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| 143 | #define CODE_GEN_AVG_BLOCK_SIZE 64
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| 144 | #endif
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| 145 |
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| 146 | #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
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| 147 | #define USE_DIRECT_JUMP
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| 148 | #endif
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| 149 |
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| 150 | #ifdef VBOX /* bird: not safe in next step because of threading & cpu_interrupt. */
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| 151 | # undef USE_DIRECT_JUMP
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| 152 | #endif /* VBOX */
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| 153 |
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| 154 | struct TranslationBlock {
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| 155 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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| 156 | target_ulong cs_base; /* CS base for this block */
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| 157 | uint64_t flags; /* flags defining in which context the code was generated */
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| 158 | uint16_t size; /* size of target code for this block (1 <=
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| 159 | size <= TARGET_PAGE_SIZE) */
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| 160 | uint16_t cflags; /* compile flags */
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| 161 | #define CF_COUNT_MASK 0x7fff
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| 162 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
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| 163 | #ifdef VBOX
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| 164 | # define CF_RAW_MODE 0x0010 /* block was generated in raw mode */
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| 165 | #endif
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| 166 |
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| 167 | uint8_t *tc_ptr; /* pointer to the translated code */
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| 168 | /* next matching tb for physical address. */
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| 169 | struct TranslationBlock *phys_hash_next;
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| 170 | /* first and second physical page containing code. The lower bit
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| 171 | of the pointer tells the index in page_next[] */
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| 172 | struct TranslationBlock *page_next[2];
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| 173 | tb_page_addr_t page_addr[2];
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| 174 |
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| 175 | /* the following data are used to directly call another TB from
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| 176 | the code of this one. */
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| 177 | uint16_t tb_next_offset[2]; /* offset of original jump target */
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| 178 | #ifdef USE_DIRECT_JUMP
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| 179 | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
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| 180 | #else
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| 181 | uintptr_t tb_next[2]; /* address of jump generated code */
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| 182 | #endif
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| 183 | /* list of TBs jumping to this one. This is a circular list using
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| 184 | the two least significant bits of the pointers to tell what is
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| 185 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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| 186 | jmp_first */
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| 187 | struct TranslationBlock *jmp_next[2];
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| 188 | struct TranslationBlock *jmp_first;
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| 189 | uint32_t icount;
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| 190 | };
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| 191 |
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| 192 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
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| 193 | {
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| 194 | target_ulong tmp;
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| 195 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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| 196 | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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| 197 | }
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| 198 |
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| 199 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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| 200 | {
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| 201 | target_ulong tmp;
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| 202 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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| 203 | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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| 204 | | (tmp & TB_JMP_ADDR_MASK));
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| 205 | }
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| 206 |
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| 207 | static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
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| 208 | {
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| 209 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
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| 210 | }
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| 211 |
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| 212 | TranslationBlock *tb_alloc(target_ulong pc);
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| 213 | void tb_free(TranslationBlock *tb);
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| 214 | void tb_flush(CPUState *env);
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| 215 | void tb_link_page(TranslationBlock *tb,
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| 216 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
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| 217 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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| 218 |
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| 219 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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| 220 |
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| 221 | #if defined(USE_DIRECT_JUMP)
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| 222 |
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| 223 | #if defined(_ARCH_PPC)
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| 224 | extern void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
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| 225 | #define tb_set_jmp_target1 ppc_tb_set_jmp_target
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| 226 | #elif defined(__i386__) || defined(__x86_64__)
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| 227 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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| 228 | {
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| 229 | /* patch the branch destination */
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| 230 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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| 231 | /* no need to flush icache explicitly */
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| 232 | }
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| 233 | #elif defined(__arm__)
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| 234 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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| 235 | {
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| 236 | #if QEMU_GNUC_PREREQ(4, 1)
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| 237 | void __clear_cache(char *beg, char *end);
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| 238 | #else
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| 239 | register unsigned long _beg __asm ("a1");
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| 240 | register unsigned long _end __asm ("a2");
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| 241 | register unsigned long _flg __asm ("a3");
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| 242 | #endif
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| 243 |
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| 244 | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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| 245 | *(uint32_t *)jmp_addr =
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| 246 | (*(uint32_t *)jmp_addr & ~0xffffff)
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| 247 | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
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| 248 |
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| 249 | #if QEMU_GNUC_PREREQ(4, 1)
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| 250 | __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
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| 251 | #else
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| 252 | /* flush icache */
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| 253 | _beg = jmp_addr;
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| 254 | _end = jmp_addr + 4;
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| 255 | _flg = 0;
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| 256 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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| 257 | #endif
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| 258 | }
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| 259 | #endif
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| 260 |
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| 261 | static inline void tb_set_jmp_target(TranslationBlock *tb,
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| 262 | int n, uintptr_t addr)
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| 263 | {
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| 264 | uintptr_t offset;
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| 265 |
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| 266 | offset = tb->tb_jmp_offset[n];
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| 267 | tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
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| 268 | }
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| 269 |
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| 270 | #else
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| 271 |
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| 272 | /* set the jump target */
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| 273 | static inline void tb_set_jmp_target(TranslationBlock *tb,
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| 274 | int n, uintptr_t addr)
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| 275 | {
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| 276 | tb->tb_next[n] = addr;
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| 277 | }
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| 278 |
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| 279 | #endif
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| 280 |
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| 281 | static inline void tb_add_jump(TranslationBlock *tb, int n,
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| 282 | TranslationBlock *tb_next)
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| 283 | {
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| 284 | /* NOTE: this test is only needed for thread safety */
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| 285 | if (!tb->jmp_next[n]) {
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| 286 | /* patch the native jump address */
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| 287 | tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
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| 288 |
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| 289 | /* add in TB jmp circular list */
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| 290 | tb->jmp_next[n] = tb_next->jmp_first;
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| 291 | tb_next->jmp_first = (TranslationBlock *)((intptr_t)(tb) | (n));
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| 292 | }
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| 293 | }
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| 294 |
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| 295 | TranslationBlock *tb_find_pc(uintptr_t pc_ptr);
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| 296 |
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| 297 | #include "qemu-lock.h"
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| 298 |
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| 299 | extern spinlock_t tb_lock;
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| 300 |
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| 301 | extern int tb_invalidated_flag;
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| 302 |
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| 303 | #if !defined(CONFIG_USER_ONLY)
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| 304 |
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| 305 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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| 306 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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| 307 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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| 308 |
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| 309 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
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| 310 | void *retaddr);
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| 311 |
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| 312 | #include "softmmu_defs.h"
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| 313 |
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| 314 | #define ACCESS_TYPE (NB_MMU_MODES + 1)
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| 315 | #define MEMSUFFIX _code
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| 316 | #define env cpu_single_env
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| 317 |
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| 318 | #define DATA_SIZE 1
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| 319 | #include "softmmu_header.h"
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| 320 |
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| 321 | #define DATA_SIZE 2
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| 322 | #include "softmmu_header.h"
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| 323 |
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| 324 | #define DATA_SIZE 4
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| 325 | #include "softmmu_header.h"
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| 326 |
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| 327 | #define DATA_SIZE 8
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| 328 | #include "softmmu_header.h"
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| 329 |
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| 330 | #undef ACCESS_TYPE
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| 331 | #undef MEMSUFFIX
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| 332 | #undef env
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| 333 |
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| 334 | #endif
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| 335 |
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| 336 | #if defined(CONFIG_USER_ONLY)
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| 337 | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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| 338 | {
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| 339 | return addr;
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| 340 | }
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| 341 | #else
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| 342 | # ifdef VBOX
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| 343 | target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry, target_phys_addr_t ioTLBEntry);
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| 344 | # endif
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| 345 | /* NOTE: this function can trigger an exception */
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| 346 | /* NOTE2: the returned address is not exactly the physical address: it
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| 347 | is the offset relative to phys_ram_base */
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| 348 | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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| 349 | {
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| 350 | int mmu_idx, page_index, pd;
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| 351 | # ifndef VBOX
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| 352 | void *p;
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| 353 | # endif
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| 354 |
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| 355 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 356 | mmu_idx = cpu_mmu_index(env1);
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| 357 | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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| 358 | (addr & TARGET_PAGE_MASK))) {
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| 359 | ldub_code(addr);
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| 360 | }
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| 361 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
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| 362 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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| 363 | # ifdef VBOX
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| 364 | /* deal with non-MMIO access handlers. */
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| 365 | return remR3PhysGetPhysicalAddressCode(env1, addr,
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| 366 | &env1->tlb_table[mmu_idx][page_index],
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| 367 | env1->iotlb[mmu_idx][page_index]);
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| 368 | # elif defined(TARGET_SPARC) || defined(TARGET_MIPS)
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| 369 | do_unassigned_access(addr, 0, 1, 0, 4);
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| 370 | #else
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| 371 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
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| 372 | #endif
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| 373 | }
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| 374 | # if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
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| 375 | return addr + env1->tlb_table[mmu_idx][page_index].addend;
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| 376 | # elif defined(VBOX)
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| 377 | Assert(env1->phys_addends[mmu_idx][page_index] != -1);
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| 378 | return addr + env1->phys_addends[mmu_idx][page_index];
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| 379 | # else
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| 380 | p = (void *)(uintptr_t)addr
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| 381 | + env1->tlb_table[mmu_idx][page_index].addend;
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| 382 | return qemu_ram_addr_from_host(p);
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| 383 | # endif
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| 384 | }
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| 385 | #endif
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| 386 |
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| 387 | typedef void (CPUDebugExcpHandler)(CPUState *env);
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| 388 |
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| 389 | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
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| 390 |
|
|---|
| 391 | #ifndef VBOX
|
|---|
| 392 | /* vl.c */
|
|---|
| 393 | extern int singlestep;
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|---|
| 394 |
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|---|
| 395 | /* cpu-exec.c */
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|---|
| 396 | extern volatile sig_atomic_t exit_request;
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|---|
| 397 | #endif /*!VBOX*/
|
|---|
| 398 |
|
|---|
| 399 |
|
|---|
| 400 | #endif
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