exec-all.h@ 109

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1	/*
2	* internal execution defines for qemu
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20
21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
22	#ifndef VBOX
23	#define DEBUG_DISAS
24	#endif
25
26	#ifdef VBOX
27	# include <VBox/tm.h>
28	# ifndef LOG_GROUP
29	# define LOG_GROUP LOG_GROUP_REM
30	# endif
31	# include <VBox/log.h>
32	# include "REMInternal.h"
33	# include <VBox/vm.h>
34	#endif /* VBOX */
35
36	#ifndef glue
37	#define xglue(x, y) x ## y
38	#define glue(x, y) xglue(x, y)
39	#define stringify(s) tostring(s)
40	#define tostring(s) #s
41	#endif
42
43	#if __GNUC__ < 3
44	#define __builtin_expect(x, n) (x)
45	#endif
46
47	#ifdef __i386__
48	#define REGPARM(n) __attribute((regparm(n)))
49	#else
50	#define REGPARM(n)
51	#endif
52
53	/* is_jmp field values */
54	#define DISAS_NEXT 0 /* next instruction can be analyzed */
55	#define DISAS_JUMP 1 /* only pc was modified dynamically */
56	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
57	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
58
59	struct TranslationBlock;
60
61	/* XXX: make safe guess about sizes */
62	#define MAX_OP_PER_INSTR 32
63	#define OPC_BUF_SIZE 512
64	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
65
66	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
67
68	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
69	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
70	extern long gen_labels[OPC_BUF_SIZE];
71	extern int nb_gen_labels;
72	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
73	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
74	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
75	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
76	extern target_ulong gen_opc_jump_pc[2];
77	extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
78
79	typedef void (GenOpFunc)(void);
80	typedef void (GenOpFunc1)(long);
81	typedef void (GenOpFunc2)(long, long);
82	typedef void (GenOpFunc3)(long, long, long);
83
84	#if defined(TARGET_I386)
85
86	void optimize_flags_init(void);
87
88	#endif
89
90	extern FILE *logfile;
91	extern int loglevel;
92
93	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
94	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
95	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
96	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
97	int max_code_size, int *gen_code_size_ptr);
98	int cpu_restore_state(struct TranslationBlock *tb,
99	CPUState *env, unsigned long searched_pc,
100	void *puc);
101	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
102	int max_code_size, int *gen_code_size_ptr);
103	int cpu_restore_state_copy(struct TranslationBlock *tb,
104	CPUState *env, unsigned long searched_pc,
105	void *puc);
106	void cpu_resume_from_signal(CPUState env1, void puc);
107	void cpu_exec_init(CPUState *env);
108	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
109	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
110	int is_cpu_write_access);
111	void tb_invalidate_page_range(target_ulong start, target_ulong end);
112	void tlb_flush_page(CPUState *env, target_ulong addr);
113	void tlb_flush(CPUState *env, int flush_global);
114	int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
115	target_phys_addr_t paddr, int prot,
116	int is_user, int is_softmmu);
117	static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
118	target_phys_addr_t paddr, int prot,
119	int is_user, int is_softmmu)
120	{
121	if (prot & PAGE_READ)
122	prot \|= PAGE_EXEC;
123	return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
124	}
125
126	#define CODE_GEN_MAX_SIZE 65536
127	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
128
129	#define CODE_GEN_PHYS_HASH_BITS 15
130	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
131
132	/* maximum total translate dcode allocated */
133
134	/* NOTE: the translated code area cannot be too big because on some
135	archs the range of "fast" function calls is limited. Here is a
136	summary of the ranges:
137
138	i386 : signed 32 bits
139	arm : signed 26 bits
140	ppc : signed 24 bits
141	sparc : signed 32 bits
142	alpha : signed 23 bits
143	*/
144
145	#if defined(__alpha__)
146	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
147	#elif defined(__ia64)
148	#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
149	#elif defined(__powerpc__)
150	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
151	#else
152	#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
153	#endif
154
155	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
156
157	/* estimated block size for TB allocation */
158	/* XXX: use a per code average code fragment size and modulate it
159	according to the host CPU */
160	#if defined(CONFIG_SOFTMMU)
161	#define CODE_GEN_AVG_BLOCK_SIZE 128
162	#else
163	#define CODE_GEN_AVG_BLOCK_SIZE 64
164	#endif
165
166	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
167
168	#if defined(__powerpc__)
169	#define USE_DIRECT_JUMP
170	#endif
171	#if defined(__i386__) && !defined(_WIN32)
172	#define USE_DIRECT_JUMP
173	#endif
174	#ifdef VBOX /* bird: not safe in next step because of threading & cpu_interrupt. */
175	#undef USE_DIRECT_JUMP
176	#endif /* VBOX */
177
178	typedef struct TranslationBlock {
179	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
180	target_ulong cs_base; /* CS base for this block */
181	unsigned int flags; /* flags defining in which context the code was generated */
182	uint16_t size; /* size of target code for this block (1 <=
183	size <= TARGET_PAGE_SIZE) */
184	uint16_t cflags; /* compile flags */
185	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
186	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
187	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
188	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
189	#ifdef VBOX
190	#define CF_RAW_MODE 0x0010 /* block was generated in raw mode */
191	#endif
192
193	uint8_t tc_ptr; / pointer to the translated code */
194	/* next matching tb for physical address. */
195	struct TranslationBlock *phys_hash_next;
196	/* first and second physical page containing code. The lower bit
197	of the pointer tells the index in page_next[] */
198	struct TranslationBlock *page_next[2];
199	target_ulong page_addr[2];
200
201	/* the following data are used to directly call another TB from
202	the code of this one. */
203	uint16_t tb_next_offset[2]; /* offset of original jump target */
204	#ifdef USE_DIRECT_JUMP
205	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
206	#else
207	uint32_t tb_next[2]; /* address of jump generated code */
208	#endif
209	/* list of TBs jumping to this one. This is a circular list using
210	the two least significant bits of the pointers to tell what is
211	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
212	jmp_first */
213	struct TranslationBlock *jmp_next[2];
214	struct TranslationBlock *jmp_first;
215	} TranslationBlock;
216
217	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
218	{
219	target_ulong tmp;
220	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
221	return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
222	}
223
224	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
225	{
226	target_ulong tmp;
227	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
228	return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) \|
229	(tmp & TB_JMP_ADDR_MASK));
230	}
231
232	static inline unsigned int tb_phys_hash_func(unsigned long pc)
233	{
234	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
235	}
236
237	TranslationBlock *tb_alloc(target_ulong pc);
238	void tb_flush(CPUState *env);
239	void tb_link_phys(TranslationBlock *tb,
240	target_ulong phys_pc, target_ulong phys_page2);
241
242	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
243
244	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
245	extern uint8_t *code_gen_ptr;
246
247	#if defined(USE_DIRECT_JUMP)
248
249	#if defined(__powerpc__)
250	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
251	{
252	uint32_t val, *ptr;
253
254	/* patch the branch destination */
255	ptr = (uint32_t *)jmp_addr;
256	val = *ptr;
257	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
258	*ptr = val;
259	/* flush icache */
260	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
261	asm volatile ("sync" : : : "memory");
262	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
263	asm volatile ("sync" : : : "memory");
264	asm volatile ("isync" : : : "memory");
265	}
266	#elif defined(__i386__)
267	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
268	{
269	/* patch the branch destination */
270	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
271	/* no need to flush icache explicitely */
272	}
273	#endif
274
275	static inline void tb_set_jmp_target(TranslationBlock *tb,
276	int n, unsigned long addr)
277	{
278	unsigned long offset;
279
280	offset = tb->tb_jmp_offset[n];
281	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
282	offset = tb->tb_jmp_offset[n + 2];
283	if (offset != 0xffff)
284	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
285	}
286
287	#else
288
289	/* set the jump target */
290	static inline void tb_set_jmp_target(TranslationBlock *tb,
291	int n, unsigned long addr)
292	{
293	tb->tb_next[n] = addr;
294	}
295
296	#endif
297
298	static inline void tb_add_jump(TranslationBlock *tb, int n,
299	TranslationBlock *tb_next)
300	{
301	/* NOTE: this test is only needed for thread safety */
302	if (!tb->jmp_next[n]) {
303	/* patch the native jump address */
304	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
305
306	/* add in TB jmp circular list */
307	tb->jmp_next[n] = tb_next->jmp_first;
308	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
309	}
310	}
311
312	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
313
314	#ifndef offsetof
315	#define offsetof(type, field) ((size_t) &((type *)0)->field)
316	#endif
317
318	#if defined(_WIN32)
319	#define ASM_DATA_SECTION ".section \".data\"\n"
320	#define ASM_PREVIOUS_SECTION ".section .text\n"
321	#elif defined(__APPLE__)
322	#define ASM_DATA_SECTION ".data\n"
323	#define ASM_PREVIOUS_SECTION ".text\n"
324	#else
325	#define ASM_DATA_SECTION ".section \".data\"\n"
326	#define ASM_PREVIOUS_SECTION ".previous\n"
327	#endif
328
329	#define ASM_OP_LABEL_NAME(n, opname) \
330	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
331
332	#if defined(__powerpc__)
333
334	/* we patch the jump instruction directly */
335	#define GOTO_TB(opname, tbparam, n)\
336	do {\
337	asm volatile (ASM_DATA_SECTION\
338	ASM_OP_LABEL_NAME(n, opname) ":\n"\
339	".long 1f\n"\
340	ASM_PREVIOUS_SECTION \
341	"b " ASM_NAME(__op_jmp) #n "\n"\
342	"1:\n");\
343	} while (0)
344
345	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
346
347	/* we patch the jump instruction directly */
348	#define GOTO_TB(opname, tbparam, n)\
349	do {\
350	asm volatile (".section .data\n"\
351	ASM_OP_LABEL_NAME(n, opname) ":\n"\
352	".long 1f\n"\
353	ASM_PREVIOUS_SECTION \
354	"jmp " ASM_NAME(__op_jmp) #n "\n"\
355	"1:\n");\
356	} while (0)
357
358	#else
359
360	/* jump to next block operations (more portable code, does not need
361	cache flushing, but slower because of indirect jump) */
362	# ifdef VBOX /* bird: GCC4 (and Ming 3.4.x?) will remove the two unused static
363	variables. I've added a dummy __asm__ statement which reference
364	the two variables to prevent this. */
365	#define GOTO_TB(opname, tbparam, n)\
366	do {\
367	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
368	static void __attribute__((unused)) *__op_label ## n \
369	__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
370	__asm__ ("" : : "m" (__op_label ## n), "m" (dummy ## n));\
371	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
372	label ## n: ;\
373	dummy_label ## n: ;\
374	} while (0)
375	# else /* !VBOX */
376	#define GOTO_TB(opname, tbparam, n)\
377	do {\
378	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
379	static void __attribute__((unused)) *__op_label ## n \
380	__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
381	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
382	label ## n: ;\
383	dummy_label ## n: ;\
384	} while (0)
385	# endif /* !VBOX */
386
387	#endif
388
389	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
390	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
391	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
392
393	#ifdef __powerpc__
394	static inline int testandset (int *p)
395	{
396	int ret;
397	__asm__ __volatile__ (
398	"0: lwarx %0,0,%1\n"
399	" xor. %0,%3,%0\n"
400	" bne 1f\n"
401	" stwcx. %2,0,%1\n"
402	" bne- 0b\n"
403	"1: "
404	: "=&r" (ret)
405	: "r" (p), "r" (1), "r" (0)
406	: "cr0", "memory");
407	return ret;
408	}
409	#endif
410
411	#ifdef __i386__
412	static inline int testandset (int *p)
413	{
414	long int readval = 0;
415
416	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
417	: "+m" (*p), "+a" (readval)
418	: "r" (1)
419	: "cc");
420	return readval;
421	}
422	#endif
423
424	#ifdef __x86_64__
425	static inline int testandset (int *p)
426	{
427	long int readval = 0;
428
429	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
430	: "+m" (*p), "+a" (readval)
431	: "r" (1)
432	: "cc");
433	return readval;
434	}
435	#endif
436
437	#ifdef __s390__
438	static inline int testandset (int *p)
439	{
440	int ret;
441
442	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
443	" jl 0b"
444	: "=&d" (ret)
445	: "r" (1), "a" (p), "0" (*p)
446	: "cc", "memory" );
447	return ret;
448	}
449	#endif
450
451	#ifdef __alpha__
452	static inline int testandset (int *p)
453	{
454	int ret;
455	unsigned long one;
456
457	__asm__ __volatile__ ("0: mov 1,%2\n"
458	" ldl_l %0,%1\n"
459	" stl_c %2,%1\n"
460	" beq %2,1f\n"
461	".subsection 2\n"
462	"1: br 0b\n"
463	".previous"
464	: "=r" (ret), "=m" (*p), "=r" (one)
465	: "m" (*p));
466	return ret;
467	}
468	#endif
469
470	#ifdef __sparc__
471	static inline int testandset (int *p)
472	{
473	int ret;
474
475	__asm__ __volatile__("ldstub [%1], %0"
476	: "=r" (ret)
477	: "r" (p)
478	: "memory");
479
480	return (ret ? 1 : 0);
481	}
482	#endif
483
484	#ifdef __arm__
485	static inline int testandset (int *spinlock)
486	{
487	register unsigned int ret;
488	__asm__ __volatile__("swp %0, %1, [%2]"
489	: "=r"(ret)
490	: "0"(1), "r"(spinlock));
491
492	return ret;
493	}
494	#endif
495
496	#ifdef __mc68000
497	static inline int testandset (int *p)
498	{
499	char ret;
500	__asm__ __volatile__("tas %1; sne %0"
501	: "=r" (ret)
502	: "m" (p)
503	: "cc","memory");
504	return ret;
505	}
506	#endif
507
508	#ifdef __ia64
509	#include <ia64intrin.h>
510
511	static inline int testandset (int *p)
512	{
513	return __sync_lock_test_and_set (p, 1);
514	}
515	#endif
516
517	typedef int spinlock_t;
518
519	#define SPIN_LOCK_UNLOCKED 0
520
521	#if defined(CONFIG_USER_ONLY)
522	static inline void spin_lock(spinlock_t *lock)
523	{
524	while (testandset(lock));
525	}
526
527	static inline void spin_unlock(spinlock_t *lock)
528	{
529	*lock = 0;
530	}
531
532	static inline int spin_trylock(spinlock_t *lock)
533	{
534	return !testandset(lock);
535	}
536	#else
537	static inline void spin_lock(spinlock_t *lock)
538	{
539	}
540
541	static inline void spin_unlock(spinlock_t *lock)
542	{
543	}
544
545	static inline int spin_trylock(spinlock_t *lock)
546	{
547	return 1;
548	}
549	#endif
550
551	extern spinlock_t tb_lock;
552
553	extern int tb_invalidated_flag;
554
555	#if !defined(CONFIG_USER_ONLY)
556
557	void tlb_fill(target_ulong addr, int is_write, int is_user,
558	void *retaddr);
559
560	#define ACCESS_TYPE 3
561	#define MEMSUFFIX _code
562	#define env cpu_single_env
563
564	#define DATA_SIZE 1
565	#include "softmmu_header.h"
566
567	#define DATA_SIZE 2
568	#include "softmmu_header.h"
569
570	#define DATA_SIZE 4
571	#include "softmmu_header.h"
572
573	#define DATA_SIZE 8
574	#include "softmmu_header.h"
575
576	#undef ACCESS_TYPE
577	#undef MEMSUFFIX
578	#undef env
579
580	#endif
581
582	#if defined(CONFIG_USER_ONLY)
583	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
584	{
585	return addr;
586	}
587	#else
588	# ifdef VBOX
589	target_ulong remR3PhysGetPhysicalAddressCode(CPUState env, target_ulong addr, CPUTLBEntry pTLBEntry);
590	# endif
591	/* NOTE: this function can trigger an exception */
592	/* NOTE2: the returned address is not exactly the physical address: it
593	is the offset relative to phys_ram_base */
594	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
595	{
596	int is_user, index, pd;
597
598	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
599	#if defined(TARGET_I386)
600	is_user = ((env->hflags & HF_CPL_MASK) == 3);
601	#elif defined (TARGET_PPC)
602	is_user = msr_pr;
603	#elif defined (TARGET_MIPS)
604	is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
605	#elif defined (TARGET_SPARC)
606	is_user = (env->psrs == 0);
607	#elif defined (TARGET_ARM)
608	is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
609	#elif defined (TARGET_SH4)
610	is_user = ((env->sr & SR_MD) == 0);
611	#else
612	#error unimplemented CPU
613	#endif
614	if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
615	(addr & TARGET_PAGE_MASK), 0)) {
616	ldub_code(addr);
617	}
618	pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
619	if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
620	#ifdef VBOX
621	/* deal with non-MMIO access handlers. */
622	return remR3PhysGetPhysicalAddressCode(env, addr, &env->tlb_table[is_user][index]);
623	#else
624	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
625	#endif
626	}
627	return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
628	}
629	#endif
630
631
632	#ifdef USE_KQEMU
633	#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG \| CODE_DIRTY_FLAG))
634
635	int kqemu_init(CPUState *env);
636	int kqemu_cpu_exec(CPUState *env);
637	void kqemu_flush_page(CPUState *env, target_ulong addr);
638	void kqemu_flush(CPUState *env, int global);
639	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
640	void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
641	void kqemu_cpu_interrupt(CPUState *env);
642	void kqemu_record_dump(void);
643
644	static inline int kqemu_is_ok(CPUState *env)
645	{
646	return(env->kqemu_enabled &&
647	(env->cr[0] & CR0_PE_MASK) &&
648	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
649	(env->eflags & IF_MASK) &&
650	!(env->eflags & VM_MASK) &&
651	(env->kqemu_enabled == 2 \|\|
652	((env->hflags & HF_CPL_MASK) == 3 &&
653	(env->eflags & IOPL_MASK) != IOPL_MASK)));
654	}
655
656	#endif

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source: vbox/trunk/src/recompiler/new/exec-all.h@ 109

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