| 1 | /*
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| 2 | * Software MMU support
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| 3 | *
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| 4 | * Copyright (c) 2003 Fabrice Bellard
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with this library; if not, write to the Free Software
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| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 19 | */
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| 20 | #if DATA_SIZE == 8
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| 21 | #define SUFFIX q
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| 22 | #define USUFFIX q
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| 23 | #define DATA_TYPE uint64_t
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| 24 | #elif DATA_SIZE == 4
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| 25 | #define SUFFIX l
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| 26 | #define USUFFIX l
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| 27 | #define DATA_TYPE uint32_t
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| 28 | #elif DATA_SIZE == 2
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| 29 | #define SUFFIX w
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| 30 | #define USUFFIX uw
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| 31 | #define DATA_TYPE uint16_t
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| 32 | #define DATA_STYPE int16_t
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| 33 | #elif DATA_SIZE == 1
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| 34 | #define SUFFIX b
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| 35 | #define USUFFIX ub
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| 36 | #define DATA_TYPE uint8_t
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| 37 | #define DATA_STYPE int8_t
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| 38 | #else
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| 39 | #error unsupported data size
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| 40 | #endif
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| 41 |
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| 42 | #if ACCESS_TYPE == 0
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| 43 |
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| 44 | #define CPU_MEM_INDEX 0
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| 45 | #define MMUSUFFIX _mmu
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| 46 |
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| 47 | #elif ACCESS_TYPE == 1
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| 48 |
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| 49 | #define CPU_MEM_INDEX 1
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| 50 | #define MMUSUFFIX _mmu
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| 51 |
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| 52 | #elif ACCESS_TYPE == 2
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| 53 |
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| 54 | #ifdef TARGET_I386
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| 55 | #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
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| 56 | #elif defined (TARGET_PPC)
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| 57 | #define CPU_MEM_INDEX (msr_pr)
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| 58 | #elif defined (TARGET_MIPS)
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| 59 | #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
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| 60 | #elif defined (TARGET_SPARC)
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| 61 | #define CPU_MEM_INDEX ((env->psrs) == 0)
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| 62 | #elif defined (TARGET_ARM)
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| 63 | #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
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| 64 | #elif defined (TARGET_SH4)
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| 65 | #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
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| 66 | #else
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| 67 | #error unsupported CPU
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| 68 | #endif
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| 69 | #define MMUSUFFIX _mmu
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| 70 |
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| 71 | #elif ACCESS_TYPE == 3
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| 72 |
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| 73 | #ifdef TARGET_I386
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| 74 | #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
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| 75 | #elif defined (TARGET_PPC)
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| 76 | #define CPU_MEM_INDEX (msr_pr)
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| 77 | #elif defined (TARGET_MIPS)
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| 78 | #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
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| 79 | #elif defined (TARGET_SPARC)
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| 80 | #define CPU_MEM_INDEX ((env->psrs) == 0)
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| 81 | #elif defined (TARGET_ARM)
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| 82 | #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
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| 83 | #elif defined (TARGET_SH4)
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| 84 | #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
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| 85 | #else
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| 86 | #error unsupported CPU
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| 87 | #endif
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| 88 | #define MMUSUFFIX _cmmu
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| 89 |
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| 90 | #else
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| 91 | #error invalid ACCESS_TYPE
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| 92 | #endif
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| 93 |
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| 94 | #if DATA_SIZE == 8
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| 95 | #define RES_TYPE uint64_t
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| 96 | #else
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| 97 | #define RES_TYPE int
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| 98 | #endif
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| 99 |
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| 100 | #if ACCESS_TYPE == 3
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| 101 | #define ADDR_READ addr_code
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| 102 | #else
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| 103 | #define ADDR_READ addr_read
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| 104 | #endif
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| 105 |
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| 106 | DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 107 | int is_user);
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| 108 | void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
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| 109 |
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| 110 | #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
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| 111 | (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU) && (!defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB))
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| 112 |
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| 113 | #define CPU_TLB_ENTRY_BITS 4
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| 114 |
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| 115 | static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
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| 116 | {
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| 117 | int res;
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| 118 |
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| 119 | asm volatile ("movl %1, %%edx\n"
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| 120 | "movl %1, %%eax\n"
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| 121 | "shrl %3, %%edx\n"
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| 122 | "andl %4, %%eax\n"
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| 123 | "andl %2, %%edx\n"
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| 124 | "leal %5(%%edx, %%ebp), %%edx\n"
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| 125 | "cmpl (%%edx), %%eax\n"
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| 126 | "movl %1, %%eax\n"
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| 127 | "je 1f\n"
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| 128 | "pushl %6\n"
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| 129 | "call %7\n"
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| 130 | "popl %%edx\n"
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| 131 | "movl %%eax, %0\n"
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| 132 | "jmp 2f\n"
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| 133 | "1:\n"
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| 134 | "addl 12(%%edx), %%eax\n"
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| 135 | #if DATA_SIZE == 1
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| 136 | "movzbl (%%eax), %0\n"
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| 137 | #elif DATA_SIZE == 2
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| 138 | "movzwl (%%eax), %0\n"
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| 139 | #elif DATA_SIZE == 4
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| 140 | "movl (%%eax), %0\n"
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| 141 | #else
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| 142 | #error unsupported size
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| 143 | #endif
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| 144 | "2:\n"
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| 145 | : "=r" (res)
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| 146 | : "r" (ptr),
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| 147 | "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
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| 148 | "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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| 149 | "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
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| 150 | "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
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| 151 | "i" (CPU_MEM_INDEX),
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| 152 | "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
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| 153 | : "%eax", "%ecx", "%edx", "memory", "cc");
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| 154 | return res;
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| 155 | }
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| 156 |
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| 157 | #if DATA_SIZE <= 2
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| 158 | static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
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| 159 | {
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| 160 | int res;
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| 161 |
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| 162 | asm volatile ("movl %1, %%edx\n"
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| 163 | "movl %1, %%eax\n"
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| 164 | "shrl %3, %%edx\n"
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| 165 | "andl %4, %%eax\n"
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| 166 | "andl %2, %%edx\n"
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| 167 | "leal %5(%%edx, %%ebp), %%edx\n"
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| 168 | "cmpl (%%edx), %%eax\n"
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| 169 | "movl %1, %%eax\n"
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| 170 | "je 1f\n"
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| 171 | "pushl %6\n"
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| 172 | "call %7\n"
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| 173 | "popl %%edx\n"
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| 174 | #if DATA_SIZE == 1
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| 175 | "movsbl %%al, %0\n"
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| 176 | #elif DATA_SIZE == 2
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| 177 | "movswl %%ax, %0\n"
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| 178 | #else
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| 179 | #error unsupported size
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| 180 | #endif
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| 181 | "jmp 2f\n"
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| 182 | "1:\n"
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| 183 | "addl 12(%%edx), %%eax\n"
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| 184 | #if DATA_SIZE == 1
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| 185 | "movsbl (%%eax), %0\n"
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| 186 | #elif DATA_SIZE == 2
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| 187 | "movswl (%%eax), %0\n"
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| 188 | #else
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| 189 | #error unsupported size
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| 190 | #endif
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| 191 | "2:\n"
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| 192 | : "=r" (res)
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| 193 | : "r" (ptr),
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| 194 | "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
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| 195 | "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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| 196 | "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
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| 197 | "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
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| 198 | "i" (CPU_MEM_INDEX),
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| 199 | "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
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| 200 | : "%eax", "%ecx", "%edx", "memory", "cc");
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| 201 | return res;
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| 202 | }
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| 203 | #endif
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| 204 |
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| 205 | #ifdef VBOX
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| 206 | /* generic store macro */
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| 207 |
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| 208 | static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
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| 209 | {
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| 210 | int index;
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| 211 | target_ulong addr;
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| 212 | unsigned long physaddr;
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| 213 | int is_user;
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| 214 |
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| 215 | addr = ptr;
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| 216 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 217 | is_user = CPU_MEM_INDEX;
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| 218 | if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
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| 219 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
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| 220 | glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
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| 221 | } else {
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| 222 | physaddr = addr + env->tlb_table[is_user][index].addend;
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| 223 | glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
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| 224 | }
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| 225 | }
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| 226 |
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| 227 | #else /* !VBOX */
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| 228 |
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| 229 | static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
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| 230 | {
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| 231 | asm volatile ("movl %0, %%edx\n"
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| 232 | "movl %0, %%eax\n"
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| 233 | "shrl %3, %%edx\n"
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| 234 | "andl %4, %%eax\n"
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| 235 | "andl %2, %%edx\n"
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| 236 | "leal %5(%%edx, %%ebp), %%edx\n"
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| 237 | "cmpl (%%edx), %%eax\n"
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| 238 | "movl %0, %%eax\n"
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| 239 | "je 1f\n"
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| 240 | #if DATA_SIZE == 1
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| 241 | "movzbl %b1, %%edx\n"
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| 242 | #elif DATA_SIZE == 2
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| 243 | "movzwl %w1, %%edx\n"
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| 244 | #elif DATA_SIZE == 4
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| 245 | "movl %1, %%edx\n"
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| 246 | #else
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| 247 | #error unsupported size
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| 248 | #endif
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| 249 | "pushl %6\n"
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| 250 | "call %7\n"
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| 251 | "popl %%eax\n"
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| 252 | "jmp 2f\n"
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| 253 | "1:\n"
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| 254 | "addl 8(%%edx), %%eax\n"
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| 255 | #if DATA_SIZE == 1
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| 256 | "movb %b1, (%%eax)\n"
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| 257 | #elif DATA_SIZE == 2
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| 258 | "movw %w1, (%%eax)\n"
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| 259 | #elif DATA_SIZE == 4
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| 260 | "movl %1, (%%eax)\n"
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| 261 | #else
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| 262 | #error unsupported size
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| 263 | #endif
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| 264 | "2:\n"
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| 265 | :
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| 266 | : "r" (ptr),
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| 267 | /* NOTE: 'q' would be needed as constraint, but we could not use it
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| 268 | with T1 ! */
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| 269 | "r" (v),
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| 270 | "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
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| 271 | "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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| 272 | "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
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| 273 | "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
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| 274 | "i" (CPU_MEM_INDEX),
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| 275 | "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
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| 276 | : "%eax", "%ecx", "%edx", "memory", "cc");
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| 277 | }
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| 278 | #endif /* !VBOX */
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| 279 |
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| 280 | #else
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| 281 |
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| 282 | /* generic load/store macros */
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| 283 |
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| 284 | static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
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| 285 | {
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| 286 | int index;
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| 287 | RES_TYPE res;
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| 288 | target_ulong addr;
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| 289 | unsigned long physaddr;
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| 290 | int is_user;
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| 291 |
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| 292 | addr = ptr;
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| 293 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 294 | is_user = CPU_MEM_INDEX;
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| 295 | if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
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| 296 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
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| 297 | res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
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| 298 | } else {
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| 299 | physaddr = addr + env->tlb_table[is_user][index].addend;
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| 300 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
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| 301 | }
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| 302 | return res;
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| 303 | }
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| 304 |
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| 305 | #if DATA_SIZE <= 2
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| 306 | static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
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| 307 | {
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| 308 | int res, index;
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| 309 | target_ulong addr;
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| 310 | unsigned long physaddr;
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| 311 | int is_user;
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| 312 |
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| 313 | addr = ptr;
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| 314 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 315 | is_user = CPU_MEM_INDEX;
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| 316 | if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
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| 317 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
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| 318 | res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
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| 319 | } else {
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| 320 | physaddr = addr + env->tlb_table[is_user][index].addend;
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| 321 | res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
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| 322 | }
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| 323 | return res;
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| 324 | }
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| 325 | #endif
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| 326 |
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| 327 | #if ACCESS_TYPE != 3
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| 328 |
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| 329 | /* generic store macro */
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| 330 |
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| 331 | static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
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| 332 | {
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| 333 | int index;
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| 334 | target_ulong addr;
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| 335 | unsigned long physaddr;
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| 336 | int is_user;
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| 337 |
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| 338 | addr = ptr;
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| 339 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 340 | is_user = CPU_MEM_INDEX;
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| 341 | if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
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| 342 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
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| 343 | glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
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| 344 | } else {
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| 345 | physaddr = addr + env->tlb_table[is_user][index].addend;
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| 346 | glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
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| 347 | }
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| 348 | }
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| 349 |
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| 350 | #endif /* ACCESS_TYPE != 3 */
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| 351 |
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| 352 | #endif /* !asm */
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| 353 |
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| 354 | #if ACCESS_TYPE != 3
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| 355 |
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| 356 | #if DATA_SIZE == 8
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| 357 | static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
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| 358 | {
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| 359 | union {
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| 360 | float64 d;
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| 361 | uint64_t i;
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| 362 | } u;
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| 363 | u.i = glue(ldq, MEMSUFFIX)(ptr);
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| 364 | return u.d;
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| 365 | }
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| 366 |
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| 367 | static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
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| 368 | {
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| 369 | union {
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| 370 | float64 d;
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| 371 | uint64_t i;
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| 372 | } u;
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| 373 | u.d = v;
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| 374 | glue(stq, MEMSUFFIX)(ptr, u.i);
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| 375 | }
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| 376 | #endif /* DATA_SIZE == 8 */
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| 377 |
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| 378 | #if DATA_SIZE == 4
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| 379 | static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
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| 380 | {
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| 381 | union {
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| 382 | float32 f;
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| 383 | uint32_t i;
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| 384 | } u;
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| 385 | u.i = glue(ldl, MEMSUFFIX)(ptr);
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| 386 | return u.f;
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| 387 | }
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| 388 |
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| 389 | static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
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| 390 | {
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| 391 | union {
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| 392 | float32 f;
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| 393 | uint32_t i;
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| 394 | } u;
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| 395 | u.f = v;
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| 396 | glue(stl, MEMSUFFIX)(ptr, u.i);
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| 397 | }
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| 398 | #endif /* DATA_SIZE == 4 */
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| 399 |
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| 400 | #endif /* ACCESS_TYPE != 3 */
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| 401 |
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| 402 | #undef RES_TYPE
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| 403 | #undef DATA_TYPE
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| 404 | #undef DATA_STYPE
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| 405 | #undef SUFFIX
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| 406 | #undef USUFFIX
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| 407 | #undef DATA_SIZE
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| 408 | #undef CPU_MEM_INDEX
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| 409 | #undef MMUSUFFIX
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| 410 | #undef ADDR_READ
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