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1/*
2 * i386 execution defines
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20
21/*
22 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29
30#include "config.h"
31#include "dyngen-exec.h"
32
33/* XXX: factorize this mess */
34#ifdef TARGET_X86_64
35#define TARGET_LONG_BITS 64
36#else
37#define TARGET_LONG_BITS 32
38#endif
39
40#include "cpu-defs.h"
41
42register struct CPUX86State *env asm(AREG0);
43
44#include "qemu-common.h"
45#include "qemu-log.h"
46
47#define EAX (env->regs[R_EAX])
48#define ECX (env->regs[R_ECX])
49#define EDX (env->regs[R_EDX])
50#define EBX (env->regs[R_EBX])
51#define ESP (env->regs[R_ESP])
52#define EBP (env->regs[R_EBP])
53#define ESI (env->regs[R_ESI])
54#define EDI (env->regs[R_EDI])
55#define EIP (env->eip)
56#define DF (env->df)
57
58#define CC_SRC (env->cc_src)
59#define CC_DST (env->cc_dst)
60#define CC_OP (env->cc_op)
61
62/* float macros */
63#define FT0 (env->ft0)
64#define ST0 (env->fpregs[env->fpstt].d)
65#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
66#define ST1 ST(1)
67
68#include "cpu.h"
69#include "exec-all.h"
70
71/* op_helper.c */
72void do_interrupt(int intno, int is_int, int error_code,
73 target_ulong next_eip, int is_hw);
74void do_interrupt_user(int intno, int is_int, int error_code,
75 target_ulong next_eip);
76void QEMU_NORETURN raise_exception_err(int exception_index, int error_code);
77void QEMU_NORETURN raise_exception(int exception_index);
78void do_smm_enter(void);
79
80/* n must be a constant to be efficient */
81static inline target_long lshift(target_long x, int n)
82{
83 if (n >= 0)
84 return x << n;
85 else
86 return x >> (-n);
87}
88
89#include "helper.h"
90
91static inline void svm_check_intercept(uint32_t type)
92{
93 helper_svm_check_intercept_param(type, 0);
94}
95
96#if !defined(CONFIG_USER_ONLY)
97
98#include "softmmu_exec.h"
99
100#endif /* !defined(CONFIG_USER_ONLY) */
101
102#ifdef USE_X86LDOUBLE
103/* use long double functions */
104#define floatx_to_int32 floatx80_to_int32
105#define floatx_to_int64 floatx80_to_int64
106#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
107#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
108#define int32_to_floatx int32_to_floatx80
109#define int64_to_floatx int64_to_floatx80
110#define float32_to_floatx float32_to_floatx80
111#define float64_to_floatx float64_to_floatx80
112#define floatx_to_float32 floatx80_to_float32
113#define floatx_to_float64 floatx80_to_float64
114#define floatx_abs floatx80_abs
115#define floatx_chs floatx80_chs
116#define floatx_round_to_int floatx80_round_to_int
117#define floatx_compare floatx80_compare
118#define floatx_compare_quiet floatx80_compare_quiet
119#ifdef VBOX
120#undef sin
121#undef cos
122#undef sqrt
123#undef pow
124#undef log
125#undef tan
126#undef atan2
127#undef floor
128#undef ceil
129#undef ldexp
130#endif /* !VBOX */
131#if !defined(VBOX) || !defined(_MSC_VER)
132#define sin sinl
133#define cos cosl
134#define sqrt sqrtl
135#define pow powl
136#define log logl
137#define tan tanl
138#define atan2 atan2l
139#define floor floorl
140#define ceil ceill
141#define ldexp ldexpl
142#endif
143#else
144#define floatx_to_int32 float64_to_int32
145#define floatx_to_int64 float64_to_int64
146#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
147#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
148#define int32_to_floatx int32_to_float64
149#define int64_to_floatx int64_to_float64
150#define float32_to_floatx float32_to_float64
151#define float64_to_floatx(x, e) (x)
152#define floatx_to_float32 float64_to_float32
153#define floatx_to_float64(x, e) (x)
154#define floatx_abs float64_abs
155#define floatx_chs float64_chs
156#define floatx_round_to_int float64_round_to_int
157#define floatx_compare float64_compare
158#define floatx_compare_quiet float64_compare_quiet
159#endif
160
161#ifdef VBOX
162extern CPU86_LDouble sin(CPU86_LDouble x);
163extern CPU86_LDouble cos(CPU86_LDouble x);
164extern CPU86_LDouble sqrt(CPU86_LDouble x);
165extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
166extern CPU86_LDouble log(CPU86_LDouble x);
167extern CPU86_LDouble tan(CPU86_LDouble x);
168extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
169extern CPU86_LDouble floor(CPU86_LDouble x);
170extern CPU86_LDouble ceil(CPU86_LDouble x);
171#endif /* VBOX */
172
173#define RC_MASK 0xc00
174#define RC_NEAR 0x000
175#define RC_DOWN 0x400
176#define RC_UP 0x800
177#define RC_CHOP 0xc00
178
179#define MAXTAN 9223372036854775808.0
180
181#ifdef USE_X86LDOUBLE
182
183/* only for x86 */
184typedef union {
185 long double d;
186 struct {
187 unsigned long long lower;
188 unsigned short upper;
189 } l;
190} CPU86_LDoubleU;
191
192/* the following deal with x86 long double-precision numbers */
193#define MAXEXPD 0x7fff
194#define EXPBIAS 16383
195#define EXPD(fp) (fp.l.upper & 0x7fff)
196#define SIGND(fp) ((fp.l.upper) & 0x8000)
197#define MANTD(fp) (fp.l.lower)
198#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
199
200#else
201
202/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
203typedef union {
204 double d;
205#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
206 struct {
207 uint32_t lower;
208 int32_t upper;
209 } l;
210#else
211 struct {
212 int32_t upper;
213 uint32_t lower;
214 } l;
215#endif
216#ifndef __arm__
217 int64_t ll;
218#endif
219} CPU86_LDoubleU;
220
221/* the following deal with IEEE double-precision numbers */
222#define MAXEXPD 0x7ff
223#define EXPBIAS 1023
224#define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
225#define SIGND(fp) ((fp.l.upper) & 0x80000000)
226#ifdef __arm__
227#define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
228#else
229#define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
230#endif
231#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
232#endif
233
234static inline void fpush(void)
235{
236 env->fpstt = (env->fpstt - 1) & 7;
237 env->fptags[env->fpstt] = 0; /* validate stack entry */
238}
239
240static inline void fpop(void)
241{
242 env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
243 env->fpstt = (env->fpstt + 1) & 7;
244}
245
246#ifndef USE_X86LDOUBLE
247static inline CPU86_LDouble helper_fldt(target_ulong ptr)
248{
249 CPU86_LDoubleU temp;
250 int upper, e;
251 uint64_t ll;
252
253 /* mantissa */
254 upper = lduw(ptr + 8);
255 /* XXX: handle overflow ? */
256 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
257 e |= (upper >> 4) & 0x800; /* sign */
258 ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
259#ifdef __arm__
260 temp.l.upper = (e << 20) | (ll >> 32);
261 temp.l.lower = ll;
262#else
263 temp.ll = ll | ((uint64_t)e << 52);
264#endif
265 return temp.d;
266}
267
268static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
269{
270 CPU86_LDoubleU temp;
271 int e;
272
273 temp.d = f;
274 /* mantissa */
275 stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
276 /* exponent + sign */
277 e = EXPD(temp) - EXPBIAS + 16383;
278 e |= SIGND(temp) >> 16;
279 stw(ptr + 8, e);
280}
281#else
282
283/* we use memory access macros */
284
285static inline CPU86_LDouble helper_fldt(target_ulong ptr)
286{
287 CPU86_LDoubleU temp;
288
289 temp.l.lower = ldq(ptr);
290 temp.l.upper = lduw(ptr + 8);
291 return temp.d;
292}
293
294static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
295{
296 CPU86_LDoubleU temp;
297
298 temp.d = f;
299 stq(ptr, temp.l.lower);
300 stw(ptr + 8, temp.l.upper);
301}
302
303#endif /* USE_X86LDOUBLE */
304
305#define FPUS_IE (1 << 0)
306#define FPUS_DE (1 << 1)
307#define FPUS_ZE (1 << 2)
308#define FPUS_OE (1 << 3)
309#define FPUS_UE (1 << 4)
310#define FPUS_PE (1 << 5)
311#define FPUS_SF (1 << 6)
312#define FPUS_SE (1 << 7)
313#define FPUS_B (1 << 15)
314
315#define FPUC_EM 0x3f
316
317static inline uint32_t compute_eflags(void)
318{
319 return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
320}
321
322/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
323static inline void load_eflags(int eflags, int update_mask)
324{
325 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
326 DF = 1 - (2 * ((eflags >> 10) & 1));
327 env->eflags = (env->eflags & ~update_mask) |
328 (eflags & update_mask) | 0x2;
329}
330
331static inline void env_to_regs(void)
332{
333#ifdef reg_EAX
334 EAX = env->regs[R_EAX];
335#endif
336#ifdef reg_ECX
337 ECX = env->regs[R_ECX];
338#endif
339#ifdef reg_EDX
340 EDX = env->regs[R_EDX];
341#endif
342#ifdef reg_EBX
343 EBX = env->regs[R_EBX];
344#endif
345#ifdef reg_ESP
346 ESP = env->regs[R_ESP];
347#endif
348#ifdef reg_EBP
349 EBP = env->regs[R_EBP];
350#endif
351#ifdef reg_ESI
352 ESI = env->regs[R_ESI];
353#endif
354#ifdef reg_EDI
355 EDI = env->regs[R_EDI];
356#endif
357}
358
359static inline void regs_to_env(void)
360{
361#ifdef reg_EAX
362 env->regs[R_EAX] = EAX;
363#endif
364#ifdef reg_ECX
365 env->regs[R_ECX] = ECX;
366#endif
367#ifdef reg_EDX
368 env->regs[R_EDX] = EDX;
369#endif
370#ifdef reg_EBX
371 env->regs[R_EBX] = EBX;
372#endif
373#ifdef reg_ESP
374 env->regs[R_ESP] = ESP;
375#endif
376#ifdef reg_EBP
377 env->regs[R_EBP] = EBP;
378#endif
379#ifdef reg_ESI
380 env->regs[R_ESI] = ESI;
381#endif
382#ifdef reg_EDI
383 env->regs[R_EDI] = EDI;
384#endif
385}
386
387static inline int cpu_halted(CPUState *env) {
388 /* handle exit of HALTED state */
389 if (!env->halted)
390 return 0;
391 /* disable halt condition */
392 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
393 (env->eflags & IF_MASK)) ||
394 (env->interrupt_request & CPU_INTERRUPT_NMI)) {
395 env->halted = 0;
396 return 0;
397 }
398 return EXCP_HALTED;
399}
400
401/* load efer and update the corresponding hflags. XXX: do consistency
402 checks with cpuid bits ? */
403static inline void cpu_load_efer(CPUState *env, uint64_t val)
404{
405 env->efer = val;
406 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
407 if (env->efer & MSR_EFER_LMA)
408 env->hflags |= HF_LMA_MASK;
409 if (env->efer & MSR_EFER_SVME)
410 env->hflags |= HF_SVME_MASK;
411}
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