| 1 | /*
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| 2 | * i386 execution defines
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| 3 | *
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| 4 | * Copyright (c) 2003 Fabrice Bellard
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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| 18 | */
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| 19 |
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| 20 | /*
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| 21 | * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 22 | * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
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| 23 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 24 | * a choice of LGPL license versions is made available with the language indicating
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| 25 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 26 | * of the LGPL is applied is otherwise unspecified.
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| 27 | */
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| 28 |
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| 29 | #include "config.h"
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| 30 | #include "dyngen-exec.h"
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| 31 |
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| 32 | /* XXX: factorize this mess */
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| 33 | #ifdef TARGET_X86_64
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| 34 | #define TARGET_LONG_BITS 64
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| 35 | #else
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| 36 | #define TARGET_LONG_BITS 32
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| 37 | #endif
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| 38 |
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| 39 | #include "cpu-defs.h"
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| 40 |
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| 41 | register struct CPUX86State *env asm(AREG0);
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| 42 |
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| 43 | #include "qemu-common.h"
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| 44 | #include "qemu-log.h"
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| 45 |
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| 46 | #undef EAX
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| 47 | #define EAX (env->regs[R_EAX])
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| 48 | #undef ECX
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| 49 | #define ECX (env->regs[R_ECX])
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| 50 | #undef EDX
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| 51 | #define EDX (env->regs[R_EDX])
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| 52 | #undef EBX
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| 53 | #define EBX (env->regs[R_EBX])
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| 54 | #undef ESP
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| 55 | #define ESP (env->regs[R_ESP])
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| 56 | #undef EBP
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| 57 | #define EBP (env->regs[R_EBP])
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| 58 | #undef ESI
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| 59 | #define ESI (env->regs[R_ESI])
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| 60 | #undef EDI
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| 61 | #define EDI (env->regs[R_EDI])
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| 62 | #undef EIP
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| 63 | #define EIP (env->eip)
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| 64 | #define DF (env->df)
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| 65 |
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| 66 | #define CC_SRC (env->cc_src)
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| 67 | #define CC_DST (env->cc_dst)
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| 68 | #define CC_OP (env->cc_op)
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| 69 |
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| 70 | /* float macros */
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| 71 | #define FT0 (env->ft0)
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| 72 | #define ST0 (env->fpregs[env->fpstt].d)
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| 73 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
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| 74 | #define ST1 ST(1)
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| 75 |
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| 76 | #include "cpu.h"
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| 77 | #include "exec-all.h"
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| 78 |
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| 79 | /* op_helper.c */
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| 80 | void do_interrupt(int intno, int is_int, int error_code,
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| 81 | target_ulong next_eip, int is_hw);
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| 82 | void do_interrupt_user(int intno, int is_int, int error_code,
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| 83 | target_ulong next_eip);
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| 84 | void QEMU_NORETURN raise_exception_err(int exception_index, int error_code);
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| 85 | void QEMU_NORETURN raise_exception(int exception_index);
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| 86 | void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *nenv);
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| 87 | void do_smm_enter(void);
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| 88 |
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| 89 | /* n must be a constant to be efficient */
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| 90 | static inline target_long lshift(target_long x, int n)
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| 91 | {
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| 92 | if (n >= 0)
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| 93 | return x << n;
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| 94 | else
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| 95 | return x >> (-n);
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| 96 | }
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| 97 |
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| 98 | #include "helper.h"
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| 99 |
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| 100 | static inline void svm_check_intercept(uint32_t type)
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| 101 | {
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| 102 | helper_svm_check_intercept_param(type, 0);
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| 103 | }
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| 104 |
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| 105 | #if !defined(CONFIG_USER_ONLY)
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| 106 |
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| 107 | #include "softmmu_exec.h"
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| 108 |
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| 109 | #endif /* !defined(CONFIG_USER_ONLY) */
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| 110 |
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| 111 | #ifdef USE_X86LDOUBLE
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| 112 | /* use long double functions */
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| 113 | #define floatx_to_int32 floatx80_to_int32
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| 114 | #define floatx_to_int64 floatx80_to_int64
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| 115 | #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
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| 116 | #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
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| 117 | #define int32_to_floatx int32_to_floatx80
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| 118 | #define int64_to_floatx int64_to_floatx80
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| 119 | #define float32_to_floatx float32_to_floatx80
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| 120 | #define float64_to_floatx float64_to_floatx80
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| 121 | #define floatx_to_float32 floatx80_to_float32
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| 122 | #define floatx_to_float64 floatx80_to_float64
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| 123 | #define floatx_abs floatx80_abs
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| 124 | #define floatx_chs floatx80_chs
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| 125 | #define floatx_round_to_int floatx80_round_to_int
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| 126 | #define floatx_compare floatx80_compare
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| 127 | #define floatx_compare_quiet floatx80_compare_quiet
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| 128 | #else
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| 129 | #define floatx_to_int32 float64_to_int32
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| 130 | #define floatx_to_int64 float64_to_int64
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| 131 | #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
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| 132 | #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
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| 133 | #define int32_to_floatx int32_to_float64
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| 134 | #define int64_to_floatx int64_to_float64
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| 135 | #define float32_to_floatx float32_to_float64
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| 136 | #define float64_to_floatx(x, e) (x)
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| 137 | #define floatx_to_float32 float64_to_float32
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| 138 | #define floatx_to_float64(x, e) (x)
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| 139 | #define floatx_abs float64_abs
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| 140 | #define floatx_chs float64_chs
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| 141 | #define floatx_round_to_int float64_round_to_int
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| 142 | #define floatx_compare float64_compare
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| 143 | #define floatx_compare_quiet float64_compare_quiet
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| 144 | #endif
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| 145 |
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| 146 | #ifdef VBOX
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| 147 | # ifdef IPRT_NO_CRT
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| 148 | # undef sin
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| 149 | # undef cos
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| 150 | # undef sqrt
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| 151 | # undef pow
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| 152 | # undef log
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| 153 | # undef tan
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| 154 | # undef atan2
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| 155 | # undef floor
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| 156 | # undef ceil
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| 157 | # undef ldexp
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| 158 | # define sin sinl
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| 159 | # define cos cosl
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| 160 | # define sqrt sqrtl
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| 161 | # define pow powl
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| 162 | # define log logl
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| 163 | # define tan tanl
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| 164 | # define atan2 atan2l
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| 165 | # define floor floorl
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| 166 | # define ceil ceill
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| 167 | # define ldexp ldexpl
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| 168 | # endif
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| 169 | #endif
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| 170 |
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| 171 | #define RC_MASK 0xc00
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| 172 | #define RC_NEAR 0x000
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| 173 | #define RC_DOWN 0x400
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| 174 | #define RC_UP 0x800
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| 175 | #define RC_CHOP 0xc00
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| 176 |
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| 177 | #define MAXTAN 9223372036854775808.0
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| 178 |
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| 179 | #ifdef USE_X86LDOUBLE
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| 180 |
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| 181 | /* only for x86 */
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| 182 | typedef union {
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| 183 | long double d;
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| 184 | struct {
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| 185 | unsigned long long lower;
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| 186 | unsigned short upper;
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| 187 | } l;
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| 188 | } CPU86_LDoubleU;
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| 189 |
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| 190 | /* the following deal with x86 long double-precision numbers */
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| 191 | #define MAXEXPD 0x7fff
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| 192 | #define EXPBIAS 16383
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| 193 | #define EXPD(fp) (fp.l.upper & 0x7fff)
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| 194 | #define SIGND(fp) ((fp.l.upper) & 0x8000)
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| 195 | #define MANTD(fp) (fp.l.lower)
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| 196 | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
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| 197 |
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| 198 | #else
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| 199 |
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| 200 | /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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| 201 | typedef union {
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| 202 | double d;
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| 203 | #if !defined(HOST_WORDS_BIGENDIAN) && !defined(__arm__)
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| 204 | struct {
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| 205 | uint32_t lower;
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| 206 | int32_t upper;
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| 207 | } l;
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| 208 | #else
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| 209 | struct {
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| 210 | int32_t upper;
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| 211 | uint32_t lower;
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| 212 | } l;
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| 213 | #endif
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| 214 | #ifndef __arm__
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| 215 | int64_t ll;
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| 216 | #endif
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| 217 | } CPU86_LDoubleU;
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| 218 |
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| 219 | /* the following deal with IEEE double-precision numbers */
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| 220 | #define MAXEXPD 0x7ff
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| 221 | #define EXPBIAS 1023
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| 222 | #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
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| 223 | #define SIGND(fp) ((fp.l.upper) & 0x80000000)
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| 224 | #ifdef __arm__
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| 225 | #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
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| 226 | #else
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| 227 | #define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
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| 228 | #endif
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| 229 | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
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| 230 | #endif
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| 231 |
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| 232 | static inline void fpush(void)
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| 233 | {
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| 234 | env->fpstt = (env->fpstt - 1) & 7;
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| 235 | env->fptags[env->fpstt] = 0; /* validate stack entry */
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| 236 | }
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| 237 |
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| 238 | static inline void fpop(void)
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| 239 | {
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| 240 | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
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| 241 | env->fpstt = (env->fpstt + 1) & 7;
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| 242 | }
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| 243 |
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| 244 | #ifndef USE_X86LDOUBLE
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| 245 | static inline CPU86_LDouble helper_fldt(target_ulong ptr)
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| 246 | {
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| 247 | CPU86_LDoubleU temp;
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| 248 | int upper, e;
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| 249 | uint64_t ll;
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| 250 |
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| 251 | /* mantissa */
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| 252 | upper = lduw(ptr + 8);
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| 253 | /* XXX: handle overflow ? */
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| 254 | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
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| 255 | e |= (upper >> 4) & 0x800; /* sign */
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| 256 | ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
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| 257 | #ifdef __arm__
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| 258 | temp.l.upper = (e << 20) | (ll >> 32);
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| 259 | temp.l.lower = ll;
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| 260 | #else
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| 261 | temp.ll = ll | ((uint64_t)e << 52);
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| 262 | #endif
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| 263 | return temp.d;
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| 264 | }
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| 265 |
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| 266 | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
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| 267 | {
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| 268 | CPU86_LDoubleU temp;
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| 269 | int e;
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| 270 |
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| 271 | temp.d = f;
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| 272 | /* mantissa */
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| 273 | stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
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| 274 | /* exponent + sign */
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| 275 | e = EXPD(temp) - EXPBIAS + 16383;
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| 276 | e |= SIGND(temp) >> 16;
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| 277 | stw(ptr + 8, e);
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| 278 | }
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| 279 | #else
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| 280 |
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| 281 | /* we use memory access macros */
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| 282 |
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| 283 | static inline CPU86_LDouble helper_fldt(target_ulong ptr)
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| 284 | {
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| 285 | CPU86_LDoubleU temp;
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| 286 |
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| 287 | temp.l.lower = ldq(ptr);
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| 288 | temp.l.upper = lduw(ptr + 8);
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| 289 | return temp.d;
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| 290 | }
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| 291 |
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| 292 | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
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| 293 | {
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| 294 | CPU86_LDoubleU temp;
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| 295 |
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| 296 | temp.d = f;
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| 297 | stq(ptr, temp.l.lower);
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| 298 | stw(ptr + 8, temp.l.upper);
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| 299 | }
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| 300 |
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| 301 | #endif /* USE_X86LDOUBLE */
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| 302 |
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| 303 | #define FPUS_IE (1 << 0)
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| 304 | #define FPUS_DE (1 << 1)
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| 305 | #define FPUS_ZE (1 << 2)
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| 306 | #define FPUS_OE (1 << 3)
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| 307 | #define FPUS_UE (1 << 4)
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| 308 | #define FPUS_PE (1 << 5)
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| 309 | #define FPUS_SF (1 << 6)
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| 310 | #define FPUS_SE (1 << 7)
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| 311 | #define FPUS_B (1 << 15)
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| 312 |
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| 313 | #define FPUC_EM 0x3f
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| 314 |
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| 315 | static inline uint32_t compute_eflags(void)
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| 316 | {
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| 317 | return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
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| 318 | }
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| 319 |
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| 320 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
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| 321 | static inline void load_eflags(int eflags, int update_mask)
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| 322 | {
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| 323 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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| 324 | DF = 1 - (2 * ((eflags >> 10) & 1));
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| 325 | env->eflags = (env->eflags & ~update_mask) |
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| 326 | (eflags & update_mask) | 0x2;
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| 327 | }
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| 328 |
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| 329 | static inline int cpu_has_work(CPUState *env)
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| 330 | {
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| 331 | int work;
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| 332 |
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| 333 | work = (env->interrupt_request & CPU_INTERRUPT_HARD) &&
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| 334 | (env->eflags & IF_MASK);
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| 335 | work |= env->interrupt_request & CPU_INTERRUPT_NMI;
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| 336 | work |= env->interrupt_request & CPU_INTERRUPT_INIT;
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| 337 | work |= env->interrupt_request & CPU_INTERRUPT_SIPI;
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| 338 |
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| 339 | return work;
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| 340 | }
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| 341 |
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| 342 | static inline int cpu_halted(CPUState *env) {
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| 343 | /* handle exit of HALTED state */
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| 344 | if (!env->halted)
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| 345 | return 0;
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| 346 | /* disable halt condition */
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| 347 | if (cpu_has_work(env)) {
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| 348 | env->halted = 0;
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| 349 | return 0;
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| 350 | }
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| 351 | return EXCP_HALTED;
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| 352 | }
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| 353 |
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| 354 | /* load efer and update the corresponding hflags. XXX: do consistency
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| 355 | checks with cpuid bits ? */
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| 356 | static inline void cpu_load_efer(CPUState *env, uint64_t val)
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| 357 | {
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| 358 | env->efer = val;
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| 359 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
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| 360 | if (env->efer & MSR_EFER_LMA)
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| 361 | env->hflags |= HF_LMA_MASK;
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| 362 | if (env->efer & MSR_EFER_SVME)
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| 363 | env->hflags |= HF_SVME_MASK;
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| 364 | }
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| 365 |
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| 366 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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| 367 | {
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| 368 | env->eip = tb->pc - tb->cs_base;
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| 369 | }
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| 370 |
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