helper.c@ 12440

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Minor 64 bits guest execution issues.
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1	/*
2	* i386 helpers
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20
21	/*
22	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
24	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25	* a choice of LGPL license versions is made available with the language indicating
26	* that LGPLv2 or any later version may be used, or where a choice of which version
27	* of the LGPL is applied is otherwise unspecified.
28	*/
29	#ifdef VBOX
30	# include <VBox/err.h>
31	#endif
32	#include "exec.h"
33
34	//#define DEBUG_PCALL
35
36	#if 0
37	#define raise_exception_err(a, b)\
38	do {\
39	if (logfile)\
40	fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
41	(raise_exception_err)(a, b);\
42	} while (0)
43	#endif
44
45	const uint8_t parity_table[256] = {
46	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
49	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
50	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
53	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
54	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
55	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
56	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
58	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
59	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
61	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
62	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
65	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
66	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
67	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
68	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
69	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
70	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
71	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
72	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
73	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
74	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
75	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
76	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
77	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
78	};
79
80	/* modulo 17 table */
81	const uint8_t rclw_table[32] = {
82	0, 1, 2, 3, 4, 5, 6, 7,
83	8, 9,10,11,12,13,14,15,
84	16, 0, 1, 2, 3, 4, 5, 6,
85	7, 8, 9,10,11,12,13,14,
86	};
87
88	/* modulo 9 table */
89	const uint8_t rclb_table[32] = {
90	0, 1, 2, 3, 4, 5, 6, 7,
91	8, 0, 1, 2, 3, 4, 5, 6,
92	7, 8, 0, 1, 2, 3, 4, 5,
93	6, 7, 8, 0, 1, 2, 3, 4,
94	};
95
96	const CPU86_LDouble f15rk[7] =
97	{
98	0.00000000000000000000L,
99	1.00000000000000000000L,
100	3.14159265358979323851L, /pi/
101	0.30102999566398119523L, /lg2/
102	0.69314718055994530943L, /ln2/
103	1.44269504088896340739L, /l2e/
104	3.32192809488736234781L, /l2t/
105	};
106
107	/* thread support */
108
109	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
110
111	void cpu_lock(void)
112	{
113	spin_lock(&global_cpu_lock);
114	}
115
116	void cpu_unlock(void)
117	{
118	spin_unlock(&global_cpu_lock);
119	}
120
121	void cpu_loop_exit(void)
122	{
123	/* NOTE: the register at this point must be saved by hand because
124	longjmp restore them */
125	regs_to_env();
126	longjmp(env->jmp_env, 1);
127	}
128
129	/* return non zero if error */
130	static inline int load_segment(uint32_t e1_ptr, uint32_t e2_ptr,
131	int selector)
132	{
133	SegmentCache *dt;
134	int index;
135	target_ulong ptr;
136
137	if (selector & 0x4)
138	dt = &env->ldt;
139	else
140	dt = &env->gdt;
141	index = selector & ~7;
142	if ((index + 7) > dt->limit)
143	return -1;
144	ptr = dt->base + index;
145	*e1_ptr = ldl_kernel(ptr);
146	*e2_ptr = ldl_kernel(ptr + 4);
147	return 0;
148	}
149
150	static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
151	{
152	unsigned int limit;
153	limit = (e1 & 0xffff) \| (e2 & 0x000f0000);
154	if (e2 & DESC_G_MASK)
155	limit = (limit << 12) \| 0xfff;
156	return limit;
157	}
158
159	static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
160	{
161	return ((e1 >> 16) \| ((e2 & 0xff) << 16) \| (e2 & 0xff000000));
162	}
163
164	static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
165	{
166	sc->base = get_seg_base(e1, e2);
167	sc->limit = get_seg_limit(e1, e2);
168	sc->flags = e2;
169	}
170
171	/* init the segment cache in vm86 mode. */
172	static inline void load_seg_vm(int seg, int selector)
173	{
174	selector &= 0xffff;
175	cpu_x86_load_seg_cache(env, seg, selector,
176	(selector << 4), 0xffff, 0);
177	}
178
179	static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
180	uint32_t *esp_ptr, int dpl)
181	{
182	int type, index, shift;
183
184	#if 0
185	{
186	int i;
187	printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
188	for(i=0;i<env->tr.limit;i++) {
189	printf("%02x ", env->tr.base[i]);
190	if ((i & 7) == 7) printf("\n");
191	}
192	printf("\n");
193	}
194	#endif
195
196	if (!(env->tr.flags & DESC_P_MASK))
197	cpu_abort(env, "invalid tss");
198	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
199	if ((type & 7) != 1)
200	cpu_abort(env, "invalid tss type %d", type);
201	shift = type >> 3;
202	index = (dpl * 4 + 2) << shift;
203	if (index + (4 << shift) - 1 > env->tr.limit)
204	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
205	if (shift == 0) {
206	*esp_ptr = lduw_kernel(env->tr.base + index);
207	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
208	} else {
209	*esp_ptr = ldl_kernel(env->tr.base + index);
210	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
211	}
212	}
213
214	/* XXX: merge with load_seg() */
215	static void tss_load_seg(int seg_reg, int selector)
216	{
217	uint32_t e1, e2;
218	int rpl, dpl, cpl;
219
220	if ((selector & 0xfffc) != 0) {
221	if (load_segment(&e1, &e2, selector) != 0)
222	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
223	if (!(e2 & DESC_S_MASK))
224	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
225	rpl = selector & 3;
226	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
227	cpl = env->hflags & HF_CPL_MASK;
228	if (seg_reg == R_CS) {
229	if (!(e2 & DESC_CS_MASK))
230	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231	/* XXX: is it correct ? */
232	if (dpl != rpl)
233	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
234	if ((e2 & DESC_C_MASK) && dpl > rpl)
235	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
236	} else if (seg_reg == R_SS) {
237	/* SS must be writable data */
238	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
239	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
240	if (dpl != cpl \|\| dpl != rpl)
241	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
242	} else {
243	/* not readable code */
244	if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
245	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
246	/* if data or non conforming code, checks the rights */
247	if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
248	if (dpl < cpl \|\| dpl < rpl)
249	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
250	}
251	}
252	if (!(e2 & DESC_P_MASK))
253	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
254	cpu_x86_load_seg_cache(env, seg_reg, selector,
255	get_seg_base(e1, e2),
256	get_seg_limit(e1, e2),
257	e2);
258	} else {
259	if (seg_reg == R_SS \|\| seg_reg == R_CS)
260	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
261	}
262	}
263
264	#define SWITCH_TSS_JMP 0
265	#define SWITCH_TSS_IRET 1
266	#define SWITCH_TSS_CALL 2
267
268	/* XXX: restore CPU state in registers (PowerPC case) */
269	static void switch_tss(int tss_selector,
270	uint32_t e1, uint32_t e2, int source,
271	uint32_t next_eip)
272	{
273	int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
274	target_ulong tss_base;
275	uint32_t new_regs[8], new_segs[6];
276	uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
277	uint32_t old_eflags, eflags_mask;
278	SegmentCache *dt;
279	int index;
280	target_ulong ptr;
281
282	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
283	#ifdef DEBUG_PCALL
284	if (loglevel & CPU_LOG_PCALL)
285	fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
286	#endif
287
288	#if defined(VBOX) && defined(DEBUG)
289	printf("switch_tss %x %x %x %d %08x\n", tss_selector, e1, e2, source, next_eip);
290	#endif
291
292	/* if task gate, we read the TSS segment and we load it */
293	if (type == 5) {
294	if (!(e2 & DESC_P_MASK))
295	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
296	tss_selector = e1 >> 16;
297	if (tss_selector & 4)
298	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
299	if (load_segment(&e1, &e2, tss_selector) != 0)
300	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
301	if (e2 & DESC_S_MASK)
302	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
303	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
304	if ((type & 7) != 1)
305	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
306	}
307
308	if (!(e2 & DESC_P_MASK))
309	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
310
311	if (type & 8)
312	tss_limit_max = 103;
313	else
314	tss_limit_max = 43;
315	tss_limit = get_seg_limit(e1, e2);
316	tss_base = get_seg_base(e1, e2);
317	if ((tss_selector & 4) != 0 \|\|
318	tss_limit < tss_limit_max)
319	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
320	old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
321	if (old_type & 8)
322	old_tss_limit_max = 103;
323	else
324	old_tss_limit_max = 43;
325
326	/* read all the registers from the new TSS */
327	if (type & 8) {
328	/* 32 bit */
329	new_cr3 = ldl_kernel(tss_base + 0x1c);
330	new_eip = ldl_kernel(tss_base + 0x20);
331	new_eflags = ldl_kernel(tss_base + 0x24);
332	for(i = 0; i < 8; i++)
333	new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
334	for(i = 0; i < 6; i++)
335	new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
336	new_ldt = lduw_kernel(tss_base + 0x60);
337	new_trap = ldl_kernel(tss_base + 0x64);
338	} else {
339	/* 16 bit */
340	new_cr3 = 0;
341	new_eip = lduw_kernel(tss_base + 0x0e);
342	new_eflags = lduw_kernel(tss_base + 0x10);
343	for(i = 0; i < 8; i++)
344	new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) \| 0xffff0000;
345	for(i = 0; i < 4; i++)
346	new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
347	new_ldt = lduw_kernel(tss_base + 0x2a);
348	new_segs[R_FS] = 0;
349	new_segs[R_GS] = 0;
350	new_trap = 0;
351	}
352
353	/* NOTE: we must avoid memory exceptions during the task switch,
354	so we make dummy accesses before */
355	/* XXX: it can still fail in some cases, so a bigger hack is
356	necessary to valid the TLB after having done the accesses */
357
358	v1 = ldub_kernel(env->tr.base);
359	v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
360	stb_kernel(env->tr.base, v1);
361	stb_kernel(env->tr.base + old_tss_limit_max, v2);
362
363	/* clear busy bit (it is restartable) */
364	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_IRET) {
365	target_ulong ptr;
366	uint32_t e2;
367	ptr = env->gdt.base + (env->tr.selector & ~7);
368	e2 = ldl_kernel(ptr + 4);
369	e2 &= ~DESC_TSS_BUSY_MASK;
370	stl_kernel(ptr + 4, e2);
371	}
372	old_eflags = compute_eflags();
373	if (source == SWITCH_TSS_IRET)
374	old_eflags &= ~NT_MASK;
375
376	/* save the current state in the old TSS */
377	if (type & 8) {
378	/* 32 bit */
379	stl_kernel(env->tr.base + 0x20, next_eip);
380	stl_kernel(env->tr.base + 0x24, old_eflags);
381	stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
382	stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
383	stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
384	stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
385	stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
386	stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
387	stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
388	stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
389	for(i = 0; i < 6; i++)
390	stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
391	#if defined(VBOX) && defined(DEBUG)
392	printf("TSS 32 bits switch\n");
393	printf("Saving CS=%08X\n", env->segs[R_CS].selector);
394	#endif
395	} else {
396	/* 16 bit */
397	stw_kernel(env->tr.base + 0x0e, next_eip);
398	stw_kernel(env->tr.base + 0x10, old_eflags);
399	stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
400	stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
401	stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
402	stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
403	stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
404	stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
405	stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
406	stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
407	for(i = 0; i < 4; i++)
408	stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
409	}
410
411	/* now if an exception occurs, it will occurs in the next task
412	context */
413
414	if (source == SWITCH_TSS_CALL) {
415	stw_kernel(tss_base, env->tr.selector);
416	new_eflags \|= NT_MASK;
417	}
418
419	/* set busy bit */
420	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_CALL) {
421	target_ulong ptr;
422	uint32_t e2;
423	ptr = env->gdt.base + (tss_selector & ~7);
424	e2 = ldl_kernel(ptr + 4);
425	e2 \|= DESC_TSS_BUSY_MASK;
426	stl_kernel(ptr + 4, e2);
427	}
428
429	/* set the new CPU state */
430	/* from this point, any exception which occurs can give problems */
431	env->cr[0] \|= CR0_TS_MASK;
432	env->hflags \|= HF_TS_MASK;
433	env->tr.selector = tss_selector;
434	env->tr.base = tss_base;
435	env->tr.limit = tss_limit;
436	env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
437
438	if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
439	cpu_x86_update_cr3(env, new_cr3);
440	}
441
442	/* load all registers without an exception, then reload them with
443	possible exception */
444	env->eip = new_eip;
445	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \|
446	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK;
447	if (!(type & 8))
448	eflags_mask &= 0xffff;
449	load_eflags(new_eflags, eflags_mask);
450	/* XXX: what to do in 16 bit case ? */
451	EAX = new_regs[0];
452	ECX = new_regs[1];
453	EDX = new_regs[2];
454	EBX = new_regs[3];
455	ESP = new_regs[4];
456	EBP = new_regs[5];
457	ESI = new_regs[6];
458	EDI = new_regs[7];
459	if (new_eflags & VM_MASK) {
460	for(i = 0; i < 6; i++)
461	load_seg_vm(i, new_segs[i]);
462	/* in vm86, CPL is always 3 */
463	cpu_x86_set_cpl(env, 3);
464	} else {
465	/* CPL is set the RPL of CS */
466	cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
467	/* first just selectors as the rest may trigger exceptions */
468	for(i = 0; i < 6; i++)
469	cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
470	}
471
472	env->ldt.selector = new_ldt & ~4;
473	env->ldt.base = 0;
474	env->ldt.limit = 0;
475	env->ldt.flags = 0;
476
477	/* load the LDT */
478	if (new_ldt & 4)
479	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
480
481	if ((new_ldt & 0xfffc) != 0) {
482	dt = &env->gdt;
483	index = new_ldt & ~7;
484	if ((index + 7) > dt->limit)
485	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
486	ptr = dt->base + index;
487	e1 = ldl_kernel(ptr);
488	e2 = ldl_kernel(ptr + 4);
489	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
490	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
491	if (!(e2 & DESC_P_MASK))
492	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
493	load_seg_cache_raw_dt(&env->ldt, e1, e2);
494	}
495
496	/* load the segments */
497	if (!(new_eflags & VM_MASK)) {
498	tss_load_seg(R_CS, new_segs[R_CS]);
499	tss_load_seg(R_SS, new_segs[R_SS]);
500	tss_load_seg(R_ES, new_segs[R_ES]);
501	tss_load_seg(R_DS, new_segs[R_DS]);
502	tss_load_seg(R_FS, new_segs[R_FS]);
503	tss_load_seg(R_GS, new_segs[R_GS]);
504	}
505
506	/* check that EIP is in the CS segment limits */
507	if (new_eip > env->segs[R_CS].limit) {
508	/* XXX: different exception if CALL ? */
509	raise_exception_err(EXCP0D_GPF, 0);
510	}
511	}
512
513	/* check if Port I/O is allowed in TSS */
514	static inline void check_io(int addr, int size)
515	{
516	int io_offset, val, mask;
517
518	/* TSS must be a valid 32 bit one */
519	if (!(env->tr.flags & DESC_P_MASK) \|\|
520	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
521	env->tr.limit < 103)
522	goto fail;
523	io_offset = lduw_kernel(env->tr.base + 0x66);
524	io_offset += (addr >> 3);
525	/* Note: the check needs two bytes */
526	if ((io_offset + 1) > env->tr.limit)
527	goto fail;
528	val = lduw_kernel(env->tr.base + io_offset);
529	val >>= (addr & 7);
530	mask = (1 << size) - 1;
531	/* all bits must be zero to allow the I/O */
532	if ((val & mask) != 0) {
533	fail:
534	raise_exception_err(EXCP0D_GPF, 0);
535	}
536	}
537
538	void check_iob_T0(void)
539	{
540	check_io(T0, 1);
541	}
542
543	void check_iow_T0(void)
544	{
545	check_io(T0, 2);
546	}
547
548	void check_iol_T0(void)
549	{
550	check_io(T0, 4);
551	}
552
553	void check_iob_DX(void)
554	{
555	check_io(EDX & 0xffff, 1);
556	}
557
558	void check_iow_DX(void)
559	{
560	check_io(EDX & 0xffff, 2);
561	}
562
563	void check_iol_DX(void)
564	{
565	check_io(EDX & 0xffff, 4);
566	}
567
568	static inline unsigned int get_sp_mask(unsigned int e2)
569	{
570	if (e2 & DESC_B_MASK)
571	return 0xffffffff;
572	else
573	return 0xffff;
574	}
575
576	#ifdef TARGET_X86_64
577	#define SET_ESP(val, sp_mask)\
578	do {\
579	if ((sp_mask) == 0xffff)\
580	ESP = (ESP & ~0xffff) \| ((val) & 0xffff);\
581	else if ((sp_mask) == 0xffffffffLL)\
582	ESP = (uint32_t)(val);\
583	else\
584	ESP = (val);\
585	} while (0)
586	#else
587	#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) \| ((val) & (sp_mask))
588	#endif
589
590	/* XXX: add a is_user flag to have proper security support */
591	#define PUSHW(ssp, sp, sp_mask, val)\
592	{\
593	sp -= 2;\
594	stw_kernel((ssp) + (sp & (sp_mask)), (val));\
595	}
596
597	#define PUSHL(ssp, sp, sp_mask, val)\
598	{\
599	sp -= 4;\
600	stl_kernel((ssp) + (sp & (sp_mask)), (val));\
601	}
602
603	#define POPW(ssp, sp, sp_mask, val)\
604	{\
605	val = lduw_kernel((ssp) + (sp & (sp_mask)));\
606	sp += 2;\
607	}
608
609	#define POPL(ssp, sp, sp_mask, val)\
610	{\
611	val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
612	sp += 4;\
613	}
614
615	/* protected mode interrupt */
616	static void do_interrupt_protected(int intno, int is_int, int error_code,
617	unsigned int next_eip, int is_hw)
618	{
619	SegmentCache *dt;
620	target_ulong ptr, ssp;
621	int type, dpl, selector, ss_dpl, cpl;
622	int has_error_code, new_stack, shift;
623	uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
624	uint32_t old_eip, sp_mask;
625
626	#ifdef VBOX
627	if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
628	cpu_loop_exit();
629	#endif
630
631	has_error_code = 0;
632	if (!is_int && !is_hw) {
633	switch(intno) {
634	case 8:
635	case 10:
636	case 11:
637	case 12:
638	case 13:
639	case 14:
640	case 17:
641	has_error_code = 1;
642	break;
643	}
644	}
645	if (is_int)
646	old_eip = next_eip;
647	else
648	old_eip = env->eip;
649
650	dt = &env->idt;
651	if (intno * 8 + 7 > dt->limit)
652	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
653	ptr = dt->base + intno * 8;
654	e1 = ldl_kernel(ptr);
655	e2 = ldl_kernel(ptr + 4);
656	/* check gate type */
657	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
658	switch(type) {
659	case 5: /* task gate */
660	/* must do that check here to return the correct error code */
661	if (!(e2 & DESC_P_MASK))
662	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
663	switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
664	if (has_error_code) {
665	int type;
666	uint32_t mask;
667	/* push the error code */
668	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
669	shift = type >> 3;
670	if (env->segs[R_SS].flags & DESC_B_MASK)
671	mask = 0xffffffff;
672	else
673	mask = 0xffff;
674	esp = (ESP - (2 << shift)) & mask;
675	ssp = env->segs[R_SS].base + esp;
676	if (shift)
677	stl_kernel(ssp, error_code);
678	else
679	stw_kernel(ssp, error_code);
680	SET_ESP(esp, mask);
681	}
682	return;
683	case 6: /* 286 interrupt gate */
684	case 7: /* 286 trap gate */
685	case 14: /* 386 interrupt gate */
686	case 15: /* 386 trap gate */
687	break;
688	default:
689	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
690	break;
691	}
692	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
693	cpl = env->hflags & HF_CPL_MASK;
694	/* check privledge if software int */
695	if (is_int && dpl < cpl)
696	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
697	/* check valid bit */
698	if (!(e2 & DESC_P_MASK))
699	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
700	selector = e1 >> 16;
701	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
702	if ((selector & 0xfffc) == 0)
703	raise_exception_err(EXCP0D_GPF, 0);
704
705	if (load_segment(&e1, &e2, selector) != 0)
706	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
707	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
708	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
709	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
710	if (dpl > cpl)
711	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
712	if (!(e2 & DESC_P_MASK))
713	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
714	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
715	/* to inner priviledge */
716	get_ss_esp_from_tss(&ss, &esp, dpl);
717	if ((ss & 0xfffc) == 0)
718	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
719	if ((ss & 3) != dpl)
720	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
721	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
722	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
723	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
724	if (ss_dpl != dpl)
725	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
726	if (!(ss_e2 & DESC_S_MASK) \|\|
727	(ss_e2 & DESC_CS_MASK) \|\|
728	!(ss_e2 & DESC_W_MASK))
729	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
730	if (!(ss_e2 & DESC_P_MASK))
731	#ifdef VBOX /* See page 3-477 of 253666.pdf */
732	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
733	#else
734	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
735	#endif
736	new_stack = 1;
737	sp_mask = get_sp_mask(ss_e2);
738	ssp = get_seg_base(ss_e1, ss_e2);
739	#if defined(VBOX) && defined(DEBUG)
740	printf("new stack %04X:%08X gate dpl=%d\n", ss, esp, dpl);
741	#endif
742	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
743	/* to same priviledge */
744	if (env->eflags & VM_MASK)
745	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
746	new_stack = 0;
747	sp_mask = get_sp_mask(env->segs[R_SS].flags);
748	ssp = env->segs[R_SS].base;
749	esp = ESP;
750	dpl = cpl;
751	} else {
752	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
753	new_stack = 0; /* avoid warning */
754	sp_mask = 0; /* avoid warning */
755	ssp = 0; /* avoid warning */
756	esp = 0; /* avoid warning */
757	}
758
759	shift = type >> 3;
760
761	#if 0
762	/* XXX: check that enough room is available */
763	push_size = 6 + (new_stack << 2) + (has_error_code << 1);
764	if (env->eflags & VM_MASK)
765	push_size += 8;
766	push_size <<= shift;
767	#endif
768	if (shift == 1) {
769	if (new_stack) {
770	if (env->eflags & VM_MASK) {
771	PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
772	PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
773	PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
774	PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
775	}
776	PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
777	PUSHL(ssp, esp, sp_mask, ESP);
778	}
779	PUSHL(ssp, esp, sp_mask, compute_eflags());
780	PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
781	PUSHL(ssp, esp, sp_mask, old_eip);
782	if (has_error_code) {
783	PUSHL(ssp, esp, sp_mask, error_code);
784	}
785	} else {
786	if (new_stack) {
787	if (env->eflags & VM_MASK) {
788	PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
789	PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
790	PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
791	PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
792	}
793	PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
794	PUSHW(ssp, esp, sp_mask, ESP);
795	}
796	PUSHW(ssp, esp, sp_mask, compute_eflags());
797	PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
798	PUSHW(ssp, esp, sp_mask, old_eip);
799	if (has_error_code) {
800	PUSHW(ssp, esp, sp_mask, error_code);
801	}
802	}
803
804	if (new_stack) {
805	if (env->eflags & VM_MASK) {
806	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
807	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
808	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
809	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
810	}
811	ss = (ss & ~3) \| dpl;
812	cpu_x86_load_seg_cache(env, R_SS, ss,
813	ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
814	}
815	SET_ESP(esp, sp_mask);
816
817	selector = (selector & ~3) \| dpl;
818	cpu_x86_load_seg_cache(env, R_CS, selector,
819	get_seg_base(e1, e2),
820	get_seg_limit(e1, e2),
821	e2);
822	cpu_x86_set_cpl(env, dpl);
823	env->eip = offset;
824
825	/* interrupt gate clear IF mask */
826	if ((type & 1) == 0) {
827	env->eflags &= ~IF_MASK;
828	}
829	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
830	}
831
832	#ifdef VBOX
833
834	/* check if VME interrupt redirection is enabled in TSS */
835	static inline bool is_vme_irq_redirected(int intno)
836	{
837	int io_offset, intredir_offset;
838	unsigned char val, mask;
839
840	/* TSS must be a valid 32 bit one */
841	if (!(env->tr.flags & DESC_P_MASK) \|\|
842	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
843	env->tr.limit < 103)
844	goto fail;
845	io_offset = lduw_kernel(env->tr.base + 0x66);
846	/* the virtual interrupt redirection bitmap is located below the io bitmap */
847	intredir_offset = io_offset - 0x20;
848
849	intredir_offset += (intno >> 3);
850	if ((intredir_offset) > env->tr.limit)
851	goto fail;
852
853	val = ldub_kernel(env->tr.base + intredir_offset);
854	mask = 1 << (unsigned char)(intno & 7);
855
856	/* bit set means no redirection. */
857	if ((val & mask) != 0) {
858	return false;
859	}
860	return true;
861
862	fail:
863	raise_exception_err(EXCP0D_GPF, 0);
864	return true;
865	}
866
867	/* V86 mode software interrupt with CR4.VME=1 */
868	static void do_soft_interrupt_vme(int intno, int error_code, unsigned int next_eip)
869	{
870	target_ulong ptr, ssp;
871	int selector;
872	uint32_t offset, esp;
873	uint32_t old_cs, old_eflags;
874	uint32_t iopl;
875
876	iopl = ((env->eflags >> IOPL_SHIFT) & 3);
877
878	if (!is_vme_irq_redirected(intno))
879	{
880	if (iopl == 3)
881	/* normal protected mode handler call */
882	return do_interrupt_protected(intno, 1, error_code, next_eip, 0);
883	else
884	raise_exception_err(EXCP0D_GPF, 0);
885	}
886
887	/* virtual mode idt is at linear address 0 */
888	ptr = 0 + intno * 4;
889	offset = lduw_kernel(ptr);
890	selector = lduw_kernel(ptr + 2);
891	esp = ESP;
892	ssp = env->segs[R_SS].base;
893	old_cs = env->segs[R_CS].selector;
894
895	old_eflags = compute_eflags();
896	if (iopl < 3)
897	{
898	/* copy VIF into IF and set IOPL to 3 */
899	if (env->eflags & VIF_MASK)
900	old_eflags \|= IF_MASK;
901	else
902	old_eflags &= ~IF_MASK;
903
904	old_eflags \|= (3 << IOPL_SHIFT);
905	}
906
907	/* XXX: use SS segment size ? */
908	PUSHW(ssp, esp, 0xffff, old_eflags);
909	PUSHW(ssp, esp, 0xffff, old_cs);
910	PUSHW(ssp, esp, 0xffff, next_eip);
911
912	/* update processor state */
913	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
914	env->eip = offset;
915	env->segs[R_CS].selector = selector;
916	env->segs[R_CS].base = (selector << 4);
917	env->eflags &= ~(TF_MASK \| RF_MASK);
918
919	if (iopl < 3)
920	env->eflags &= ~VIF_MASK;
921	else
922	env->eflags &= ~IF_MASK;
923	}
924	#endif /* VBOX */
925
926	#ifdef TARGET_X86_64
927
928	#define PUSHQ(sp, val)\
929	{\
930	sp -= 8;\
931	stq_kernel(sp, (val));\
932	}
933
934	#define POPQ(sp, val)\
935	{\
936	val = ldq_kernel(sp);\
937	sp += 8;\
938	}
939
940	static inline target_ulong get_rsp_from_tss(int level)
941	{
942	int index;
943
944	#if 0
945	printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
946	env->tr.base, env->tr.limit);
947	#endif
948
949	if (!(env->tr.flags & DESC_P_MASK))
950	cpu_abort(env, "invalid tss");
951	index = 8 * level + 4;
952	if ((index + 7) > env->tr.limit)
953	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
954	return ldq_kernel(env->tr.base + index);
955	}
956
957	/* 64 bit interrupt */
958	static void do_interrupt64(int intno, int is_int, int error_code,
959	target_ulong next_eip, int is_hw)
960	{
961	SegmentCache *dt;
962	target_ulong ptr;
963	int type, dpl, selector, cpl, ist;
964	int has_error_code, new_stack;
965	uint32_t e1, e2, e3, ss;
966	target_ulong old_eip, esp, offset;
967
968	#ifdef VBOX
969	if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
970	cpu_loop_exit();
971	#endif
972
973	has_error_code = 0;
974	if (!is_int && !is_hw) {
975	switch(intno) {
976	case 8:
977	case 10:
978	case 11:
979	case 12:
980	case 13:
981	case 14:
982	case 17:
983	has_error_code = 1;
984	break;
985	}
986	}
987	if (is_int)
988	old_eip = next_eip;
989	else
990	old_eip = env->eip;
991
992	dt = &env->idt;
993	if (intno * 16 + 15 > dt->limit)
994	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
995	ptr = dt->base + intno * 16;
996	e1 = ldl_kernel(ptr);
997	e2 = ldl_kernel(ptr + 4);
998	e3 = ldl_kernel(ptr + 8);
999	/* check gate type */
1000	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1001	switch(type) {
1002	case 14: /* 386 interrupt gate */
1003	case 15: /* 386 trap gate */
1004	break;
1005	default:
1006	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1007	break;
1008	}
1009	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1010	cpl = env->hflags & HF_CPL_MASK;
1011	/* check privledge if software int */
1012	if (is_int && dpl < cpl)
1013	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1014	/* check valid bit */
1015	if (!(e2 & DESC_P_MASK))
1016	raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
1017	selector = e1 >> 16;
1018	offset = ((target_ulong)e3 << 32) \| (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
1019	ist = e2 & 7;
1020	if ((selector & 0xfffc) == 0)
1021	raise_exception_err(EXCP0D_GPF, 0);
1022
1023	if (load_segment(&e1, &e2, selector) != 0)
1024	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1025	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
1026	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1027	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1028	if (dpl > cpl)
1029	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1030	if (!(e2 & DESC_P_MASK))
1031	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1032	if (!(e2 & DESC_L_MASK) \|\| (e2 & DESC_B_MASK))
1033	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1034	if ((!(e2 & DESC_C_MASK) && dpl < cpl) \|\| ist != 0) {
1035	/* to inner priviledge */
1036	if (ist != 0)
1037	esp = get_rsp_from_tss(ist + 3);
1038	else
1039	esp = get_rsp_from_tss(dpl);
1040	esp &= ~0xfLL; /* align stack */
1041	ss = 0;
1042	new_stack = 1;
1043	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
1044	/* to same priviledge */
1045	if (env->eflags & VM_MASK)
1046	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1047	new_stack = 0;
1048	if (ist != 0)
1049	esp = get_rsp_from_tss(ist + 3);
1050	else
1051	esp = ESP;
1052	esp &= ~0xfLL; /* align stack */
1053	dpl = cpl;
1054	} else {
1055	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1056	new_stack = 0; /* avoid warning */
1057	esp = 0; /* avoid warning */
1058	}
1059
1060	PUSHQ(esp, env->segs[R_SS].selector);
1061	PUSHQ(esp, ESP);
1062	PUSHQ(esp, compute_eflags());
1063	PUSHQ(esp, env->segs[R_CS].selector);
1064	PUSHQ(esp, old_eip);
1065	if (has_error_code) {
1066	PUSHQ(esp, error_code);
1067	}
1068
1069	if (new_stack) {
1070	ss = 0 \| dpl;
1071	cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
1072	}
1073	ESP = esp;
1074
1075	selector = (selector & ~3) \| dpl;
1076	cpu_x86_load_seg_cache(env, R_CS, selector,
1077	get_seg_base(e1, e2),
1078	get_seg_limit(e1, e2),
1079	e2);
1080	cpu_x86_set_cpl(env, dpl);
1081	env->eip = offset;
1082
1083	/* interrupt gate clear IF mask */
1084	if ((type & 1) == 0) {
1085	env->eflags &= ~IF_MASK;
1086	}
1087	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1088	}
1089	#endif
1090
1091	void helper_syscall(int next_eip_addend)
1092	{
1093	int selector;
1094
1095	if (!(env->efer & MSR_EFER_SCE)) {
1096	raise_exception_err(EXCP06_ILLOP, 0);
1097	}
1098	selector = (env->star >> 32) & 0xffff;
1099	#ifdef TARGET_X86_64
1100	if (env->hflags & HF_LMA_MASK) {
1101	int code64;
1102
1103	ECX = env->eip + next_eip_addend;
1104	env->regs[11] = compute_eflags();
1105
1106	code64 = env->hflags & HF_CS64_MASK;
1107
1108	cpu_x86_set_cpl(env, 0);
1109	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1110	0, 0xffffffff,
1111	DESC_G_MASK \| DESC_P_MASK \|
1112	DESC_S_MASK \|
1113	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \| DESC_L_MASK);
1114	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1115	0, 0xffffffff,
1116	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1117	DESC_S_MASK \|
1118	DESC_W_MASK \| DESC_A_MASK);
1119	env->eflags &= ~env->fmask;
1120	if (code64)
1121	env->eip = env->lstar;
1122	else
1123	env->eip = env->cstar;
1124	} else
1125	#endif
1126	{
1127	ECX = (uint32_t)(env->eip + next_eip_addend);
1128
1129	cpu_x86_set_cpl(env, 0);
1130	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1131	0, 0xffffffff,
1132	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1133	DESC_S_MASK \|
1134	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1135	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1136	0, 0xffffffff,
1137	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1138	DESC_S_MASK \|
1139	DESC_W_MASK \| DESC_A_MASK);
1140	env->eflags &= ~(IF_MASK \| RF_MASK \| VM_MASK);
1141	env->eip = (uint32_t)env->star;
1142	}
1143	}
1144
1145	void helper_sysret(int dflag)
1146	{
1147	int cpl, selector;
1148
1149	if (!(env->efer & MSR_EFER_SCE)) {
1150	raise_exception_err(EXCP06_ILLOP, 0);
1151	}
1152	cpl = env->hflags & HF_CPL_MASK;
1153	if (!(env->cr[0] & CR0_PE_MASK) \|\| cpl != 0) {
1154	raise_exception_err(EXCP0D_GPF, 0);
1155	}
1156	selector = (env->star >> 48) & 0xffff;
1157	#ifdef TARGET_X86_64
1158	if (env->hflags & HF_LMA_MASK) {
1159	if (dflag == 2) {
1160	cpu_x86_load_seg_cache(env, R_CS, (selector + 16) \| 3,
1161	0, 0xffffffff,
1162	DESC_G_MASK \| DESC_P_MASK \|
1163	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1164	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \|
1165	DESC_L_MASK);
1166	env->eip = ECX;
1167	} else {
1168	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1169	0, 0xffffffff,
1170	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1171	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1172	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1173	env->eip = (uint32_t)ECX;
1174	}
1175	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1176	0, 0xffffffff,
1177	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1178	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1179	DESC_W_MASK \| DESC_A_MASK);
1180	load_eflags((uint32_t)(env->regs[11]), TF_MASK \| AC_MASK \| ID_MASK \|
1181	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1182	cpu_x86_set_cpl(env, 3);
1183	} else
1184	#endif
1185	{
1186	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1187	0, 0xffffffff,
1188	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1189	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1190	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1191	env->eip = (uint32_t)ECX;
1192	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1193	0, 0xffffffff,
1194	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1195	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1196	DESC_W_MASK \| DESC_A_MASK);
1197	env->eflags \|= IF_MASK;
1198	cpu_x86_set_cpl(env, 3);
1199	}
1200	#ifdef USE_KQEMU
1201	if (kqemu_is_ok(env)) {
1202	if (env->hflags & HF_LMA_MASK)
1203	CC_OP = CC_OP_EFLAGS;
1204	env->exception_index = -1;
1205	cpu_loop_exit();
1206	}
1207	#endif
1208	}
1209
1210	#ifdef VBOX
1211	/**
1212	* Checks and processes external VMM events.
1213	* Called by op_check_external_event() when any of the flags is set and can be serviced.
1214	*/
1215	void helper_external_event(void)
1216	{
1217	#if defined(RT_OS_DARWIN) && defined(VBOX_STRICT)
1218	uintptr_t uESP;
1219	__asm__ __volatile__("movl %%esp, %0" : "=r" (uESP));
1220	AssertMsg(!(uESP & 15), ("esp=%#p\n", uESP));
1221	#endif
1222	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
1223	{
1224	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_HARD);
1225	cpu_interrupt(env, CPU_INTERRUPT_HARD);
1226	}
1227	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_EXIT)
1228	{
1229	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_EXIT);
1230	cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1231	}
1232	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_DMA)
1233	{
1234	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_DMA);
1235	remR3DmaRun(env);
1236	}
1237	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_TIMER)
1238	{
1239	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_TIMER);
1240	remR3TimersRun(env);
1241	}
1242	}
1243	/* helper for recording call instruction addresses for later scanning */
1244	void helper_record_call()
1245	{
1246	if ( !(env->state & CPU_RAW_RING0)
1247	&& (env->cr[0] & CR0_PG_MASK)
1248	&& !(env->eflags & X86_EFL_IF))
1249	remR3RecordCall(env);
1250	}
1251	#endif /* VBOX */
1252
1253	/* real mode interrupt */
1254	static void do_interrupt_real(int intno, int is_int, int error_code,
1255	unsigned int next_eip)
1256	{
1257	SegmentCache *dt;
1258	target_ulong ptr, ssp;
1259	int selector;
1260	uint32_t offset, esp;
1261	uint32_t old_cs, old_eip;
1262
1263	/* real mode (simpler !) */
1264	dt = &env->idt;
1265	if (intno * 4 + 3 > dt->limit)
1266	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1267	ptr = dt->base + intno * 4;
1268	offset = lduw_kernel(ptr);
1269	selector = lduw_kernel(ptr + 2);
1270	esp = ESP;
1271	ssp = env->segs[R_SS].base;
1272	if (is_int)
1273	old_eip = next_eip;
1274	else
1275	old_eip = env->eip;
1276	old_cs = env->segs[R_CS].selector;
1277	/* XXX: use SS segment size ? */
1278	PUSHW(ssp, esp, 0xffff, compute_eflags());
1279	PUSHW(ssp, esp, 0xffff, old_cs);
1280	PUSHW(ssp, esp, 0xffff, old_eip);
1281
1282	/* update processor state */
1283	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
1284	env->eip = offset;
1285	env->segs[R_CS].selector = selector;
1286	env->segs[R_CS].base = (selector << 4);
1287	env->eflags &= ~(IF_MASK \| TF_MASK \| AC_MASK \| RF_MASK);
1288	}
1289
1290	/* fake user mode interrupt */
1291	void do_interrupt_user(int intno, int is_int, int error_code,
1292	target_ulong next_eip)
1293	{
1294	SegmentCache *dt;
1295	target_ulong ptr;
1296	int dpl, cpl;
1297	uint32_t e2;
1298
1299	dt = &env->idt;
1300	ptr = dt->base + (intno * 8);
1301	e2 = ldl_kernel(ptr + 4);
1302
1303	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1304	cpl = env->hflags & HF_CPL_MASK;
1305	/* check privledge if software int */
1306	if (is_int && dpl < cpl)
1307	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1308
1309	/* Since we emulate only user space, we cannot do more than
1310	exiting the emulation with the suitable exception and error
1311	code */
1312	if (is_int)
1313	EIP = next_eip;
1314	}
1315
1316	/*
1317	* Begin execution of an interruption. is_int is TRUE if coming from
1318	* the int instruction. next_eip is the EIP value AFTER the interrupt
1319	* instruction. It is only relevant if is_int is TRUE.
1320	*/
1321	void do_interrupt(int intno, int is_int, int error_code,
1322	target_ulong next_eip, int is_hw)
1323	{
1324	if (loglevel & CPU_LOG_INT) {
1325	if ((env->cr[0] & CR0_PE_MASK)) {
1326	static int count;
1327	fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1328	count, intno, error_code, is_int,
1329	env->hflags & HF_CPL_MASK,
1330	env->segs[R_CS].selector, EIP,
1331	(int)env->segs[R_CS].base + EIP,
1332	env->segs[R_SS].selector, ESP);
1333	if (intno == 0x0e) {
1334	fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1335	} else {
1336	fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1337	}
1338	fprintf(logfile, "\n");
1339	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1340	#if 0
1341	{
1342	int i;
1343	uint8_t *ptr;
1344	fprintf(logfile, " code=");
1345	ptr = env->segs[R_CS].base + env->eip;
1346	for(i = 0; i < 16; i++) {
1347	fprintf(logfile, " %02x", ldub(ptr + i));
1348	}
1349	fprintf(logfile, "\n");
1350	}
1351	#endif
1352	count++;
1353	}
1354	}
1355	if (env->cr[0] & CR0_PE_MASK) {
1356	#ifdef TARGET_X86_64
1357	if (env->hflags & HF_LMA_MASK) {
1358	do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1359	} else
1360	#endif
1361	{
1362	#ifdef VBOX
1363	/* int xx , v86 code and VME enabled? /
1364	if ( (env->eflags & VM_MASK)
1365	&& (env->cr[4] & CR4_VME_MASK)
1366	&& is_int
1367	&& !is_hw
1368	&& env->eip + 1 != next_eip /* single byte int 3 goes straight to the protected mode handler */
1369	)
1370	do_soft_interrupt_vme(intno, error_code, next_eip);
1371	else
1372	#endif /* VBOX */
1373	do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1374	}
1375	} else {
1376	do_interrupt_real(intno, is_int, error_code, next_eip);
1377	}
1378	}
1379
1380	/*
1381	* Signal an interruption. It is executed in the main CPU loop.
1382	* is_int is TRUE if coming from the int instruction. next_eip is the
1383	* EIP value AFTER the interrupt instruction. It is only relevant if
1384	* is_int is TRUE.
1385	*/
1386	void raise_interrupt(int intno, int is_int, int error_code,
1387	int next_eip_addend)
1388	{
1389	#if defined(VBOX) && defined(DEBUG)
1390	NOT_DMIK(Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend)));
1391	#endif
1392	env->exception_index = intno;
1393	env->error_code = error_code;
1394	env->exception_is_int = is_int;
1395	env->exception_next_eip = env->eip + next_eip_addend;
1396	cpu_loop_exit();
1397	}
1398
1399	/* same as raise_exception_err, but do not restore global registers */
1400	static void raise_exception_err_norestore(int exception_index, int error_code)
1401	{
1402	env->exception_index = exception_index;
1403	env->error_code = error_code;
1404	env->exception_is_int = 0;
1405	env->exception_next_eip = 0;
1406	longjmp(env->jmp_env, 1);
1407	}
1408
1409	/* shortcuts to generate exceptions */
1410
1411	void (raise_exception_err)(int exception_index, int error_code)
1412	{
1413	raise_interrupt(exception_index, 0, error_code, 0);
1414	}
1415
1416	void raise_exception(int exception_index)
1417	{
1418	raise_interrupt(exception_index, 0, 0, 0);
1419	}
1420
1421	/* SMM support */
1422
1423	#if defined(CONFIG_USER_ONLY)
1424
1425	void do_smm_enter(void)
1426	{
1427	}
1428
1429	void helper_rsm(void)
1430	{
1431	}
1432
1433	#else
1434
1435	#ifdef TARGET_X86_64
1436	#define SMM_REVISION_ID 0x00020064
1437	#else
1438	#define SMM_REVISION_ID 0x00020000
1439	#endif
1440
1441	void do_smm_enter(void)
1442	{
1443	#ifdef VBOX
1444	cpu_abort(env, "do_ssm_enter");
1445	#else /* !VBOX */
1446	target_ulong sm_state;
1447	SegmentCache *dt;
1448	int i, offset;
1449
1450	if (loglevel & CPU_LOG_INT) {
1451	fprintf(logfile, "SMM: enter\n");
1452	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1453	}
1454
1455	env->hflags \|= HF_SMM_MASK;
1456	cpu_smm_update(env);
1457
1458	sm_state = env->smbase + 0x8000;
1459
1460	#ifdef TARGET_X86_64
1461	for(i = 0; i < 6; i++) {
1462	dt = &env->segs[i];
1463	offset = 0x7e00 + i * 16;
1464	stw_phys(sm_state + offset, dt->selector);
1465	stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1466	stl_phys(sm_state + offset + 4, dt->limit);
1467	stq_phys(sm_state + offset + 8, dt->base);
1468	}
1469
1470	stq_phys(sm_state + 0x7e68, env->gdt.base);
1471	stl_phys(sm_state + 0x7e64, env->gdt.limit);
1472
1473	stw_phys(sm_state + 0x7e70, env->ldt.selector);
1474	stq_phys(sm_state + 0x7e78, env->ldt.base);
1475	stl_phys(sm_state + 0x7e74, env->ldt.limit);
1476	stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1477
1478	stq_phys(sm_state + 0x7e88, env->idt.base);
1479	stl_phys(sm_state + 0x7e84, env->idt.limit);
1480
1481	stw_phys(sm_state + 0x7e90, env->tr.selector);
1482	stq_phys(sm_state + 0x7e98, env->tr.base);
1483	stl_phys(sm_state + 0x7e94, env->tr.limit);
1484	stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1485
1486	stq_phys(sm_state + 0x7ed0, env->efer);
1487
1488	stq_phys(sm_state + 0x7ff8, EAX);
1489	stq_phys(sm_state + 0x7ff0, ECX);
1490	stq_phys(sm_state + 0x7fe8, EDX);
1491	stq_phys(sm_state + 0x7fe0, EBX);
1492	stq_phys(sm_state + 0x7fd8, ESP);
1493	stq_phys(sm_state + 0x7fd0, EBP);
1494	stq_phys(sm_state + 0x7fc8, ESI);
1495	stq_phys(sm_state + 0x7fc0, EDI);
1496	for(i = 8; i < 16; i++)
1497	stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1498	stq_phys(sm_state + 0x7f78, env->eip);
1499	stl_phys(sm_state + 0x7f70, compute_eflags());
1500	stl_phys(sm_state + 0x7f68, env->dr[6]);
1501	stl_phys(sm_state + 0x7f60, env->dr[7]);
1502
1503	stl_phys(sm_state + 0x7f48, env->cr[4]);
1504	stl_phys(sm_state + 0x7f50, env->cr[3]);
1505	stl_phys(sm_state + 0x7f58, env->cr[0]);
1506
1507	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1508	stl_phys(sm_state + 0x7f00, env->smbase);
1509	#else
1510	stl_phys(sm_state + 0x7ffc, env->cr[0]);
1511	stl_phys(sm_state + 0x7ff8, env->cr[3]);
1512	stl_phys(sm_state + 0x7ff4, compute_eflags());
1513	stl_phys(sm_state + 0x7ff0, env->eip);
1514	stl_phys(sm_state + 0x7fec, EDI);
1515	stl_phys(sm_state + 0x7fe8, ESI);
1516	stl_phys(sm_state + 0x7fe4, EBP);
1517	stl_phys(sm_state + 0x7fe0, ESP);
1518	stl_phys(sm_state + 0x7fdc, EBX);
1519	stl_phys(sm_state + 0x7fd8, EDX);
1520	stl_phys(sm_state + 0x7fd4, ECX);
1521	stl_phys(sm_state + 0x7fd0, EAX);
1522	stl_phys(sm_state + 0x7fcc, env->dr[6]);
1523	stl_phys(sm_state + 0x7fc8, env->dr[7]);
1524
1525	stl_phys(sm_state + 0x7fc4, env->tr.selector);
1526	stl_phys(sm_state + 0x7f64, env->tr.base);
1527	stl_phys(sm_state + 0x7f60, env->tr.limit);
1528	stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1529
1530	stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1531	stl_phys(sm_state + 0x7f80, env->ldt.base);
1532	stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1533	stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1534
1535	stl_phys(sm_state + 0x7f74, env->gdt.base);
1536	stl_phys(sm_state + 0x7f70, env->gdt.limit);
1537
1538	stl_phys(sm_state + 0x7f58, env->idt.base);
1539	stl_phys(sm_state + 0x7f54, env->idt.limit);
1540
1541	for(i = 0; i < 6; i++) {
1542	dt = &env->segs[i];
1543	if (i < 3)
1544	offset = 0x7f84 + i * 12;
1545	else
1546	offset = 0x7f2c + (i - 3) * 12;
1547	stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1548	stl_phys(sm_state + offset + 8, dt->base);
1549	stl_phys(sm_state + offset + 4, dt->limit);
1550	stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1551	}
1552	stl_phys(sm_state + 0x7f14, env->cr[4]);
1553
1554	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1555	stl_phys(sm_state + 0x7ef8, env->smbase);
1556	#endif
1557	/* init SMM cpu state */
1558
1559	#ifdef TARGET_X86_64
1560	env->efer = 0;
1561	env->hflags &= ~HF_LMA_MASK;
1562	#endif
1563	load_eflags(0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1564	env->eip = 0x00008000;
1565	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1566	0xffffffff, 0);
1567	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1568	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1569	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1570	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1571	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1572
1573	cpu_x86_update_cr0(env,
1574	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \| CR0_PG_MASK));
1575	cpu_x86_update_cr4(env, 0);
1576	env->dr[7] = 0x00000400;
1577	CC_OP = CC_OP_EFLAGS;
1578	#endif /* VBOX */
1579	}
1580
1581	void helper_rsm(void)
1582	{
1583	#ifdef VBOX
1584	cpu_abort(env, "helper_rsm");
1585	#else /* !VBOX */
1586	target_ulong sm_state;
1587	int i, offset;
1588	uint32_t val;
1589
1590	sm_state = env->smbase + 0x8000;
1591	#ifdef TARGET_X86_64
1592	env->efer = ldq_phys(sm_state + 0x7ed0);
1593	if (env->efer & MSR_EFER_LMA)
1594	env->hflags \|= HF_LMA_MASK;
1595	else
1596	env->hflags &= ~HF_LMA_MASK;
1597
1598	for(i = 0; i < 6; i++) {
1599	offset = 0x7e00 + i * 16;
1600	cpu_x86_load_seg_cache(env, i,
1601	lduw_phys(sm_state + offset),
1602	ldq_phys(sm_state + offset + 8),
1603	ldl_phys(sm_state + offset + 4),
1604	(lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1605	}
1606
1607	env->gdt.base = ldq_phys(sm_state + 0x7e68);
1608	env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1609
1610	env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1611	env->ldt.base = ldq_phys(sm_state + 0x7e78);
1612	env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1613	env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1614
1615	env->idt.base = ldq_phys(sm_state + 0x7e88);
1616	env->idt.limit = ldl_phys(sm_state + 0x7e84);
1617
1618	env->tr.selector = lduw_phys(sm_state + 0x7e90);
1619	env->tr.base = ldq_phys(sm_state + 0x7e98);
1620	env->tr.limit = ldl_phys(sm_state + 0x7e94);
1621	env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1622
1623	EAX = ldq_phys(sm_state + 0x7ff8);
1624	ECX = ldq_phys(sm_state + 0x7ff0);
1625	EDX = ldq_phys(sm_state + 0x7fe8);
1626	EBX = ldq_phys(sm_state + 0x7fe0);
1627	ESP = ldq_phys(sm_state + 0x7fd8);
1628	EBP = ldq_phys(sm_state + 0x7fd0);
1629	ESI = ldq_phys(sm_state + 0x7fc8);
1630	EDI = ldq_phys(sm_state + 0x7fc0);
1631	for(i = 8; i < 16; i++)
1632	env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1633	env->eip = ldq_phys(sm_state + 0x7f78);
1634	load_eflags(ldl_phys(sm_state + 0x7f70),
1635	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1636	env->dr[6] = ldl_phys(sm_state + 0x7f68);
1637	env->dr[7] = ldl_phys(sm_state + 0x7f60);
1638
1639	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1640	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1641	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1642
1643	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1644	if (val & 0x20000) {
1645	env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1646	}
1647	#else
1648	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1649	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1650	load_eflags(ldl_phys(sm_state + 0x7ff4),
1651	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1652	env->eip = ldl_phys(sm_state + 0x7ff0);
1653	EDI = ldl_phys(sm_state + 0x7fec);
1654	ESI = ldl_phys(sm_state + 0x7fe8);
1655	EBP = ldl_phys(sm_state + 0x7fe4);
1656	ESP = ldl_phys(sm_state + 0x7fe0);
1657	EBX = ldl_phys(sm_state + 0x7fdc);
1658	EDX = ldl_phys(sm_state + 0x7fd8);
1659	ECX = ldl_phys(sm_state + 0x7fd4);
1660	EAX = ldl_phys(sm_state + 0x7fd0);
1661	env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1662	env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1663
1664	env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1665	env->tr.base = ldl_phys(sm_state + 0x7f64);
1666	env->tr.limit = ldl_phys(sm_state + 0x7f60);
1667	env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1668
1669	env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1670	env->ldt.base = ldl_phys(sm_state + 0x7f80);
1671	env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1672	env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1673
1674	env->gdt.base = ldl_phys(sm_state + 0x7f74);
1675	env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1676
1677	env->idt.base = ldl_phys(sm_state + 0x7f58);
1678	env->idt.limit = ldl_phys(sm_state + 0x7f54);
1679
1680	for(i = 0; i < 6; i++) {
1681	if (i < 3)
1682	offset = 0x7f84 + i * 12;
1683	else
1684	offset = 0x7f2c + (i - 3) * 12;
1685	cpu_x86_load_seg_cache(env, i,
1686	ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1687	ldl_phys(sm_state + offset + 8),
1688	ldl_phys(sm_state + offset + 4),
1689	(ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1690	}
1691	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1692
1693	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1694	if (val & 0x20000) {
1695	env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1696	}
1697	#endif
1698	CC_OP = CC_OP_EFLAGS;
1699	env->hflags &= ~HF_SMM_MASK;
1700	cpu_smm_update(env);
1701
1702	if (loglevel & CPU_LOG_INT) {
1703	fprintf(logfile, "SMM: after RSM\n");
1704	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1705	}
1706	#endif /* !VBOX */
1707	}
1708
1709	#endif /* !CONFIG_USER_ONLY */
1710
1711
1712	#ifdef BUGGY_GCC_DIV64
1713	/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1714	call it from another function */
1715	uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1716	{
1717	*q_ptr = num / den;
1718	return num % den;
1719	}
1720
1721	int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1722	{
1723	*q_ptr = num / den;
1724	return num % den;
1725	}
1726	#endif
1727
1728	void helper_divl_EAX_T0(void)
1729	{
1730	unsigned int den, r;
1731	uint64_t num, q;
1732
1733	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1734	den = T0;
1735	if (den == 0) {
1736	raise_exception(EXCP00_DIVZ);
1737	}
1738	#ifdef BUGGY_GCC_DIV64
1739	r = div32(&q, num, den);
1740	#else
1741	q = (num / den);
1742	r = (num % den);
1743	#endif
1744	if (q > 0xffffffff)
1745	raise_exception(EXCP00_DIVZ);
1746	EAX = (uint32_t)q;
1747	EDX = (uint32_t)r;
1748	}
1749
1750	void helper_idivl_EAX_T0(void)
1751	{
1752	int den, r;
1753	int64_t num, q;
1754
1755	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1756	den = T0;
1757	if (den == 0) {
1758	raise_exception(EXCP00_DIVZ);
1759	}
1760	#ifdef BUGGY_GCC_DIV64
1761	r = idiv32(&q, num, den);
1762	#else
1763	q = (num / den);
1764	r = (num % den);
1765	#endif
1766	if (q != (int32_t)q)
1767	raise_exception(EXCP00_DIVZ);
1768	EAX = (uint32_t)q;
1769	EDX = (uint32_t)r;
1770	}
1771
1772	void helper_cmpxchg8b(void)
1773	{
1774	uint64_t d;
1775	int eflags;
1776
1777	eflags = cc_table[CC_OP].compute_all();
1778	d = ldq(A0);
1779	if (d == (((uint64_t)EDX << 32) \| EAX)) {
1780	stq(A0, ((uint64_t)ECX << 32) \| EBX);
1781	eflags \|= CC_Z;
1782	} else {
1783	/* always do the store */
1784	stq(A0, d);
1785	EDX = (uint32_t)(d >> 32);
1786	EAX = (uint32_t)d;
1787	eflags &= ~CC_Z;
1788	}
1789	CC_SRC = eflags;
1790	}
1791
1792	void helper_single_step()
1793	{
1794	env->dr[6] \|= 0x4000;
1795	raise_exception(EXCP01_SSTP);
1796	}
1797
1798	void helper_cpuid(void)
1799	{
1800	#ifndef VBOX
1801	uint32_t index;
1802	index = (uint32_t)EAX;
1803
1804	/* test if maximum index reached */
1805	if (index & 0x80000000) {
1806	if (index > env->cpuid_xlevel)
1807	index = env->cpuid_level;
1808	} else {
1809	if (index > env->cpuid_level)
1810	index = env->cpuid_level;
1811	}
1812
1813	switch(index) {
1814	case 0:
1815	EAX = env->cpuid_level;
1816	EBX = env->cpuid_vendor1;
1817	EDX = env->cpuid_vendor2;
1818	ECX = env->cpuid_vendor3;
1819	break;
1820	case 1:
1821	EAX = env->cpuid_version;
1822	EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1823	ECX = env->cpuid_ext_features;
1824	EDX = env->cpuid_features;
1825	break;
1826	case 2:
1827	/* cache info: needed for Pentium Pro compatibility */
1828	EAX = 0x410601;
1829	EBX = 0;
1830	ECX = 0;
1831	EDX = 0;
1832	break;
1833	case 0x80000000:
1834	EAX = env->cpuid_xlevel;
1835	EBX = env->cpuid_vendor1;
1836	EDX = env->cpuid_vendor2;
1837	ECX = env->cpuid_vendor3;
1838	break;
1839	case 0x80000001:
1840	EAX = env->cpuid_features;
1841	EBX = 0;
1842	ECX = 0;
1843	EDX = env->cpuid_ext2_features;
1844	break;
1845	case 0x80000002:
1846	case 0x80000003:
1847	case 0x80000004:
1848	EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1849	EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1850	ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1851	EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1852	break;
1853	case 0x80000005:
1854	/* cache info (L1 cache) */
1855	EAX = 0x01ff01ff;
1856	EBX = 0x01ff01ff;
1857	ECX = 0x40020140;
1858	EDX = 0x40020140;
1859	break;
1860	case 0x80000006:
1861	/* cache info (L2 cache) */
1862	EAX = 0;
1863	EBX = 0x42004200;
1864	ECX = 0x02008140;
1865	EDX = 0;
1866	break;
1867	case 0x80000008:
1868	/* virtual & phys address size in low 2 bytes. */
1869	EAX = 0x00003028;
1870	EBX = 0;
1871	ECX = 0;
1872	EDX = 0;
1873	break;
1874	default:
1875	/* reserved values: zero */
1876	EAX = 0;
1877	EBX = 0;
1878	ECX = 0;
1879	EDX = 0;
1880	break;
1881	}
1882	#else /* VBOX */
1883	remR3CpuId(env, EAX, &EAX, &EBX, &ECX, &EDX);
1884	#endif /* VBOX */
1885	}
1886
1887	void helper_enter_level(int level, int data32)
1888	{
1889	target_ulong ssp;
1890	uint32_t esp_mask, esp, ebp;
1891
1892	esp_mask = get_sp_mask(env->segs[R_SS].flags);
1893	ssp = env->segs[R_SS].base;
1894	ebp = EBP;
1895	esp = ESP;
1896	if (data32) {
1897	/* 32 bit */
1898	esp -= 4;
1899	while (--level) {
1900	esp -= 4;
1901	ebp -= 4;
1902	stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1903	}
1904	esp -= 4;
1905	stl(ssp + (esp & esp_mask), T1);
1906	} else {
1907	/* 16 bit */
1908	esp -= 2;
1909	while (--level) {
1910	esp -= 2;
1911	ebp -= 2;
1912	stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1913	}
1914	esp -= 2;
1915	stw(ssp + (esp & esp_mask), T1);
1916	}
1917	}
1918
1919	#ifdef TARGET_X86_64
1920	void helper_enter64_level(int level, int data64)
1921	{
1922	target_ulong esp, ebp;
1923	ebp = EBP;
1924	esp = ESP;
1925
1926	if (data64) {
1927	/* 64 bit */
1928	esp -= 8;
1929	while (--level) {
1930	esp -= 8;
1931	ebp -= 8;
1932	stq(esp, ldq(ebp));
1933	}
1934	esp -= 8;
1935	stq(esp, T1);
1936	} else {
1937	/* 16 bit */
1938	esp -= 2;
1939	while (--level) {
1940	esp -= 2;
1941	ebp -= 2;
1942	stw(esp, lduw(ebp));
1943	}
1944	esp -= 2;
1945	stw(esp, T1);
1946	}
1947	}
1948	#endif
1949
1950	void helper_lldt_T0(void)
1951	{
1952	int selector;
1953	SegmentCache *dt;
1954	uint32_t e1, e2;
1955	int index, entry_limit;
1956	target_ulong ptr;
1957	#ifdef VBOX
1958	Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
1959	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
1960	#endif
1961
1962	selector = T0 & 0xffff;
1963	if ((selector & 0xfffc) == 0) {
1964	/* XXX: NULL selector case: invalid LDT */
1965	env->ldt.base = 0;
1966	env->ldt.limit = 0;
1967	} else {
1968	if (selector & 0x4)
1969	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1970	dt = &env->gdt;
1971	index = selector & ~7;
1972	#ifdef TARGET_X86_64
1973	if (env->hflags & HF_LMA_MASK)
1974	entry_limit = 15;
1975	else
1976	#endif
1977	entry_limit = 7;
1978	if ((index + entry_limit) > dt->limit)
1979	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1980	ptr = dt->base + index;
1981	e1 = ldl_kernel(ptr);
1982	e2 = ldl_kernel(ptr + 4);
1983	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1984	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1985	if (!(e2 & DESC_P_MASK))
1986	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1987	#ifdef TARGET_X86_64
1988	if (env->hflags & HF_LMA_MASK) {
1989	uint32_t e3;
1990	e3 = ldl_kernel(ptr + 8);
1991	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1992	env->ldt.base \|= (target_ulong)e3 << 32;
1993	} else
1994	#endif
1995	{
1996	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1997	}
1998	}
1999	env->ldt.selector = selector;
2000	#ifdef VBOX
2001	Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
2002	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
2003	#endif
2004	}
2005
2006	void helper_ltr_T0(void)
2007	{
2008	int selector;
2009	SegmentCache *dt;
2010	uint32_t e1, e2;
2011	int index, type, entry_limit;
2012	target_ulong ptr;
2013
2014	#ifdef VBOX
2015	Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2016	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2017	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2018	#endif
2019
2020	selector = T0 & 0xffff;
2021	if ((selector & 0xfffc) == 0) {
2022	/* NULL selector case: invalid TR */
2023	env->tr.base = 0;
2024	env->tr.limit = 0;
2025	env->tr.flags = 0;
2026	} else {
2027	if (selector & 0x4)
2028	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2029	dt = &env->gdt;
2030	index = selector & ~7;
2031	#ifdef TARGET_X86_64
2032	if (env->hflags & HF_LMA_MASK)
2033	entry_limit = 15;
2034	else
2035	#endif
2036	entry_limit = 7;
2037	if ((index + entry_limit) > dt->limit)
2038	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2039	ptr = dt->base + index;
2040	e1 = ldl_kernel(ptr);
2041	e2 = ldl_kernel(ptr + 4);
2042	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2043	if ((e2 & DESC_S_MASK) \|\|
2044	(type != 1 && type != 9))
2045	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2046	if (!(e2 & DESC_P_MASK))
2047	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2048	#ifdef TARGET_X86_64
2049	if (env->hflags & HF_LMA_MASK) {
2050	uint32_t e3;
2051	e3 = ldl_kernel(ptr + 8);
2052	load_seg_cache_raw_dt(&env->tr, e1, e2);
2053	env->tr.base \|= (target_ulong)e3 << 32;
2054	} else
2055	#endif
2056	{
2057	load_seg_cache_raw_dt(&env->tr, e1, e2);
2058	}
2059	e2 \|= DESC_TSS_BUSY_MASK;
2060	stl_kernel(ptr + 4, e2);
2061	}
2062	env->tr.selector = selector;
2063	#ifdef VBOX
2064	Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2065	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2066	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2067	#endif
2068	}
2069
2070	/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2071	void load_seg(int seg_reg, int selector)
2072	{
2073	uint32_t e1, e2;
2074	int cpl, dpl, rpl;
2075	SegmentCache *dt;
2076	int index;
2077	target_ulong ptr;
2078
2079	selector &= 0xffff;
2080	cpl = env->hflags & HF_CPL_MASK;
2081
2082	#ifdef VBOX
2083	/* Trying to load a selector with CPL=1? */
2084	if (cpl == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0))
2085	{
2086	Log(("RPL 1 -> sel %04X -> %04X\n", selector, selector & 0xfffc));
2087	selector = selector & 0xfffc;
2088	}
2089	#endif
2090
2091	if ((selector & 0xfffc) == 0) {
2092	/* null selector case */
2093	if (seg_reg == R_SS
2094	#ifdef TARGET_X86_64
2095	&& (!(env->hflags & HF_CS64_MASK) \|\| cpl == 3)
2096	#endif
2097	)
2098	raise_exception_err(EXCP0D_GPF, 0);
2099	cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2100	} else {
2101
2102	if (selector & 0x4)
2103	dt = &env->ldt;
2104	else
2105	dt = &env->gdt;
2106	index = selector & ~7;
2107	if ((index + 7) > dt->limit)
2108	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2109	ptr = dt->base + index;
2110	e1 = ldl_kernel(ptr);
2111	e2 = ldl_kernel(ptr + 4);
2112
2113	if (!(e2 & DESC_S_MASK))
2114	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2115	rpl = selector & 3;
2116	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2117	if (seg_reg == R_SS) {
2118	/* must be writable segment */
2119	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
2120	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2121	if (rpl != cpl \|\| dpl != cpl)
2122	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2123	} else {
2124	/* must be readable segment */
2125	if ((e2 & (DESC_CS_MASK \| DESC_R_MASK)) == DESC_CS_MASK)
2126	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2127
2128	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2129	/* if not conforming code, test rights */
2130	if (dpl < cpl \|\| dpl < rpl)
2131	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2132	}
2133	}
2134
2135	if (!(e2 & DESC_P_MASK)) {
2136	if (seg_reg == R_SS)
2137	raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
2138	else
2139	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2140	}
2141
2142	/* set the access bit if not already set */
2143	if (!(e2 & DESC_A_MASK)) {
2144	e2 \|= DESC_A_MASK;
2145	stl_kernel(ptr + 4, e2);
2146	}
2147
2148	cpu_x86_load_seg_cache(env, seg_reg, selector,
2149	get_seg_base(e1, e2),
2150	get_seg_limit(e1, e2),
2151	e2);
2152	#if 0
2153	fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
2154	selector, (unsigned long)sc->base, sc->limit, sc->flags);
2155	#endif
2156	}
2157	}
2158
2159	/* protected mode jump */
2160	void helper_ljmp_protected_T0_T1(int next_eip_addend)
2161	{
2162	int new_cs, gate_cs, type;
2163	uint32_t e1, e2, cpl, dpl, rpl, limit;
2164	target_ulong new_eip, next_eip;
2165
2166	new_cs = T0;
2167	new_eip = T1;
2168	if ((new_cs & 0xfffc) == 0)
2169	raise_exception_err(EXCP0D_GPF, 0);
2170	if (load_segment(&e1, &e2, new_cs) != 0)
2171	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2172	cpl = env->hflags & HF_CPL_MASK;
2173	if (e2 & DESC_S_MASK) {
2174	if (!(e2 & DESC_CS_MASK))
2175	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2176	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2177	if (e2 & DESC_C_MASK) {
2178	/* conforming code segment */
2179	if (dpl > cpl)
2180	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2181	} else {
2182	/* non conforming code segment */
2183	rpl = new_cs & 3;
2184	if (rpl > cpl)
2185	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2186	if (dpl != cpl)
2187	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2188	}
2189	if (!(e2 & DESC_P_MASK))
2190	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2191	limit = get_seg_limit(e1, e2);
2192	if (new_eip > limit &&
2193	!(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
2194	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2195	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2196	get_seg_base(e1, e2), limit, e2);
2197	EIP = new_eip;
2198	} else {
2199	/* jump to call or task gate */
2200	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2201	rpl = new_cs & 3;
2202	cpl = env->hflags & HF_CPL_MASK;
2203	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2204	switch(type) {
2205	case 1: /* 286 TSS */
2206	case 9: /* 386 TSS */
2207	case 5: /* task gate */
2208	if (dpl < cpl \|\| dpl < rpl)
2209	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2210	next_eip = env->eip + next_eip_addend;
2211	switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
2212	CC_OP = CC_OP_EFLAGS;
2213	break;
2214	case 4: /* 286 call gate */
2215	case 12: /* 386 call gate */
2216	if ((dpl < cpl) \|\| (dpl < rpl))
2217	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2218	if (!(e2 & DESC_P_MASK))
2219	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2220	gate_cs = e1 >> 16;
2221	new_eip = (e1 & 0xffff);
2222	if (type == 12)
2223	new_eip \|= (e2 & 0xffff0000);
2224	if (load_segment(&e1, &e2, gate_cs) != 0)
2225	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2226	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2227	/* must be code segment */
2228	if (((e2 & (DESC_S_MASK \| DESC_CS_MASK)) !=
2229	(DESC_S_MASK \| DESC_CS_MASK)))
2230	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2231	if (((e2 & DESC_C_MASK) && (dpl > cpl)) \|\|
2232	(!(e2 & DESC_C_MASK) && (dpl != cpl)))
2233	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2234	if (!(e2 & DESC_P_MASK))
2235	#ifdef VBOX /* See page 3-514 of 253666.pdf */
2236	raise_exception_err(EXCP0B_NOSEG, gate_cs & 0xfffc);
2237	#else
2238	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2239	#endif
2240	limit = get_seg_limit(e1, e2);
2241	if (new_eip > limit)
2242	raise_exception_err(EXCP0D_GPF, 0);
2243	cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) \| cpl,
2244	get_seg_base(e1, e2), limit, e2);
2245	EIP = new_eip;
2246	break;
2247	default:
2248	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2249	break;
2250	}
2251	}
2252	}
2253
2254	/* real mode call */
2255	void helper_lcall_real_T0_T1(int shift, int next_eip)
2256	{
2257	int new_cs, new_eip;
2258	uint32_t esp, esp_mask;
2259	target_ulong ssp;
2260
2261	new_cs = T0;
2262	new_eip = T1;
2263	esp = ESP;
2264	esp_mask = get_sp_mask(env->segs[R_SS].flags);
2265	ssp = env->segs[R_SS].base;
2266	if (shift) {
2267	PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2268	PUSHL(ssp, esp, esp_mask, next_eip);
2269	} else {
2270	PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2271	PUSHW(ssp, esp, esp_mask, next_eip);
2272	}
2273
2274	SET_ESP(esp, esp_mask);
2275	env->eip = new_eip;
2276	env->segs[R_CS].selector = new_cs;
2277	env->segs[R_CS].base = (new_cs << 4);
2278	}
2279
2280	/* protected mode call */
2281	void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
2282	{
2283	int new_cs, new_stack, i;
2284	uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
2285	uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
2286	uint32_t val, limit, old_sp_mask;
2287	target_ulong ssp, old_ssp, next_eip, new_eip;
2288
2289	new_cs = T0;
2290	new_eip = T1;
2291	next_eip = env->eip + next_eip_addend;
2292	#ifdef DEBUG_PCALL
2293	if (loglevel & CPU_LOG_PCALL) {
2294	fprintf(logfile, "lcall %04x:%08x s=%d\n",
2295	new_cs, (uint32_t)new_eip, shift);
2296	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2297	}
2298	#endif
2299	if ((new_cs & 0xfffc) == 0)
2300	raise_exception_err(EXCP0D_GPF, 0);
2301	if (load_segment(&e1, &e2, new_cs) != 0)
2302	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2303	cpl = env->hflags & HF_CPL_MASK;
2304	#ifdef DEBUG_PCALL
2305	if (loglevel & CPU_LOG_PCALL) {
2306	fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
2307	}
2308	#endif
2309	if (e2 & DESC_S_MASK) {
2310	if (!(e2 & DESC_CS_MASK))
2311	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2312	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2313	if (e2 & DESC_C_MASK) {
2314	/* conforming code segment */
2315	if (dpl > cpl)
2316	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2317	} else {
2318	/* non conforming code segment */
2319	rpl = new_cs & 3;
2320	if (rpl > cpl)
2321	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2322	if (dpl != cpl)
2323	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2324	}
2325	if (!(e2 & DESC_P_MASK))
2326	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2327
2328	#ifdef TARGET_X86_64
2329	/* XXX: check 16/32 bit cases in long mode */
2330	if (shift == 2) {
2331	target_ulong rsp;
2332	/* 64 bit case */
2333	rsp = ESP;
2334	PUSHQ(rsp, env->segs[R_CS].selector);
2335	PUSHQ(rsp, next_eip);
2336	/* from this point, not restartable */
2337	ESP = rsp;
2338	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2339	get_seg_base(e1, e2),
2340	get_seg_limit(e1, e2), e2);
2341	EIP = new_eip;
2342	} else
2343	#endif
2344	{
2345	sp = ESP;
2346	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2347	ssp = env->segs[R_SS].base;
2348	if (shift) {
2349	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2350	PUSHL(ssp, sp, sp_mask, next_eip);
2351	} else {
2352	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2353	PUSHW(ssp, sp, sp_mask, next_eip);
2354	}
2355
2356	limit = get_seg_limit(e1, e2);
2357	if (new_eip > limit)
2358	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2359	/* from this point, not restartable */
2360	SET_ESP(sp, sp_mask);
2361	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2362	get_seg_base(e1, e2), limit, e2);
2363	EIP = new_eip;
2364	}
2365	} else {
2366	/* check gate type */
2367	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
2368	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2369	rpl = new_cs & 3;
2370	switch(type) {
2371	case 1: /* available 286 TSS */
2372	case 9: /* available 386 TSS */
2373	case 5: /* task gate */
2374	if (dpl < cpl \|\| dpl < rpl)
2375	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2376	switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
2377	CC_OP = CC_OP_EFLAGS;
2378	return;
2379	case 4: /* 286 call gate */
2380	case 12: /* 386 call gate */
2381	break;
2382	default:
2383	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2384	break;
2385	}
2386	shift = type >> 3;
2387
2388	if (dpl < cpl \|\| dpl < rpl)
2389	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2390	/* check valid bit */
2391	if (!(e2 & DESC_P_MASK))
2392	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2393	selector = e1 >> 16;
2394	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
2395	param_count = e2 & 0x1f;
2396	if ((selector & 0xfffc) == 0)
2397	raise_exception_err(EXCP0D_GPF, 0);
2398
2399	if (load_segment(&e1, &e2, selector) != 0)
2400	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2401	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
2402	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2403	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2404	if (dpl > cpl)
2405	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2406	if (!(e2 & DESC_P_MASK))
2407	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2408
2409	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2410	/* to inner priviledge */
2411	get_ss_esp_from_tss(&ss, &sp, dpl);
2412	#ifdef DEBUG_PCALL
2413	if (loglevel & CPU_LOG_PCALL)
2414	fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2415	ss, sp, param_count, ESP);
2416	#endif
2417	if ((ss & 0xfffc) == 0)
2418	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2419	if ((ss & 3) != dpl)
2420	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2421	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2422	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2423	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2424	if (ss_dpl != dpl)
2425	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2426	if (!(ss_e2 & DESC_S_MASK) \|\|
2427	(ss_e2 & DESC_CS_MASK) \|\|
2428	!(ss_e2 & DESC_W_MASK))
2429	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2430	if (!(ss_e2 & DESC_P_MASK))
2431	#ifdef VBOX /* See page 3-99 of 253666.pdf */
2432	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
2433	#else
2434	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2435	#endif
2436
2437	// push_size = ((param_count * 2) + 8) << shift;
2438
2439	old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2440	old_ssp = env->segs[R_SS].base;
2441
2442	sp_mask = get_sp_mask(ss_e2);
2443	ssp = get_seg_base(ss_e1, ss_e2);
2444	if (shift) {
2445	PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2446	PUSHL(ssp, sp, sp_mask, ESP);
2447	for(i = param_count - 1; i >= 0; i--) {
2448	val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2449	PUSHL(ssp, sp, sp_mask, val);
2450	}
2451	} else {
2452	PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2453	PUSHW(ssp, sp, sp_mask, ESP);
2454	for(i = param_count - 1; i >= 0; i--) {
2455	val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2456	PUSHW(ssp, sp, sp_mask, val);
2457	}
2458	}
2459	new_stack = 1;
2460	} else {
2461	/* to same priviledge */
2462	sp = ESP;
2463	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2464	ssp = env->segs[R_SS].base;
2465	// push_size = (4 << shift);
2466	new_stack = 0;
2467	}
2468
2469	if (shift) {
2470	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2471	PUSHL(ssp, sp, sp_mask, next_eip);
2472	} else {
2473	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2474	PUSHW(ssp, sp, sp_mask, next_eip);
2475	}
2476
2477	/* from this point, not restartable */
2478
2479	if (new_stack) {
2480	ss = (ss & ~3) \| dpl;
2481	cpu_x86_load_seg_cache(env, R_SS, ss,
2482	ssp,
2483	get_seg_limit(ss_e1, ss_e2),
2484	ss_e2);
2485	}
2486
2487	selector = (selector & ~3) \| dpl;
2488	cpu_x86_load_seg_cache(env, R_CS, selector,
2489	get_seg_base(e1, e2),
2490	get_seg_limit(e1, e2),
2491	e2);
2492	cpu_x86_set_cpl(env, dpl);
2493	SET_ESP(sp, sp_mask);
2494	EIP = offset;
2495	}
2496	#ifdef USE_KQEMU
2497	if (kqemu_is_ok(env)) {
2498	env->exception_index = -1;
2499	cpu_loop_exit();
2500	}
2501	#endif
2502	}
2503
2504	/* real and vm86 mode iret */
2505	void helper_iret_real(int shift)
2506	{
2507	uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2508	target_ulong ssp;
2509	int eflags_mask;
2510	#ifdef VBOX
2511	bool fVME = false;
2512
2513	remR3TrapClear(env->pVM);
2514	#endif /* VBOX */
2515
2516	sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2517	sp = ESP;
2518	ssp = env->segs[R_SS].base;
2519	if (shift == 1) {
2520	/* 32 bits */
2521	POPL(ssp, sp, sp_mask, new_eip);
2522	POPL(ssp, sp, sp_mask, new_cs);
2523	new_cs &= 0xffff;
2524	POPL(ssp, sp, sp_mask, new_eflags);
2525	} else {
2526	/* 16 bits */
2527	POPW(ssp, sp, sp_mask, new_eip);
2528	POPW(ssp, sp, sp_mask, new_cs);
2529	POPW(ssp, sp, sp_mask, new_eflags);
2530	}
2531	#ifdef VBOX
2532	if ( (env->eflags & VM_MASK)
2533	&& ((env->eflags >> IOPL_SHIFT) & 3) != 3
2534	&& (env->cr[4] & CR4_VME_MASK)) /* implied or else we would fault earlier */
2535	{
2536	fVME = true;
2537	/* if virtual interrupt pending and (virtual) interrupts will be enabled -> #GP */
2538	/* if TF will be set -> #GP */
2539	if ( ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK))
2540	\|\| (new_eflags & TF_MASK))
2541	raise_exception(EXCP0D_GPF);
2542	}
2543	#endif /* VBOX */
2544
2545	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);
2546	load_seg_vm(R_CS, new_cs);
2547	env->eip = new_eip;
2548	#ifdef VBOX
2549	if (fVME)
2550	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2551	else
2552	#endif
2553	if (env->eflags & VM_MASK)
2554	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| RF_MASK \| NT_MASK;
2555	else
2556	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| IOPL_MASK \| RF_MASK \| NT_MASK;
2557	if (shift == 0)
2558	eflags_mask &= 0xffff;
2559	load_eflags(new_eflags, eflags_mask);
2560
2561	#ifdef VBOX
2562	if (fVME)
2563	{
2564	if (new_eflags & IF_MASK)
2565	env->eflags \|= VIF_MASK;
2566	else
2567	env->eflags &= ~VIF_MASK;
2568	}
2569	#endif /* VBOX */
2570	}
2571
2572	static inline void validate_seg(int seg_reg, int cpl)
2573	{
2574	int dpl;
2575	uint32_t e2;
2576
2577	/* XXX: on x86_64, we do not want to nullify FS and GS because
2578	they may still contain a valid base. I would be interested to
2579	know how a real x86_64 CPU behaves */
2580	if ((seg_reg == R_FS \|\| seg_reg == R_GS) &&
2581	(env->segs[seg_reg].selector & 0xfffc) == 0)
2582	return;
2583
2584	e2 = env->segs[seg_reg].flags;
2585	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2586	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2587	/* data or non conforming code segment */
2588	if (dpl < cpl) {
2589	cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2590	}
2591	}
2592	}
2593
2594	/* protected mode iret */
2595	static inline void helper_ret_protected(int shift, int is_iret, int addend)
2596	{
2597	uint32_t new_cs, new_eflags, new_ss;
2598	uint32_t new_es, new_ds, new_fs, new_gs;
2599	uint32_t e1, e2, ss_e1, ss_e2;
2600	int cpl, dpl, rpl, eflags_mask, iopl;
2601	target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2602
2603	#ifdef TARGET_X86_64
2604	if (shift == 2)
2605	sp_mask = -1;
2606	else
2607	#endif
2608	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2609	sp = ESP;
2610	ssp = env->segs[R_SS].base;
2611	new_eflags = 0; /* avoid warning */
2612	#ifdef TARGET_X86_64
2613	if (shift == 2) {
2614	POPQ(sp, new_eip);
2615	POPQ(sp, new_cs);
2616	new_cs &= 0xffff;
2617	if (is_iret) {
2618	POPQ(sp, new_eflags);
2619	}
2620	} else
2621	#endif
2622	if (shift == 1) {
2623	/* 32 bits */
2624	POPL(ssp, sp, sp_mask, new_eip);
2625	POPL(ssp, sp, sp_mask, new_cs);
2626	new_cs &= 0xffff;
2627	if (is_iret) {
2628	POPL(ssp, sp, sp_mask, new_eflags);
2629	#if defined(VBOX) && defined(DEBUG)
2630	printf("iret: new CS %04X\n", new_cs);
2631	printf("iret: new EIP %08X\n", new_eip);
2632	printf("iret: new EFLAGS %08X\n", new_eflags);
2633	printf("iret: EAX=%08x\n", EAX);
2634	#endif
2635
2636	if (new_eflags & VM_MASK)
2637	goto return_to_vm86;
2638	}
2639	#ifdef VBOX
2640	if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
2641	{
2642	#ifdef DEBUG
2643	printf("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc);
2644	#endif
2645	new_cs = new_cs & 0xfffc;
2646	}
2647	#endif
2648	} else {
2649	/* 16 bits */
2650	POPW(ssp, sp, sp_mask, new_eip);
2651	POPW(ssp, sp, sp_mask, new_cs);
2652	if (is_iret)
2653	POPW(ssp, sp, sp_mask, new_eflags);
2654	}
2655	#ifdef DEBUG_PCALL
2656	if (loglevel & CPU_LOG_PCALL) {
2657	fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2658	new_cs, new_eip, shift, addend);
2659	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2660	}
2661	#endif
2662	if ((new_cs & 0xfffc) == 0)
2663	{
2664	#if defined(VBOX) && defined(DEBUG)
2665	printf("new_cs & 0xfffc) == 0\n");
2666	#endif
2667	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2668	}
2669	if (load_segment(&e1, &e2, new_cs) != 0)
2670	{
2671	#if defined(VBOX) && defined(DEBUG)
2672	printf("load_segment failed\n");
2673	#endif
2674	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2675	}
2676	if (!(e2 & DESC_S_MASK) \|\|
2677	!(e2 & DESC_CS_MASK))
2678	{
2679	#if defined(VBOX) && defined(DEBUG)
2680	printf("e2 mask %08x\n", e2);
2681	#endif
2682	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2683	}
2684	cpl = env->hflags & HF_CPL_MASK;
2685	rpl = new_cs & 3;
2686	if (rpl < cpl)
2687	{
2688	#if defined(VBOX) && defined(DEBUG)
2689	printf("rpl < cpl (%d vs %d)\n", rpl, cpl);
2690	#endif
2691	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2692	}
2693	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2694	if (e2 & DESC_C_MASK) {
2695	if (dpl > rpl)
2696	{
2697	#if defined(VBOX) && defined(DEBUG)
2698	printf("dpl > rpl (%d vs %d)\n", dpl, rpl);
2699	#endif
2700	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2701	}
2702	} else {
2703	if (dpl != rpl)
2704	{
2705	#if defined(VBOX) && defined(DEBUG)
2706	printf("dpl != rpl (%d vs %d) e1=%x e2=%x\n", dpl, rpl, e1, e2);
2707	#endif
2708	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2709	}
2710	}
2711	if (!(e2 & DESC_P_MASK))
2712	{
2713	#if defined(VBOX) && defined(DEBUG)
2714	printf("DESC_P_MASK e2=%08x\n", e2);
2715	#endif
2716	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2717	}
2718	sp += addend;
2719	if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) \|\|
2720	((env->hflags & HF_CS64_MASK) && !is_iret))) {
2721	/* return to same priledge level */
2722	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2723	get_seg_base(e1, e2),
2724	get_seg_limit(e1, e2),
2725	e2);
2726	} else {
2727	/* return to different priviledge level */
2728	#ifdef TARGET_X86_64
2729	if (shift == 2) {
2730	POPQ(sp, new_esp);
2731	POPQ(sp, new_ss);
2732	new_ss &= 0xffff;
2733	} else
2734	#endif
2735	if (shift == 1) {
2736	/* 32 bits */
2737	POPL(ssp, sp, sp_mask, new_esp);
2738	POPL(ssp, sp, sp_mask, new_ss);
2739	new_ss &= 0xffff;
2740	} else {
2741	/* 16 bits */
2742	POPW(ssp, sp, sp_mask, new_esp);
2743	POPW(ssp, sp, sp_mask, new_ss);
2744	}
2745	#ifdef DEBUG_PCALL
2746	if (loglevel & CPU_LOG_PCALL) {
2747	fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2748	new_ss, new_esp);
2749	}
2750	#endif
2751	if ((new_ss & 0xfffc) == 0) {
2752	#ifdef TARGET_X86_64
2753	/* NULL ss is allowed in long mode if cpl != 3*/
2754	/* XXX: test CS64 ? */
2755	if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2756	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2757	0, 0xffffffff,
2758	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2759	DESC_S_MASK \| (rpl << DESC_DPL_SHIFT) \|
2760	DESC_W_MASK \| DESC_A_MASK);
2761	ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
2762	} else
2763	#endif
2764	{
2765	raise_exception_err(EXCP0D_GPF, 0);
2766	}
2767	} else {
2768	if ((new_ss & 3) != rpl)
2769	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2770	if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2771	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2772	if (!(ss_e2 & DESC_S_MASK) \|\|
2773	(ss_e2 & DESC_CS_MASK) \|\|
2774	!(ss_e2 & DESC_W_MASK))
2775	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2776	dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2777	if (dpl != rpl)
2778	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2779	if (!(ss_e2 & DESC_P_MASK))
2780	raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2781	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2782	get_seg_base(ss_e1, ss_e2),
2783	get_seg_limit(ss_e1, ss_e2),
2784	ss_e2);
2785	}
2786
2787	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2788	get_seg_base(e1, e2),
2789	get_seg_limit(e1, e2),
2790	e2);
2791	cpu_x86_set_cpl(env, rpl);
2792	sp = new_esp;
2793	#ifdef TARGET_X86_64
2794	if (env->hflags & HF_CS64_MASK)
2795	sp_mask = -1;
2796	else
2797	#endif
2798	sp_mask = get_sp_mask(ss_e2);
2799
2800	/* validate data segments */
2801	validate_seg(R_ES, rpl);
2802	validate_seg(R_DS, rpl);
2803	validate_seg(R_FS, rpl);
2804	validate_seg(R_GS, rpl);
2805
2806	sp += addend;
2807	}
2808	SET_ESP(sp, sp_mask);
2809	env->eip = new_eip;
2810	if (is_iret) {
2811	/* NOTE: 'cpl' is the _old_ CPL */
2812	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2813	if (cpl == 0)
2814	#ifdef VBOX
2815	eflags_mask \|= IOPL_MASK \| VIF_MASK \| VIP_MASK;
2816	#else
2817	eflags_mask \|= IOPL_MASK;
2818	#endif
2819	iopl = (env->eflags >> IOPL_SHIFT) & 3;
2820	if (cpl <= iopl)
2821	eflags_mask \|= IF_MASK;
2822	if (shift == 0)
2823	eflags_mask &= 0xffff;
2824	load_eflags(new_eflags, eflags_mask);
2825	}
2826	return;
2827
2828	return_to_vm86:
2829
2830	#if 0 // defined(VBOX) && defined(DEBUG)
2831	printf("V86: new CS %04X\n", new_cs);
2832	printf("V86: Descriptor %08X:%08X\n", e2, e1);
2833	printf("V86: new EIP %08X\n", new_eip);
2834	printf("V86: new EFLAGS %08X\n", new_eflags);
2835	#endif
2836
2837	POPL(ssp, sp, sp_mask, new_esp);
2838	POPL(ssp, sp, sp_mask, new_ss);
2839	POPL(ssp, sp, sp_mask, new_es);
2840	POPL(ssp, sp, sp_mask, new_ds);
2841	POPL(ssp, sp, sp_mask, new_fs);
2842	POPL(ssp, sp, sp_mask, new_gs);
2843
2844	/* modify processor state */
2845	load_eflags(new_eflags, TF_MASK \| AC_MASK \| ID_MASK \|
2846	IF_MASK \| IOPL_MASK \| VM_MASK \| NT_MASK \| VIF_MASK \| VIP_MASK);
2847	load_seg_vm(R_CS, new_cs & 0xffff);
2848	cpu_x86_set_cpl(env, 3);
2849	load_seg_vm(R_SS, new_ss & 0xffff);
2850	load_seg_vm(R_ES, new_es & 0xffff);
2851	load_seg_vm(R_DS, new_ds & 0xffff);
2852	load_seg_vm(R_FS, new_fs & 0xffff);
2853	load_seg_vm(R_GS, new_gs & 0xffff);
2854
2855	env->eip = new_eip & 0xffff;
2856	ESP = new_esp;
2857	}
2858
2859	void helper_iret_protected(int shift, int next_eip)
2860	{
2861	int tss_selector, type;
2862	uint32_t e1, e2;
2863
2864	#ifdef VBOX
2865	remR3TrapClear(env->pVM);
2866	#endif
2867
2868	/* specific case for TSS */
2869	if (env->eflags & NT_MASK) {
2870	#ifdef TARGET_X86_64
2871	if (env->hflags & HF_LMA_MASK)
2872	raise_exception_err(EXCP0D_GPF, 0);
2873	#endif
2874	tss_selector = lduw_kernel(env->tr.base + 0);
2875	if (tss_selector & 4)
2876	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2877	if (load_segment(&e1, &e2, tss_selector) != 0)
2878	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2879	type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2880	/* NOTE: we check both segment and busy TSS */
2881	if (type != 3)
2882	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2883	switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2884	} else {
2885	helper_ret_protected(shift, 1, 0);
2886	}
2887	#ifdef USE_KQEMU
2888	if (kqemu_is_ok(env)) {
2889	CC_OP = CC_OP_EFLAGS;
2890	env->exception_index = -1;
2891	cpu_loop_exit();
2892	}
2893	#endif
2894	}
2895
2896	void helper_lret_protected(int shift, int addend)
2897	{
2898	helper_ret_protected(shift, 0, addend);
2899	#ifdef USE_KQEMU
2900	if (kqemu_is_ok(env)) {
2901	env->exception_index = -1;
2902	cpu_loop_exit();
2903	}
2904	#endif
2905	}
2906
2907	void helper_sysenter(void)
2908	{
2909	if (env->sysenter_cs == 0) {
2910	raise_exception_err(EXCP0D_GPF, 0);
2911	}
2912	env->eflags &= ~(VM_MASK \| IF_MASK \| RF_MASK);
2913	cpu_x86_set_cpl(env, 0);
2914	cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2915	0, 0xffffffff,
2916	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2917	DESC_S_MASK \|
2918	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2919	cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2920	0, 0xffffffff,
2921	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2922	DESC_S_MASK \|
2923	DESC_W_MASK \| DESC_A_MASK);
2924	ESP = env->sysenter_esp;
2925	EIP = env->sysenter_eip;
2926	}
2927
2928	void helper_sysexit(void)
2929	{
2930	int cpl;
2931
2932	cpl = env->hflags & HF_CPL_MASK;
2933	if (env->sysenter_cs == 0 \|\| cpl != 0) {
2934	raise_exception_err(EXCP0D_GPF, 0);
2935	}
2936	cpu_x86_set_cpl(env, 3);
2937	cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) \| 3,
2938	0, 0xffffffff,
2939	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2940	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2941	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2942	cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) \| 3,
2943	0, 0xffffffff,
2944	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2945	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2946	DESC_W_MASK \| DESC_A_MASK);
2947	ESP = ECX;
2948	EIP = EDX;
2949	#ifdef USE_KQEMU
2950	if (kqemu_is_ok(env)) {
2951	env->exception_index = -1;
2952	cpu_loop_exit();
2953	}
2954	#endif
2955	}
2956
2957	void helper_movl_crN_T0(int reg)
2958	{
2959	#if !defined(CONFIG_USER_ONLY)
2960	switch(reg) {
2961	case 0:
2962	cpu_x86_update_cr0(env, T0);
2963	break;
2964	case 3:
2965	cpu_x86_update_cr3(env, T0);
2966	break;
2967	case 4:
2968	cpu_x86_update_cr4(env, T0);
2969	break;
2970	case 8:
2971	cpu_set_apic_tpr(env, T0);
2972	break;
2973	default:
2974	env->cr[reg] = T0;
2975	break;
2976	}
2977	#endif
2978	}
2979
2980	/* XXX: do more */
2981	void helper_movl_drN_T0(int reg)
2982	{
2983	env->dr[reg] = T0;
2984	}
2985
2986	void helper_invlpg(target_ulong addr)
2987	{
2988	cpu_x86_flush_tlb(env, addr);
2989	}
2990
2991	void helper_rdtsc(void)
2992	{
2993	uint64_t val;
2994
2995	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2996	raise_exception(EXCP0D_GPF);
2997	}
2998	val = cpu_get_tsc(env);
2999	EAX = (uint32_t)(val);
3000	EDX = (uint32_t)(val >> 32);
3001	}
3002
3003	#if defined(CONFIG_USER_ONLY)
3004	void helper_wrmsr(void)
3005	{
3006	}
3007
3008	void helper_rdmsr(void)
3009	{
3010	}
3011	#else
3012	void helper_wrmsr(void)
3013	{
3014	uint64_t val;
3015
3016	val = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
3017
3018	switch((uint32_t)ECX) {
3019	case MSR_IA32_SYSENTER_CS:
3020	env->sysenter_cs = val & 0xffff;
3021	break;
3022	case MSR_IA32_SYSENTER_ESP:
3023	env->sysenter_esp = val;
3024	break;
3025	case MSR_IA32_SYSENTER_EIP:
3026	env->sysenter_eip = val;
3027	break;
3028	case MSR_IA32_APICBASE:
3029	cpu_set_apic_base(env, val);
3030	break;
3031	case MSR_EFER:
3032	{
3033	uint64_t update_mask;
3034	update_mask = 0;
3035	if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
3036	update_mask \|= MSR_EFER_SCE;
3037	if (env->cpuid_ext2_features & CPUID_EXT2_LM)
3038	update_mask \|= MSR_EFER_LME;
3039	if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
3040	update_mask \|= MSR_EFER_FFXSR;
3041	if (env->cpuid_ext2_features & CPUID_EXT2_NX)
3042	update_mask \|= MSR_EFER_NXE;
3043	env->efer = (env->efer & ~update_mask) \|
3044	(val & update_mask);
3045	}
3046	break;
3047	case MSR_STAR:
3048	env->star = val;
3049	break;
3050	case MSR_PAT:
3051	env->pat = val;
3052	break;
3053	#ifdef TARGET_X86_64
3054	case MSR_LSTAR:
3055	env->lstar = val;
3056	break;
3057	case MSR_CSTAR:
3058	env->cstar = val;
3059	break;
3060	case MSR_FMASK:
3061	env->fmask = val;
3062	break;
3063	case MSR_FSBASE:
3064	env->segs[R_FS].base = val;
3065	break;
3066	case MSR_GSBASE:
3067	env->segs[R_GS].base = val;
3068	break;
3069	case MSR_KERNELGSBASE:
3070	env->kernelgsbase = val;
3071	break;
3072	#endif
3073	default:
3074	/* XXX: exception ? */
3075	break;
3076	}
3077	}
3078
3079	void helper_rdmsr(void)
3080	{
3081	uint64_t val;
3082	switch((uint32_t)ECX) {
3083	case MSR_IA32_SYSENTER_CS:
3084	val = env->sysenter_cs;
3085	break;
3086	case MSR_IA32_SYSENTER_ESP:
3087	val = env->sysenter_esp;
3088	break;
3089	case MSR_IA32_SYSENTER_EIP:
3090	val = env->sysenter_eip;
3091	break;
3092	case MSR_IA32_APICBASE:
3093	val = cpu_get_apic_base(env);
3094	break;
3095	case MSR_EFER:
3096	val = env->efer;
3097	break;
3098	case MSR_STAR:
3099	val = env->star;
3100	break;
3101	case MSR_PAT:
3102	val = env->pat;
3103	break;
3104	#ifdef TARGET_X86_64
3105	case MSR_LSTAR:
3106	val = env->lstar;
3107	break;
3108	case MSR_CSTAR:
3109	val = env->cstar;
3110	break;
3111	case MSR_FMASK:
3112	val = env->fmask;
3113	break;
3114	case MSR_FSBASE:
3115	val = env->segs[R_FS].base;
3116	break;
3117	case MSR_GSBASE:
3118	val = env->segs[R_GS].base;
3119	break;
3120	case MSR_KERNELGSBASE:
3121	val = env->kernelgsbase;
3122	break;
3123	#endif
3124	default:
3125	/* XXX: exception ? */
3126	val = 0;
3127	break;
3128	}
3129	EAX = (uint32_t)(val);
3130	EDX = (uint32_t)(val >> 32);
3131	}
3132	#endif
3133
3134	void helper_lsl(void)
3135	{
3136	unsigned int selector, limit;
3137	uint32_t e1, e2, eflags;
3138	int rpl, dpl, cpl, type;
3139
3140	eflags = cc_table[CC_OP].compute_all();
3141	selector = T0 & 0xffff;
3142	if (load_segment(&e1, &e2, selector) != 0)
3143	goto fail;
3144	rpl = selector & 3;
3145	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3146	cpl = env->hflags & HF_CPL_MASK;
3147	if (e2 & DESC_S_MASK) {
3148	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3149	/* conforming */
3150	} else {
3151	if (dpl < cpl \|\| dpl < rpl)
3152	goto fail;
3153	}
3154	} else {
3155	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3156	switch(type) {
3157	case 1:
3158	case 2:
3159	case 3:
3160	case 9:
3161	case 11:
3162	break;
3163	default:
3164	goto fail;
3165	}
3166	if (dpl < cpl \|\| dpl < rpl) {
3167	fail:
3168	CC_SRC = eflags & ~CC_Z;
3169	return;
3170	}
3171	}
3172	limit = get_seg_limit(e1, e2);
3173	T1 = limit;
3174	CC_SRC = eflags \| CC_Z;
3175	}
3176
3177	void helper_lar(void)
3178	{
3179	unsigned int selector;
3180	uint32_t e1, e2, eflags;
3181	int rpl, dpl, cpl, type;
3182
3183	eflags = cc_table[CC_OP].compute_all();
3184	selector = T0 & 0xffff;
3185	if ((selector & 0xfffc) == 0)
3186	goto fail;
3187	if (load_segment(&e1, &e2, selector) != 0)
3188	goto fail;
3189	rpl = selector & 3;
3190	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3191	cpl = env->hflags & HF_CPL_MASK;
3192	if (e2 & DESC_S_MASK) {
3193	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3194	/* conforming */
3195	} else {
3196	if (dpl < cpl \|\| dpl < rpl)
3197	goto fail;
3198	}
3199	} else {
3200	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3201	switch(type) {
3202	case 1:
3203	case 2:
3204	case 3:
3205	case 4:
3206	case 5:
3207	case 9:
3208	case 11:
3209	case 12:
3210	break;
3211	default:
3212	goto fail;
3213	}
3214	if (dpl < cpl \|\| dpl < rpl) {
3215	fail:
3216	CC_SRC = eflags & ~CC_Z;
3217	return;
3218	}
3219	}
3220	T1 = e2 & 0x00f0ff00;
3221	CC_SRC = eflags \| CC_Z;
3222	}
3223
3224	void helper_verr(void)
3225	{
3226	unsigned int selector;
3227	uint32_t e1, e2, eflags;
3228	int rpl, dpl, cpl;
3229
3230	eflags = cc_table[CC_OP].compute_all();
3231	selector = T0 & 0xffff;
3232	if ((selector & 0xfffc) == 0)
3233	goto fail;
3234	if (load_segment(&e1, &e2, selector) != 0)
3235	goto fail;
3236	if (!(e2 & DESC_S_MASK))
3237	goto fail;
3238	rpl = selector & 3;
3239	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3240	cpl = env->hflags & HF_CPL_MASK;
3241	if (e2 & DESC_CS_MASK) {
3242	if (!(e2 & DESC_R_MASK))
3243	goto fail;
3244	if (!(e2 & DESC_C_MASK)) {
3245	if (dpl < cpl \|\| dpl < rpl)
3246	goto fail;
3247	}
3248	} else {
3249	if (dpl < cpl \|\| dpl < rpl) {
3250	fail:
3251	CC_SRC = eflags & ~CC_Z;
3252	return;
3253	}
3254	}
3255	CC_SRC = eflags \| CC_Z;
3256	}
3257
3258	void helper_verw(void)
3259	{
3260	unsigned int selector;
3261	uint32_t e1, e2, eflags;
3262	int rpl, dpl, cpl;
3263
3264	eflags = cc_table[CC_OP].compute_all();
3265	selector = T0 & 0xffff;
3266	if ((selector & 0xfffc) == 0)
3267	goto fail;
3268	if (load_segment(&e1, &e2, selector) != 0)
3269	goto fail;
3270	if (!(e2 & DESC_S_MASK))
3271	goto fail;
3272	rpl = selector & 3;
3273	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3274	cpl = env->hflags & HF_CPL_MASK;
3275	if (e2 & DESC_CS_MASK) {
3276	goto fail;
3277	} else {
3278	if (dpl < cpl \|\| dpl < rpl)
3279	goto fail;
3280	if (!(e2 & DESC_W_MASK)) {
3281	fail:
3282	CC_SRC = eflags & ~CC_Z;
3283	return;
3284	}
3285	}
3286	CC_SRC = eflags \| CC_Z;
3287	}
3288
3289	/* FPU helpers */
3290
3291	void helper_fldt_ST0_A0(void)
3292	{
3293	int new_fpstt;
3294	new_fpstt = (env->fpstt - 1) & 7;
3295	env->fpregs[new_fpstt].d = helper_fldt(A0);
3296	env->fpstt = new_fpstt;
3297	env->fptags[new_fpstt] = 0; /* validate stack entry */
3298	}
3299
3300	void helper_fstt_ST0_A0(void)
3301	{
3302	helper_fstt(ST0, A0);
3303	}
3304
3305	void fpu_set_exception(int mask)
3306	{
3307	env->fpus \|= mask;
3308	if (env->fpus & (~env->fpuc & FPUC_EM))
3309	env->fpus \|= FPUS_SE \| FPUS_B;
3310	}
3311
3312	CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
3313	{
3314	if (b == 0.0)
3315	fpu_set_exception(FPUS_ZE);
3316	return a / b;
3317	}
3318
3319	void fpu_raise_exception(void)
3320	{
3321	if (env->cr[0] & CR0_NE_MASK) {
3322	raise_exception(EXCP10_COPR);
3323	}
3324	#if !defined(CONFIG_USER_ONLY)
3325	else {
3326	cpu_set_ferr(env);
3327	}
3328	#endif
3329	}
3330
3331	/* BCD ops */
3332
3333	void helper_fbld_ST0_A0(void)
3334	{
3335	CPU86_LDouble tmp;
3336	uint64_t val;
3337	unsigned int v;
3338	int i;
3339
3340	val = 0;
3341	for(i = 8; i >= 0; i--) {
3342	v = ldub(A0 + i);
3343	val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
3344	}
3345	tmp = val;
3346	if (ldub(A0 + 9) & 0x80)
3347	tmp = -tmp;
3348	fpush();
3349	ST0 = tmp;
3350	}
3351
3352	void helper_fbst_ST0_A0(void)
3353	{
3354	int v;
3355	target_ulong mem_ref, mem_end;
3356	int64_t val;
3357
3358	val = floatx_to_int64(ST0, &env->fp_status);
3359	mem_ref = A0;
3360	mem_end = mem_ref + 9;
3361	if (val < 0) {
3362	stb(mem_end, 0x80);
3363	val = -val;
3364	} else {
3365	stb(mem_end, 0x00);
3366	}
3367	while (mem_ref < mem_end) {
3368	if (val == 0)
3369	break;
3370	v = val % 100;
3371	val = val / 100;
3372	v = ((v / 10) << 4) \| (v % 10);
3373	stb(mem_ref++, v);
3374	}
3375	while (mem_ref < mem_end) {
3376	stb(mem_ref++, 0);
3377	}
3378	}
3379
3380	void helper_f2xm1(void)
3381	{
3382	ST0 = pow(2.0,ST0) - 1.0;
3383	}
3384
3385	void helper_fyl2x(void)
3386	{
3387	CPU86_LDouble fptemp;
3388
3389	fptemp = ST0;
3390	if (fptemp>0.0){
3391	fptemp = log(fptemp)/log(2.0); /* log2(ST) */
3392	ST1 *= fptemp;
3393	fpop();
3394	} else {
3395	env->fpus &= (~0x4700);
3396	env->fpus \|= 0x400;
3397	}
3398	}
3399
3400	void helper_fptan(void)
3401	{
3402	CPU86_LDouble fptemp;
3403
3404	fptemp = ST0;
3405	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3406	env->fpus \|= 0x400;
3407	} else {
3408	ST0 = tan(fptemp);
3409	fpush();
3410	ST0 = 1.0;
3411	env->fpus &= (~0x400); /* C2 <-- 0 */
3412	/* the above code is for \|arg\| < 2*52 only /
3413	}
3414	}
3415
3416	void helper_fpatan(void)
3417	{
3418	CPU86_LDouble fptemp, fpsrcop;
3419
3420	fpsrcop = ST1;
3421	fptemp = ST0;
3422	ST1 = atan2(fpsrcop,fptemp);
3423	fpop();
3424	}
3425
3426	void helper_fxtract(void)
3427	{
3428	CPU86_LDoubleU temp;
3429	unsigned int expdif;
3430
3431	temp.d = ST0;
3432	expdif = EXPD(temp) - EXPBIAS;
3433	/DP exponent bias/
3434	ST0 = expdif;
3435	fpush();
3436	BIASEXPONENT(temp);
3437	ST0 = temp.d;
3438	}
3439
3440	void helper_fprem1(void)
3441	{
3442	CPU86_LDouble dblq, fpsrcop, fptemp;
3443	CPU86_LDoubleU fpsrcop1, fptemp1;
3444	int expdif;
3445	int q;
3446
3447	fpsrcop = ST0;
3448	fptemp = ST1;
3449	fpsrcop1.d = fpsrcop;
3450	fptemp1.d = fptemp;
3451	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3452	if (expdif < 53) {
3453	dblq = fpsrcop / fptemp;
3454	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3455	ST0 = fpsrcop - fptemp*dblq;
3456	q = (int)dblq; /* cutting off top bits is assumed here */
3457	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3458	/* (C0,C1,C3) <-- (q2,q1,q0) */
3459	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3460	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3461	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3462	} else {
3463	env->fpus \|= 0x400; /* C2 <-- 1 */
3464	fptemp = pow(2.0, expdif-50);
3465	fpsrcop = (ST0 / ST1) / fptemp;
3466	/* fpsrcop = integer obtained by rounding to the nearest */
3467	fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3468	floor(fpsrcop): ceil(fpsrcop);
3469	ST0 -= (ST1 * fpsrcop * fptemp);
3470	}
3471	}
3472
3473	void helper_fprem(void)
3474	{
3475	CPU86_LDouble dblq, fpsrcop, fptemp;
3476	CPU86_LDoubleU fpsrcop1, fptemp1;
3477	int expdif;
3478	int q;
3479
3480	fpsrcop = ST0;
3481	fptemp = ST1;
3482	fpsrcop1.d = fpsrcop;
3483	fptemp1.d = fptemp;
3484	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3485	if ( expdif < 53 ) {
3486	dblq = fpsrcop / fptemp;
3487	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3488	ST0 = fpsrcop - fptemp*dblq;
3489	q = (int)dblq; /* cutting off top bits is assumed here */
3490	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3491	/* (C0,C1,C3) <-- (q2,q1,q0) */
3492	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3493	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3494	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3495	} else {
3496	env->fpus \|= 0x400; /* C2 <-- 1 */
3497	fptemp = pow(2.0, expdif-50);
3498	fpsrcop = (ST0 / ST1) / fptemp;
3499	/* fpsrcop = integer obtained by chopping */
3500	fpsrcop = (fpsrcop < 0.0)?
3501	-(floor(fabs(fpsrcop))): floor(fpsrcop);
3502	ST0 -= (ST1 * fpsrcop * fptemp);
3503	}
3504	}
3505
3506	void helper_fyl2xp1(void)
3507	{
3508	CPU86_LDouble fptemp;
3509
3510	fptemp = ST0;
3511	if ((fptemp+1.0)>0.0) {
3512	fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3513	ST1 *= fptemp;
3514	fpop();
3515	} else {
3516	env->fpus &= (~0x4700);
3517	env->fpus \|= 0x400;
3518	}
3519	}
3520
3521	void helper_fsqrt(void)
3522	{
3523	CPU86_LDouble fptemp;
3524
3525	fptemp = ST0;
3526	if (fptemp<0.0) {
3527	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3528	env->fpus \|= 0x400;
3529	}
3530	ST0 = sqrt(fptemp);
3531	}
3532
3533	void helper_fsincos(void)
3534	{
3535	CPU86_LDouble fptemp;
3536
3537	fptemp = ST0;
3538	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3539	env->fpus \|= 0x400;
3540	} else {
3541	ST0 = sin(fptemp);
3542	fpush();
3543	ST0 = cos(fptemp);
3544	env->fpus &= (~0x400); /* C2 <-- 0 */
3545	/* the above code is for \|arg\| < 2*63 only /
3546	}
3547	}
3548
3549	void helper_frndint(void)
3550	{
3551	ST0 = floatx_round_to_int(ST0, &env->fp_status);
3552	}
3553
3554	void helper_fscale(void)
3555	{
3556	ST0 = ldexp (ST0, (int)(ST1));
3557	}
3558
3559	void helper_fsin(void)
3560	{
3561	CPU86_LDouble fptemp;
3562
3563	fptemp = ST0;
3564	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3565	env->fpus \|= 0x400;
3566	} else {
3567	ST0 = sin(fptemp);
3568	env->fpus &= (~0x400); /* C2 <-- 0 */
3569	/* the above code is for \|arg\| < 2*53 only /
3570	}
3571	}
3572
3573	void helper_fcos(void)
3574	{
3575	CPU86_LDouble fptemp;
3576
3577	fptemp = ST0;
3578	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3579	env->fpus \|= 0x400;
3580	} else {
3581	ST0 = cos(fptemp);
3582	env->fpus &= (~0x400); /* C2 <-- 0 */
3583	/* the above code is for \|arg5 < 2*63 only /
3584	}
3585	}
3586
3587	void helper_fxam_ST0(void)
3588	{
3589	CPU86_LDoubleU temp;
3590	int expdif;
3591
3592	temp.d = ST0;
3593
3594	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3595	if (SIGND(temp))
3596	env->fpus \|= 0x200; /* C1 <-- 1 */
3597
3598	/* XXX: test fptags too */
3599	expdif = EXPD(temp);
3600	if (expdif == MAXEXPD) {
3601	#ifdef USE_X86LDOUBLE
3602	if (MANTD(temp) == 0x8000000000000000ULL)
3603	#else
3604	if (MANTD(temp) == 0)
3605	#endif
3606	env->fpus \|= 0x500 /Infinity/;
3607	else
3608	env->fpus \|= 0x100 /NaN/;
3609	} else if (expdif == 0) {
3610	if (MANTD(temp) == 0)
3611	env->fpus \|= 0x4000 /Zero/;
3612	else
3613	env->fpus \|= 0x4400 /Denormal/;
3614	} else {
3615	env->fpus \|= 0x400;
3616	}
3617	}
3618
3619	void helper_fstenv(target_ulong ptr, int data32)
3620	{
3621	int fpus, fptag, exp, i;
3622	uint64_t mant;
3623	CPU86_LDoubleU tmp;
3624
3625	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3626	fptag = 0;
3627	for (i=7; i>=0; i--) {
3628	fptag <<= 2;
3629	if (env->fptags[i]) {
3630	fptag \|= 3;
3631	} else {
3632	tmp.d = env->fpregs[i].d;
3633	exp = EXPD(tmp);
3634	mant = MANTD(tmp);
3635	if (exp == 0 && mant == 0) {
3636	/* zero */
3637	fptag \|= 1;
3638	} else if (exp == 0 \|\| exp == MAXEXPD
3639	#ifdef USE_X86LDOUBLE
3640	\|\| (mant & (1LL << 63)) == 0
3641	#endif
3642	) {
3643	/* NaNs, infinity, denormal */
3644	fptag \|= 2;
3645	}
3646	}
3647	}
3648	if (data32) {
3649	/* 32 bit */
3650	stl(ptr, env->fpuc);
3651	stl(ptr + 4, fpus);
3652	stl(ptr + 8, fptag);
3653	stl(ptr + 12, 0); /* fpip */
3654	stl(ptr + 16, 0); /* fpcs */
3655	stl(ptr + 20, 0); /* fpoo */
3656	stl(ptr + 24, 0); /* fpos */
3657	} else {
3658	/* 16 bit */
3659	stw(ptr, env->fpuc);
3660	stw(ptr + 2, fpus);
3661	stw(ptr + 4, fptag);
3662	stw(ptr + 6, 0);
3663	stw(ptr + 8, 0);
3664	stw(ptr + 10, 0);
3665	stw(ptr + 12, 0);
3666	}
3667	}
3668
3669	void helper_fldenv(target_ulong ptr, int data32)
3670	{
3671	int i, fpus, fptag;
3672
3673	if (data32) {
3674	env->fpuc = lduw(ptr);
3675	fpus = lduw(ptr + 4);
3676	fptag = lduw(ptr + 8);
3677	}
3678	else {
3679	env->fpuc = lduw(ptr);
3680	fpus = lduw(ptr + 2);
3681	fptag = lduw(ptr + 4);
3682	}
3683	env->fpstt = (fpus >> 11) & 7;
3684	env->fpus = fpus & ~0x3800;
3685	for(i = 0;i < 8; i++) {
3686	env->fptags[i] = ((fptag & 3) == 3);
3687	fptag >>= 2;
3688	}
3689	}
3690
3691	void helper_fsave(target_ulong ptr, int data32)
3692	{
3693	CPU86_LDouble tmp;
3694	int i;
3695
3696	helper_fstenv(ptr, data32);
3697
3698	ptr += (14 << data32);
3699	for(i = 0;i < 8; i++) {
3700	tmp = ST(i);
3701	helper_fstt(tmp, ptr);
3702	ptr += 10;
3703	}
3704
3705	/* fninit */
3706	env->fpus = 0;
3707	env->fpstt = 0;
3708	env->fpuc = 0x37f;
3709	env->fptags[0] = 1;
3710	env->fptags[1] = 1;
3711	env->fptags[2] = 1;
3712	env->fptags[3] = 1;
3713	env->fptags[4] = 1;
3714	env->fptags[5] = 1;
3715	env->fptags[6] = 1;
3716	env->fptags[7] = 1;
3717	}
3718
3719	void helper_frstor(target_ulong ptr, int data32)
3720	{
3721	CPU86_LDouble tmp;
3722	int i;
3723
3724	helper_fldenv(ptr, data32);
3725	ptr += (14 << data32);
3726
3727	for(i = 0;i < 8; i++) {
3728	tmp = helper_fldt(ptr);
3729	ST(i) = tmp;
3730	ptr += 10;
3731	}
3732	}
3733
3734	void helper_fxsave(target_ulong ptr, int data64)
3735	{
3736	int fpus, fptag, i, nb_xmm_regs;
3737	CPU86_LDouble tmp;
3738	target_ulong addr;
3739
3740	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3741	fptag = 0;
3742	for(i = 0; i < 8; i++) {
3743	fptag \|= (env->fptags[i] << i);
3744	}
3745	stw(ptr, env->fpuc);
3746	stw(ptr + 2, fpus);
3747	stw(ptr + 4, fptag ^ 0xff);
3748
3749	addr = ptr + 0x20;
3750	for(i = 0;i < 8; i++) {
3751	tmp = ST(i);
3752	helper_fstt(tmp, addr);
3753	addr += 16;
3754	}
3755
3756	if (env->cr[4] & CR4_OSFXSR_MASK) {
3757	/* XXX: finish it */
3758	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3759	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3760	nb_xmm_regs = 8 << data64;
3761	addr = ptr + 0xa0;
3762	for(i = 0; i < nb_xmm_regs; i++) {
3763	stq(addr, env->xmm_regs[i].XMM_Q(0));
3764	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3765	addr += 16;
3766	}
3767	}
3768	}
3769
3770	void helper_fxrstor(target_ulong ptr, int data64)
3771	{
3772	int i, fpus, fptag, nb_xmm_regs;
3773	CPU86_LDouble tmp;
3774	target_ulong addr;
3775
3776	env->fpuc = lduw(ptr);
3777	fpus = lduw(ptr + 2);
3778	fptag = lduw(ptr + 4);
3779	env->fpstt = (fpus >> 11) & 7;
3780	env->fpus = fpus & ~0x3800;
3781	fptag ^= 0xff;
3782	for(i = 0;i < 8; i++) {
3783	env->fptags[i] = ((fptag >> i) & 1);
3784	}
3785
3786	addr = ptr + 0x20;
3787	for(i = 0;i < 8; i++) {
3788	tmp = helper_fldt(addr);
3789	ST(i) = tmp;
3790	addr += 16;
3791	}
3792
3793	if (env->cr[4] & CR4_OSFXSR_MASK) {
3794	/* XXX: finish it */
3795	env->mxcsr = ldl(ptr + 0x18);
3796	//ldl(ptr + 0x1c);
3797	nb_xmm_regs = 8 << data64;
3798	addr = ptr + 0xa0;
3799	for(i = 0; i < nb_xmm_regs; i++) {
3800	#if !defined(VBOX) \|\| __GNUC__ < 4
3801	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3802	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3803	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
3804	# if 1
3805	env->xmm_regs[i].XMM_L(0) = ldl(addr);
3806	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
3807	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
3808	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
3809	# else
3810	/* this works fine on Mac OS X, gcc 4.0.1 */
3811	uint64_t u64 = ldq(addr);
3812	env->xmm_regs[i].XMM_Q(0);
3813	u64 = ldq(addr + 4);
3814	env->xmm_regs[i].XMM_Q(1) = u64;
3815	# endif
3816	#endif
3817	addr += 16;
3818	}
3819	}
3820	}
3821
3822	#ifndef USE_X86LDOUBLE
3823
3824	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3825	{
3826	CPU86_LDoubleU temp;
3827	int e;
3828
3829	temp.d = f;
3830	/* mantissa */
3831	*pmant = (MANTD(temp) << 11) \| (1LL << 63);
3832	/* exponent + sign */
3833	e = EXPD(temp) - EXPBIAS + 16383;
3834	e \|= SIGND(temp) >> 16;
3835	*pexp = e;
3836	}
3837
3838	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3839	{
3840	CPU86_LDoubleU temp;
3841	int e;
3842	uint64_t ll;
3843
3844	/* XXX: handle overflow ? */
3845	e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3846	e \|= (upper >> 4) & 0x800; /* sign */
3847	ll = (mant >> 11) & ((1LL << 52) - 1);
3848	#ifdef __arm__
3849	temp.l.upper = (e << 20) \| (ll >> 32);
3850	temp.l.lower = ll;
3851	#else
3852	temp.ll = ll \| ((uint64_t)e << 52);
3853	#endif
3854	return temp.d;
3855	}
3856
3857	#else
3858
3859	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3860	{
3861	CPU86_LDoubleU temp;
3862
3863	temp.d = f;
3864	*pmant = temp.l.lower;
3865	*pexp = temp.l.upper;
3866	}
3867
3868	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3869	{
3870	CPU86_LDoubleU temp;
3871
3872	temp.l.upper = upper;
3873	temp.l.lower = mant;
3874	return temp.d;
3875	}
3876	#endif
3877
3878	#ifdef TARGET_X86_64
3879
3880	//#define DEBUG_MULDIV
3881
3882	static void add128(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3883	{
3884	*plow += a;
3885	/* carry test */
3886	if (*plow < a)
3887	(*phigh)++;
3888	*phigh += b;
3889	}
3890
3891	static void neg128(uint64_t plow, uint64_t phigh)
3892	{
3893	plow = ~ plow;
3894	phigh = ~ phigh;
3895	add128(plow, phigh, 1, 0);
3896	}
3897
3898	static void mul64(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3899	{
3900	uint32_t a0, a1, b0, b1;
3901	uint64_t v;
3902
3903	a0 = a;
3904	a1 = a >> 32;
3905
3906	b0 = b;
3907	b1 = b >> 32;
3908
3909	v = (uint64_t)a0 * (uint64_t)b0;
3910	*plow = v;
3911	*phigh = 0;
3912
3913	v = (uint64_t)a0 * (uint64_t)b1;
3914	add128(plow, phigh, v << 32, v >> 32);
3915
3916	v = (uint64_t)a1 * (uint64_t)b0;
3917	add128(plow, phigh, v << 32, v >> 32);
3918
3919	v = (uint64_t)a1 * (uint64_t)b1;
3920	*phigh += v;
3921	#ifdef DEBUG_MULDIV
3922	printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
3923	a, b, phigh, plow);
3924	#endif
3925	}
3926
3927	static void imul64(uint64_t plow, uint64_t phigh, int64_t a, int64_t b)
3928	{
3929	int sa, sb;
3930	sa = (a < 0);
3931	if (sa)
3932	a = -a;
3933	sb = (b < 0);
3934	if (sb)
3935	b = -b;
3936	mul64(plow, phigh, a, b);
3937	if (sa ^ sb) {
3938	neg128(plow, phigh);
3939	}
3940	}
3941
3942	/* return TRUE if overflow */
3943	static int div64(uint64_t plow, uint64_t phigh, uint64_t b)
3944	{
3945	uint64_t q, r, a1, a0;
3946	int i, qb, ab;
3947
3948	a0 = *plow;
3949	a1 = *phigh;
3950	if (a1 == 0) {
3951	q = a0 / b;
3952	r = a0 % b;
3953	*plow = q;
3954	*phigh = r;
3955	} else {
3956	if (a1 >= b)
3957	return 1;
3958	/* XXX: use a better algorithm */
3959	for(i = 0; i < 64; i++) {
3960	ab = a1 >> 63;
3961	a1 = (a1 << 1) \| (a0 >> 63);
3962	if (ab \|\| a1 >= b) {
3963	a1 -= b;
3964	qb = 1;
3965	} else {
3966	qb = 0;
3967	}
3968	a0 = (a0 << 1) \| qb;
3969	}
3970	#if defined(DEBUG_MULDIV)
3971	printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
3972	phigh, plow, b, a0, a1);
3973	#endif
3974	*plow = a0;
3975	*phigh = a1;
3976	}
3977	return 0;
3978	}
3979
3980	/* return TRUE if overflow */
3981	static int idiv64(uint64_t plow, uint64_t phigh, int64_t b)
3982	{
3983	int sa, sb;
3984	sa = ((int64_t)*phigh < 0);
3985	if (sa)
3986	neg128(plow, phigh);
3987	sb = (b < 0);
3988	if (sb)
3989	b = -b;
3990	if (div64(plow, phigh, b) != 0)
3991	return 1;
3992	if (sa ^ sb) {
3993	if (*plow > (1ULL << 63))
3994	return 1;
3995	plow = - plow;
3996	} else {
3997	if (*plow >= (1ULL << 63))
3998	return 1;
3999	}
4000	if (sa)
4001	phigh = - phigh;
4002	return 0;
4003	}
4004
4005	void helper_mulq_EAX_T0(void)
4006	{
4007	uint64_t r0, r1;
4008
4009	mul64(&r0, &r1, EAX, T0);
4010	EAX = r0;
4011	EDX = r1;
4012	CC_DST = r0;
4013	CC_SRC = r1;
4014	}
4015
4016	void helper_imulq_EAX_T0(void)
4017	{
4018	uint64_t r0, r1;
4019
4020	imul64(&r0, &r1, EAX, T0);
4021	EAX = r0;
4022	EDX = r1;
4023	CC_DST = r0;
4024	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4025	}
4026
4027	void helper_imulq_T0_T1(void)
4028	{
4029	uint64_t r0, r1;
4030
4031	imul64(&r0, &r1, T0, T1);
4032	T0 = r0;
4033	CC_DST = r0;
4034	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4035	}
4036
4037	void helper_divq_EAX_T0(void)
4038	{
4039	uint64_t r0, r1;
4040	if (T0 == 0) {
4041	raise_exception(EXCP00_DIVZ);
4042	}
4043	r0 = EAX;
4044	r1 = EDX;
4045	if (div64(&r0, &r1, T0))
4046	raise_exception(EXCP00_DIVZ);
4047	EAX = r0;
4048	EDX = r1;
4049	}
4050
4051	void helper_idivq_EAX_T0(void)
4052	{
4053	uint64_t r0, r1;
4054	if (T0 == 0) {
4055	raise_exception(EXCP00_DIVZ);
4056	}
4057	r0 = EAX;
4058	r1 = EDX;
4059	if (idiv64(&r0, &r1, T0))
4060	raise_exception(EXCP00_DIVZ);
4061	EAX = r0;
4062	EDX = r1;
4063	}
4064
4065	void helper_bswapq_T0(void)
4066	{
4067	T0 = bswap64(T0);
4068	}
4069	#endif
4070
4071	void helper_hlt(void)
4072	{
4073	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
4074	env->hflags \|= HF_HALTED_MASK;
4075	env->exception_index = EXCP_HLT;
4076	cpu_loop_exit();
4077	}
4078
4079	void helper_monitor(void)
4080	{
4081	if ((uint32_t)ECX != 0)
4082	raise_exception(EXCP0D_GPF);
4083	/* XXX: store address ? */
4084	}
4085
4086	void helper_mwait(void)
4087	{
4088	if ((uint32_t)ECX != 0)
4089	raise_exception(EXCP0D_GPF);
4090	#ifdef VBOX
4091	helper_hlt();
4092	#else
4093	/* XXX: not complete but not completely erroneous */
4094	if (env->cpu_index != 0 \|\| env->next_cpu != NULL) {
4095	/* more than one CPU: do not sleep because another CPU may
4096	wake this one */
4097	} else {
4098	helper_hlt();
4099	}
4100	#endif
4101	}
4102
4103	float approx_rsqrt(float a)
4104	{
4105	return 1.0 / sqrt(a);
4106	}
4107
4108	float approx_rcp(float a)
4109	{
4110	return 1.0 / a;
4111	}
4112
4113	void update_fp_status(void)
4114	{
4115	int rnd_type;
4116
4117	/* set rounding mode */
4118	switch(env->fpuc & RC_MASK) {
4119	default:
4120	case RC_NEAR:
4121	rnd_type = float_round_nearest_even;
4122	break;
4123	case RC_DOWN:
4124	rnd_type = float_round_down;
4125	break;
4126	case RC_UP:
4127	rnd_type = float_round_up;
4128	break;
4129	case RC_CHOP:
4130	rnd_type = float_round_to_zero;
4131	break;
4132	}
4133	set_float_rounding_mode(rnd_type, &env->fp_status);
4134	#ifdef FLOATX80
4135	switch((env->fpuc >> 8) & 3) {
4136	case 0:
4137	rnd_type = 32;
4138	break;
4139	case 2:
4140	rnd_type = 64;
4141	break;
4142	case 3:
4143	default:
4144	rnd_type = 80;
4145	break;
4146	}
4147	set_floatx80_rounding_precision(rnd_type, &env->fp_status);
4148	#endif
4149	}
4150
4151	#if !defined(CONFIG_USER_ONLY)
4152
4153	#define MMUSUFFIX _mmu
4154	#define GETPC() (__builtin_return_address(0))
4155
4156	#define SHIFT 0
4157	#include "softmmu_template.h"
4158
4159	#define SHIFT 1
4160	#include "softmmu_template.h"
4161
4162	#define SHIFT 2
4163	#include "softmmu_template.h"
4164
4165	#define SHIFT 3
4166	#include "softmmu_template.h"
4167
4168	#endif
4169
4170	/* try to fill the TLB and return an exception if error. If retaddr is
4171	NULL, it means that the function was called in C code (i.e. not
4172	from generated code or from helper.c) */
4173	/* XXX: fix it to restore all registers */
4174	void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
4175	{
4176	TranslationBlock *tb;
4177	int ret;
4178	unsigned long pc;
4179	CPUX86State *saved_env;
4180
4181	/* XXX: hack to restore env in all cases, even if not called from
4182	generated code */
4183	saved_env = env;
4184	env = cpu_single_env;
4185
4186	ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
4187	if (ret) {
4188	if (retaddr) {
4189	/* now we have a real cpu fault */
4190	pc = (unsigned long)retaddr;
4191	tb = tb_find_pc(pc);
4192	if (tb) {
4193	/* the PC is inside the translated code. It means that we have
4194	a virtual CPU fault */
4195	cpu_restore_state(tb, env, pc, NULL);
4196	}
4197	}
4198	if (retaddr)
4199	raise_exception_err(env->exception_index, env->error_code);
4200	else
4201	raise_exception_err_norestore(env->exception_index, env->error_code);
4202	}
4203	env = saved_env;
4204	}
4205
4206	#ifdef VBOX
4207
4208	/**
4209	* Correctly computes the eflags.
4210	* @returns eflags.
4211	* @param env1 CPU environment.
4212	*/
4213	uint32_t raw_compute_eflags(CPUX86State *env1)
4214	{
4215	CPUX86State *savedenv = env;
4216	env = env1;
4217	uint32_t efl = compute_eflags();
4218	env = savedenv;
4219	return efl;
4220	}
4221
4222	/**
4223	* Reads byte from virtual address in guest memory area.
4224	* XXX: is it working for any addresses? swapped out pages?
4225	* @returns readed data byte.
4226	* @param env1 CPU environment.
4227	* @param pvAddr GC Virtual address.
4228	*/
4229	uint8_t read_byte(CPUX86State *env1, target_ulong addr)
4230	{
4231	CPUX86State *savedenv = env;
4232	env = env1;
4233	uint8_t u8 = ldub_kernel(addr);
4234	env = savedenv;
4235	return u8;
4236	}
4237
4238	/**
4239	* Reads byte from virtual address in guest memory area.
4240	* XXX: is it working for any addresses? swapped out pages?
4241	* @returns readed data byte.
4242	* @param env1 CPU environment.
4243	* @param pvAddr GC Virtual address.
4244	*/
4245	uint16_t read_word(CPUX86State *env1, target_ulong addr)
4246	{
4247	CPUX86State *savedenv = env;
4248	env = env1;
4249	uint16_t u16 = lduw_kernel(addr);
4250	env = savedenv;
4251	return u16;
4252	}
4253
4254	/**
4255	* Reads byte from virtual address in guest memory area.
4256	* XXX: is it working for any addresses? swapped out pages?
4257	* @returns readed data byte.
4258	* @param env1 CPU environment.
4259	* @param pvAddr GC Virtual address.
4260	*/
4261	uint32_t read_dword(CPUX86State *env1, target_ulong addr)
4262	{
4263	CPUX86State *savedenv = env;
4264	env = env1;
4265	uint32_t u32 = ldl_kernel(addr);
4266	env = savedenv;
4267	return u32;
4268	}
4269
4270	/**
4271	* Writes byte to virtual address in guest memory area.
4272	* XXX: is it working for any addresses? swapped out pages?
4273	* @returns readed data byte.
4274	* @param env1 CPU environment.
4275	* @param pvAddr GC Virtual address.
4276	* @param val byte value
4277	*/
4278	void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val)
4279	{
4280	CPUX86State *savedenv = env;
4281	env = env1;
4282	stb(addr, val);
4283	env = savedenv;
4284	}
4285
4286	void write_word(CPUX86State *env1, target_ulong addr, uint16_t val)
4287	{
4288	CPUX86State *savedenv = env;
4289	env = env1;
4290	stw(addr, val);
4291	env = savedenv;
4292	}
4293
4294	void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val)
4295	{
4296	CPUX86State *savedenv = env;
4297	env = env1;
4298	stl(addr, val);
4299	env = savedenv;
4300	}
4301
4302	/**
4303	* Correctly loads selector into segment register with updating internal
4304	* qemu data/caches.
4305	* @param env1 CPU environment.
4306	* @param seg_reg Segment register.
4307	* @param selector Selector to load.
4308	*/
4309	void sync_seg(CPUX86State *env1, int seg_reg, int selector)
4310	{
4311	CPUX86State *savedenv = env;
4312	env = env1;
4313
4314	if ( env->eflags & X86_EFL_VM
4315	\|\| !(env->cr[0] & X86_CR0_PE))
4316	{
4317	load_seg_vm(seg_reg, selector);
4318
4319	env = savedenv;
4320
4321	/* Successful sync. */
4322	env1->segs[seg_reg].newselector = 0;
4323	}
4324	else
4325	{
4326	if (setjmp(env1->jmp_env) == 0)
4327	{
4328	if (seg_reg == R_CS)
4329	{
4330	uint32_t e1, e2;
4331	load_segment(&e1, &e2, selector);
4332	cpu_x86_load_seg_cache(env, R_CS, selector,
4333	get_seg_base(e1, e2),
4334	get_seg_limit(e1, e2),
4335	e2);
4336	}
4337	else
4338	load_seg(seg_reg, selector);
4339	env = savedenv;
4340
4341	/* Successful sync. */
4342	env1->segs[seg_reg].newselector = 0;
4343	}
4344	else
4345	{
4346	env = savedenv;
4347
4348	/* Postpone sync until the guest uses the selector. */
4349	env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
4350	env1->segs[seg_reg].newselector = selector;
4351	Log(("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector));
4352	}
4353	}
4354
4355	}
4356
4357
4358	/**
4359	* Correctly loads a new ldtr selector.
4360	*
4361	* @param env1 CPU environment.
4362	* @param selector Selector to load.
4363	*/
4364	void sync_ldtr(CPUX86State *env1, int selector)
4365	{
4366	CPUX86State *saved_env = env;
4367	target_ulong saved_T0 = T0;
4368	if (setjmp(env1->jmp_env) == 0)
4369	{
4370	env = env1;
4371	T0 = selector;
4372	helper_lldt_T0();
4373	T0 = saved_T0;
4374	env = saved_env;
4375	}
4376	else
4377	{
4378	T0 = saved_T0;
4379	env = saved_env;
4380	#ifdef VBOX_STRICT
4381	cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
4382	#endif
4383	}
4384	}
4385
4386	/**
4387	* Correctly loads a new tr selector.
4388	*
4389	* @param env1 CPU environment.
4390	* @param selector Selector to load.
4391	*/
4392	int sync_tr(CPUX86State *env1, int selector)
4393	{
4394	/* ARG! this was going to call helper_ltr_T0 but that won't work because of busy flag. */
4395	SegmentCache *dt;
4396	uint32_t e1, e2;
4397	int index, type, entry_limit;
4398	target_ulong ptr;
4399	CPUX86State *saved_env = env;
4400	env = env1;
4401
4402	selector &= 0xffff;
4403	if ((selector & 0xfffc) == 0) {
4404	/* NULL selector case: invalid TR */
4405	env->tr.base = 0;
4406	env->tr.limit = 0;
4407	env->tr.flags = 0;
4408	} else {
4409	if (selector & 0x4)
4410	goto l_failure;
4411	dt = &env->gdt;
4412	index = selector & ~7;
4413	#ifdef TARGET_X86_64
4414	if (env->hflags & HF_LMA_MASK)
4415	entry_limit = 15;
4416	else
4417	#endif
4418	entry_limit = 7;
4419	if ((index + entry_limit) > dt->limit)
4420	goto l_failure;
4421	ptr = dt->base + index;
4422	e1 = ldl_kernel(ptr);
4423	e2 = ldl_kernel(ptr + 4);
4424	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
4425	if ((e2 & DESC_S_MASK) /*\|\|
4426	(type != 1 && type != 9)*/)
4427	goto l_failure;
4428	if (!(e2 & DESC_P_MASK))
4429	goto l_failure;
4430	#ifdef TARGET_X86_64
4431	if (env->hflags & HF_LMA_MASK) {
4432	uint32_t e3;
4433	e3 = ldl_kernel(ptr + 8);
4434	load_seg_cache_raw_dt(&env->tr, e1, e2);
4435	env->tr.base \|= (target_ulong)e3 << 32;
4436	} else
4437	#endif
4438	{
4439	load_seg_cache_raw_dt(&env->tr, e1, e2);
4440	}
4441	e2 \|= DESC_TSS_BUSY_MASK;
4442	stl_kernel(ptr + 4, e2);
4443	}
4444	env->tr.selector = selector;
4445
4446	env = saved_env;
4447	return 0;
4448	l_failure:
4449	AssertMsgFailed(("selector=%d\n", selector));
4450	return -1;
4451	}
4452
4453	int emulate_single_instr(CPUX86State *env1)
4454	{
4455	#if 1 /* single stepping is broken when using a static tb... feel free to figure out why. :-) */
4456	/* This has to be static because it needs to be addressible
4457	using 32-bit immediate addresses on 64-bit machines. This
4458	is dictated by the gcc code model used when building this
4459	module / op.o. Using a static here pushes the problem
4460	onto the module loader. */
4461	static TranslationBlock tb_temp;
4462	#endif
4463	TranslationBlock *tb;
4464	TranslationBlock *current;
4465	int csize;
4466	void (*gen_func)(void);
4467	uint8_t *tc_ptr;
4468	target_ulong old_eip;
4469
4470	/* ensures env is loaded in ebp! */
4471	CPUX86State *savedenv = env;
4472	env = env1;
4473
4474	RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
4475
4476	#if 1 /* see above */
4477	tc_ptr = env->pvCodeBuffer;
4478	#else
4479	tc_ptr = code_gen_ptr;
4480	#endif
4481
4482	/*
4483	* Setup temporary translation block.
4484	*/
4485	/* tb_alloc: */
4486	#if 1 /* see above */
4487	tb = &tb_temp;
4488	tb->pc = env->segs[R_CS].base + env->eip;
4489	tb->cflags = 0;
4490	#else
4491	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4492	if (!tb)
4493	{
4494	tb_flush(env);
4495	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4496	}
4497	#endif
4498
4499	/* tb_find_slow: */
4500	tb->tc_ptr = tc_ptr;
4501	tb->cs_base = env->segs[R_CS].base;
4502	tb->flags = env->hflags \| (env->eflags & (IOPL_MASK \| TF_MASK \| VM_MASK));
4503
4504	/* Initialize the rest with sensible values. */
4505	tb->size = 0;
4506	tb->phys_hash_next = NULL;
4507	tb->page_next[0] = NULL;
4508	tb->page_next[1] = NULL;
4509	tb->page_addr[0] = 0;
4510	tb->page_addr[1] = 0;
4511	tb->tb_next_offset[0] = 0xffff;
4512	tb->tb_next_offset[1] = 0xffff;
4513	tb->tb_next[0] = 0xffff;
4514	tb->tb_next[1] = 0xffff;
4515	tb->jmp_next[0] = NULL;
4516	tb->jmp_next[1] = NULL;
4517	tb->jmp_first = NULL;
4518
4519	current = env->current_tb;
4520	env->current_tb = NULL;
4521
4522	/*
4523	* Translate only one instruction.
4524	*/
4525	ASMAtomicOrU32(&env->state, CPU_EMULATE_SINGLE_INSTR);
4526	if (cpu_gen_code(env, tb, env->cbCodeBuffer, &csize) < 0)
4527	{
4528	AssertFailed();
4529	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4530	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4531	env = savedenv;
4532	return -1;
4533	}
4534	#ifdef DEBUG
4535	if(csize > env->cbCodeBuffer)
4536	{
4537	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4538	AssertFailed();
4539	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4540	env = savedenv;
4541	return -1;
4542	}
4543	if (tb->tc_ptr != tc_ptr)
4544	{
4545	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4546	AssertFailed();
4547	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4548	env = savedenv;
4549	return -1;
4550	}
4551	#endif
4552	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4553
4554	/* tb_link_phys: */
4555	tb->jmp_first = (TranslationBlock *)((intptr_t)tb \| 2);
4556	Assert(tb->jmp_next[0] == NULL); Assert(tb->jmp_next[1] == NULL);
4557	if (tb->tb_next_offset[0] != 0xffff)
4558	tb_set_jmp_target(tb, 0, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[0]));
4559	if (tb->tb_next_offset[1] != 0xffff)
4560	tb_set_jmp_target(tb, 1, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[1]));
4561
4562	/*
4563	* Execute it using emulation
4564	*/
4565	old_eip = env->eip;
4566	gen_func = (void *)tb->tc_ptr;
4567	env->current_tb = tb;
4568
4569	// eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
4570	// perhaps not a very safe hack
4571	while(old_eip == env->eip)
4572	{
4573	gen_func();
4574	/*
4575	* Exit once we detect an external interrupt and interrupts are enabled
4576	*/
4577	if( (env->interrupt_request & (CPU_INTERRUPT_EXTERNAL_EXIT\|CPU_INTERRUPT_EXTERNAL_TIMER)) \|\|
4578	( (env->eflags & IF_MASK) &&
4579	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
4580	(env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD) ) )
4581	{
4582	break;
4583	}
4584	}
4585	env->current_tb = current;
4586
4587	Assert(tb->phys_hash_next == NULL);
4588	Assert(tb->page_next[0] == NULL);
4589	Assert(tb->page_next[1] == NULL);
4590	Assert(tb->page_addr[0] == 0);
4591	Assert(tb->page_addr[1] == 0);
4592	/*
4593	Assert(tb->tb_next_offset[0] == 0xffff);
4594	Assert(tb->tb_next_offset[1] == 0xffff);
4595	Assert(tb->tb_next[0] == 0xffff);
4596	Assert(tb->tb_next[1] == 0xffff);
4597	Assert(tb->jmp_next[0] == NULL);
4598	Assert(tb->jmp_next[1] == NULL);
4599	Assert(tb->jmp_first == NULL); */
4600
4601	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4602
4603	/*
4604	* Execute the next instruction when we encounter instruction fusing.
4605	*/
4606	if (env->hflags & HF_INHIBIT_IRQ_MASK)
4607	{
4608	Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK) at %VGv\n", env->eip));
4609	env->hflags &= ~HF_INHIBIT_IRQ_MASK;
4610	emulate_single_instr(env);
4611	}
4612
4613	env = savedenv;
4614	return 0;
4615	}
4616
4617	int get_ss_esp_from_tss_raw(CPUX86State env1, uint32_t ss_ptr,
4618	uint32_t *esp_ptr, int dpl)
4619	{
4620	int type, index, shift;
4621
4622	CPUX86State *savedenv = env;
4623	env = env1;
4624
4625	if (!(env->tr.flags & DESC_P_MASK))
4626	cpu_abort(env, "invalid tss");
4627	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
4628	if ((type & 7) != 1)
4629	cpu_abort(env, "invalid tss type %d", type);
4630	shift = type >> 3;
4631	index = (dpl * 4 + 2) << shift;
4632	if (index + (4 << shift) - 1 > env->tr.limit)
4633	{
4634	env = savedenv;
4635	return 0;
4636	}
4637	//raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
4638
4639	if (shift == 0) {
4640	*esp_ptr = lduw_kernel(env->tr.base + index);
4641	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
4642	} else {
4643	*esp_ptr = ldl_kernel(env->tr.base + index);
4644	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
4645	}
4646
4647	env = savedenv;
4648	return 1;
4649	}
4650
4651	//*****************************************************************************
4652	// Needs to be at the bottom of the file (overriding macros)
4653
4654	static inline CPU86_LDouble helper_fldt_raw(uint8_t *ptr)
4655	{
4656	return (CPU86_LDouble )ptr;
4657	}
4658
4659	static inline void helper_fstt_raw(CPU86_LDouble f, uint8_t *ptr)
4660	{
4661	(CPU86_LDouble )ptr = f;
4662	}
4663
4664	#undef stw
4665	#undef stl
4666	#undef stq
4667	#define stw(a,b) (uint16_t )(a) = (uint16_t)(b)
4668	#define stl(a,b) (uint32_t )(a) = (uint32_t)(b)
4669	#define stq(a,b) (uint64_t )(a) = (uint64_t)(b)
4670	#define data64 0
4671
4672	//*****************************************************************************
4673	void restore_raw_fp_state(CPUX86State env, uint8_t ptr)
4674	{
4675	int fpus, fptag, i, nb_xmm_regs;
4676	CPU86_LDouble tmp;
4677	uint8_t *addr;
4678
4679	if (env->cpuid_features & CPUID_FXSR)
4680	{
4681	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4682	fptag = 0;
4683	for(i = 0; i < 8; i++) {
4684	fptag \|= (env->fptags[i] << i);
4685	}
4686	stw(ptr, env->fpuc);
4687	stw(ptr + 2, fpus);
4688	stw(ptr + 4, fptag ^ 0xff);
4689
4690	addr = ptr + 0x20;
4691	for(i = 0;i < 8; i++) {
4692	tmp = ST(i);
4693	helper_fstt_raw(tmp, addr);
4694	addr += 16;
4695	}
4696
4697	if (env->cr[4] & CR4_OSFXSR_MASK) {
4698	/* XXX: finish it */
4699	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
4700	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
4701	nb_xmm_regs = 8 << data64;
4702	addr = ptr + 0xa0;
4703	for(i = 0; i < nb_xmm_regs; i++) {
4704	#if __GNUC__ < 4
4705	stq(addr, env->xmm_regs[i].XMM_Q(0));
4706	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
4707	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
4708	stl(addr, env->xmm_regs[i].XMM_L(0));
4709	stl(addr + 4, env->xmm_regs[i].XMM_L(1));
4710	stl(addr + 8, env->xmm_regs[i].XMM_L(2));
4711	stl(addr + 12, env->xmm_regs[i].XMM_L(3));
4712	#endif
4713	addr += 16;
4714	}
4715	}
4716	}
4717	else
4718	{
4719	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4720	int fptag;
4721
4722	fp->FCW = env->fpuc;
4723	fp->FSW = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4724	fptag = 0;
4725	for (i=7; i>=0; i--) {
4726	fptag <<= 2;
4727	if (env->fptags[i]) {
4728	fptag \|= 3;
4729	} else {
4730	/* the FPU automatically computes it */
4731	}
4732	}
4733	fp->FTW = fptag;
4734
4735	for(i = 0;i < 8; i++) {
4736	tmp = ST(i);
4737	helper_fstt_raw(tmp, &fp->regs[i].reg[0]);
4738	}
4739	}
4740	}
4741
4742	//*****************************************************************************
4743	#undef lduw
4744	#undef ldl
4745	#undef ldq
4746	#define lduw(a) (uint16_t )(a)
4747	#define ldl(a) (uint32_t )(a)
4748	#define ldq(a) (uint64_t )(a)
4749	//*****************************************************************************
4750	void save_raw_fp_state(CPUX86State env, uint8_t ptr)
4751	{
4752	int i, fpus, fptag, nb_xmm_regs;
4753	CPU86_LDouble tmp;
4754	uint8_t *addr;
4755
4756	if (env->cpuid_features & CPUID_FXSR)
4757	{
4758	env->fpuc = lduw(ptr);
4759	fpus = lduw(ptr + 2);
4760	fptag = lduw(ptr + 4);
4761	env->fpstt = (fpus >> 11) & 7;
4762	env->fpus = fpus & ~0x3800;
4763	fptag ^= 0xff;
4764	for(i = 0;i < 8; i++) {
4765	env->fptags[i] = ((fptag >> i) & 1);
4766	}
4767
4768	addr = ptr + 0x20;
4769	for(i = 0;i < 8; i++) {
4770	tmp = helper_fldt_raw(addr);
4771	ST(i) = tmp;
4772	addr += 16;
4773	}
4774
4775	if (env->cr[4] & CR4_OSFXSR_MASK) {
4776	/* XXX: finish it, endianness */
4777	env->mxcsr = ldl(ptr + 0x18);
4778	//ldl(ptr + 0x1c);
4779	nb_xmm_regs = 8 << data64;
4780	addr = ptr + 0xa0;
4781	for(i = 0; i < nb_xmm_regs; i++) {
4782	#if HC_ARCH_BITS == 32
4783	/* this is a workaround for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35135 */
4784	env->xmm_regs[i].XMM_L(0) = ldl(addr);
4785	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
4786	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
4787	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
4788	#else
4789	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
4790	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
4791	#endif
4792	addr += 16;
4793	}
4794	}
4795	}
4796	else
4797	{
4798	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4799	int fptag, j;
4800
4801	env->fpuc = fp->FCW;
4802	env->fpstt = (fp->FSW >> 11) & 7;
4803	env->fpus = fp->FSW & ~0x3800;
4804	fptag = fp->FTW;
4805	for(i = 0;i < 8; i++) {
4806	env->fptags[i] = ((fptag & 3) == 3);
4807	fptag >>= 2;
4808	}
4809	j = env->fpstt;
4810	for(i = 0;i < 8; i++) {
4811	tmp = helper_fldt_raw(&fp->regs[i].reg[0]);
4812	ST(i) = tmp;
4813	}
4814	}
4815	}
4816	//*****************************************************************************
4817	//*****************************************************************************
4818
4819	#endif /* VBOX */
4820

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source: vbox/trunk/src/recompiler/target-i386/helper.c@ 12440

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