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source: vbox/trunk/src/recompiler/tcg/i386/tcg-target.c@ 37012

最後變更 在這個檔案從37012是 36175,由 vboxsync 提交於 14 年 前

rem: Synced up to v0.11.1 (35bfc7324e2e6946c4113ada5db30553a1a7c40b) from ​git://git.savannah.nongnu.org/qemu.git.
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1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#ifndef NDEBUG
26static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27 "%eax",
28 "%ecx",
29 "%edx",
30 "%ebx",
31 "%esp",
32 "%ebp",
33 "%esi",
34 "%edi",
35};
36#endif
37
38static const int tcg_target_reg_alloc_order[] = {
39 TCG_REG_EAX,
40 TCG_REG_EDX,
41 TCG_REG_ECX,
42 TCG_REG_EBX,
43 TCG_REG_ESI,
44 TCG_REG_EDI,
45 TCG_REG_EBP,
46};
47
48static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
49static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
50
51static uint8_t *tb_ret_addr;
52
53static void patch_reloc(uint8_t *code_ptr, int type,
54 tcg_target_long value, tcg_target_long addend)
55{
56 value += addend;
57 switch(type) {
58 case R_386_32:
59 *(uint32_t *)code_ptr = value;
60 break;
61 case R_386_PC32:
62 *(uint32_t *)code_ptr = value - (long)code_ptr;
63 break;
64 default:
65 tcg_abort();
66 }
67}
68
69#ifdef VBOX
70/* emits stack alignment checks for strict builds. */
71DECLINLINE(void) tcg_gen_stack_alignment_check(TCGContext *s)
72{
73# if defined(RT_STRICT) && defined(RT_OS_DARWIN) /** @todo all OSes? */
74 tcg_out8(s, 0xf7); tcg_out8(s, 0xc4); /* test %esp, 1fh */
75 tcg_out32(s, TCG_TARGET_STACK_ALIGN - 1);
76 tcg_out8(s, 0x74); /* jz imm8 */
77 tcg_out8(s, 1); /* $+3 (over int3) */
78 tcg_out8(s, 0xcc); /* int3 */
79# else
80 NOREF(s);
81# endif
82}
83#endif /* VBOX */
84
85/* maximum number of register used for input function arguments */
86static inline int tcg_target_get_call_iarg_regs_count(int flags)
87{
88 flags &= TCG_CALL_TYPE_MASK;
89 switch(flags) {
90 case TCG_CALL_TYPE_STD:
91 return 0;
92 case TCG_CALL_TYPE_REGPARM_1:
93 case TCG_CALL_TYPE_REGPARM_2:
94 case TCG_CALL_TYPE_REGPARM:
95 return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
96 default:
97 tcg_abort();
98 }
99}
100
101/* parse target specific constraints */
102static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
103{
104 const char *ct_str;
105
106 ct_str = *pct_str;
107 switch(ct_str[0]) {
108 case 'a':
109 ct->ct |= TCG_CT_REG;
110 tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
111 break;
112 case 'b':
113 ct->ct |= TCG_CT_REG;
114 tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
115 break;
116 case 'c':
117 ct->ct |= TCG_CT_REG;
118 tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
119 break;
120 case 'd':
121 ct->ct |= TCG_CT_REG;
122 tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
123 break;
124 case 'S':
125 ct->ct |= TCG_CT_REG;
126 tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
127 break;
128 case 'D':
129 ct->ct |= TCG_CT_REG;
130 tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
131 break;
132 case 'q':
133 ct->ct |= TCG_CT_REG;
134 tcg_regset_set32(ct->u.regs, 0, 0xf);
135 break;
136 case 'r':
137 ct->ct |= TCG_CT_REG;
138 tcg_regset_set32(ct->u.regs, 0, 0xff);
139 break;
140
141 /* qemu_ld/st address constraint */
142 case 'L':
143 ct->ct |= TCG_CT_REG;
144 tcg_regset_set32(ct->u.regs, 0, 0xff);
145 tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
146 tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
147 break;
148 default:
149 return -1;
150 }
151 ct_str++;
152 *pct_str = ct_str;
153 return 0;
154}
155
156/* test if a constant matches the constraint */
157static inline int tcg_target_const_match(tcg_target_long val,
158 const TCGArgConstraint *arg_ct)
159{
160 int ct;
161 ct = arg_ct->ct;
162 if (ct & TCG_CT_CONST)
163 return 1;
164 else
165 return 0;
166}
167
168#define ARITH_ADD 0
169#define ARITH_OR 1
170#define ARITH_ADC 2
171#define ARITH_SBB 3
172#define ARITH_AND 4
173#define ARITH_SUB 5
174#define ARITH_XOR 6
175#define ARITH_CMP 7
176
177#define SHIFT_ROL 0
178#define SHIFT_ROR 1
179#define SHIFT_SHL 4
180#define SHIFT_SHR 5
181#define SHIFT_SAR 7
182
183#define JCC_JMP (-1)
184#define JCC_JO 0x0
185#define JCC_JNO 0x1
186#define JCC_JB 0x2
187#define JCC_JAE 0x3
188#define JCC_JE 0x4
189#define JCC_JNE 0x5
190#define JCC_JBE 0x6
191#define JCC_JA 0x7
192#define JCC_JS 0x8
193#define JCC_JNS 0x9
194#define JCC_JP 0xa
195#define JCC_JNP 0xb
196#define JCC_JL 0xc
197#define JCC_JGE 0xd
198#define JCC_JLE 0xe
199#define JCC_JG 0xf
200
201#define P_EXT 0x100 /* 0x0f opcode prefix */
202
203static const uint8_t tcg_cond_to_jcc[10] = {
204 [TCG_COND_EQ] = JCC_JE,
205 [TCG_COND_NE] = JCC_JNE,
206 [TCG_COND_LT] = JCC_JL,
207 [TCG_COND_GE] = JCC_JGE,
208 [TCG_COND_LE] = JCC_JLE,
209 [TCG_COND_GT] = JCC_JG,
210 [TCG_COND_LTU] = JCC_JB,
211 [TCG_COND_GEU] = JCC_JAE,
212 [TCG_COND_LEU] = JCC_JBE,
213 [TCG_COND_GTU] = JCC_JA,
214};
215
216static inline void tcg_out_opc(TCGContext *s, int opc)
217{
218 if (opc & P_EXT)
219 tcg_out8(s, 0x0f);
220 tcg_out8(s, opc);
221}
222
223static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
224{
225 tcg_out_opc(s, opc);
226 tcg_out8(s, 0xc0 | (r << 3) | rm);
227}
228
229/* rm == -1 means no register index */
230static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
231 int32_t offset)
232{
233 tcg_out_opc(s, opc);
234 if (rm == -1) {
235 tcg_out8(s, 0x05 | (r << 3));
236 tcg_out32(s, offset);
237 } else if (offset == 0 && rm != TCG_REG_EBP) {
238 if (rm == TCG_REG_ESP) {
239 tcg_out8(s, 0x04 | (r << 3));
240 tcg_out8(s, 0x24);
241 } else {
242 tcg_out8(s, 0x00 | (r << 3) | rm);
243 }
244 } else if ((int8_t)offset == offset) {
245 if (rm == TCG_REG_ESP) {
246 tcg_out8(s, 0x44 | (r << 3));
247 tcg_out8(s, 0x24);
248 } else {
249 tcg_out8(s, 0x40 | (r << 3) | rm);
250 }
251 tcg_out8(s, offset);
252 } else {
253 if (rm == TCG_REG_ESP) {
254 tcg_out8(s, 0x84 | (r << 3));
255 tcg_out8(s, 0x24);
256 } else {
257 tcg_out8(s, 0x80 | (r << 3) | rm);
258 }
259 tcg_out32(s, offset);
260 }
261}
262
263static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
264{
265 if (arg != ret)
266 tcg_out_modrm(s, 0x8b, ret, arg);
267}
268
269static inline void tcg_out_movi(TCGContext *s, TCGType type,
270 int ret, int32_t arg)
271{
272 if (arg == 0) {
273 /* xor r0,r0 */
274 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret);
275 } else {
276 tcg_out8(s, 0xb8 + ret);
277 tcg_out32(s, arg);
278 }
279}
280
281static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
282 int arg1, tcg_target_long arg2)
283{
284 /* movl */
285 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
286}
287
288static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
289 int arg1, tcg_target_long arg2)
290{
291 /* movl */
292 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
293}
294
295static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
296{
297 if (val == (int8_t)val) {
298 tcg_out_modrm(s, 0x83, c, r0);
299 tcg_out8(s, val);
300 } else {
301 tcg_out_modrm(s, 0x81, c, r0);
302 tcg_out32(s, val);
303 }
304}
305
306static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
307{
308 if (val != 0)
309 tgen_arithi(s, ARITH_ADD, reg, val);
310}
311
312#ifdef VBOX
313static void tcg_out_subi(TCGContext *s, int reg, tcg_target_long val)
314{
315 if (val != 0)
316 tgen_arithi(s, ARITH_SUB, reg, val);
317}
318#endif
319
320static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
321{
322 int32_t val, val1;
323 TCGLabel *l = &s->labels[label_index];
324
325 if (l->has_value) {
326 val = l->u.value - (tcg_target_long)s->code_ptr;
327 val1 = val - 2;
328 if ((int8_t)val1 == val1) {
329 if (opc == -1)
330 tcg_out8(s, 0xeb);
331 else
332 tcg_out8(s, 0x70 + opc);
333 tcg_out8(s, val1);
334 } else {
335 if (opc == -1) {
336 tcg_out8(s, 0xe9);
337 tcg_out32(s, val - 5);
338 } else {
339 tcg_out8(s, 0x0f);
340 tcg_out8(s, 0x80 + opc);
341 tcg_out32(s, val - 6);
342 }
343 }
344 } else {
345 if (opc == -1) {
346 tcg_out8(s, 0xe9);
347 } else {
348 tcg_out8(s, 0x0f);
349 tcg_out8(s, 0x80 + opc);
350 }
351 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
352 s->code_ptr += 4;
353 }
354}
355
356static void tcg_out_brcond(TCGContext *s, int cond,
357 TCGArg arg1, TCGArg arg2, int const_arg2,
358 int label_index)
359{
360 if (const_arg2) {
361 if (arg2 == 0) {
362 /* test r, r */
363 tcg_out_modrm(s, 0x85, arg1, arg1);
364 } else {
365 tgen_arithi(s, ARITH_CMP, arg1, arg2);
366 }
367 } else {
368 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3), arg2, arg1);
369 }
370 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
371}
372
373#ifdef VBOX
374
375DECLINLINE(void) tcg_out_long_call(TCGContext *s, void* dst)
376{
377 intptr_t disp;
378# ifdef VBOX
379 tcg_gen_stack_alignment_check(s);
380# endif
381 disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
382 tcg_out8(s, 0xe8); /* call disp32 */
383 tcg_out32(s, disp); /* disp32 */
384}
385
386DECLINLINE(void) tcg_out_long_jmp(TCGContext *s, void* dst)
387{
388 intptr_t disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
389 tcg_out8(s, 0xe9); /* jmp disp32 */
390 tcg_out32(s, disp); /* disp32 */
391}
392
393#endif /* VBOX */
394
395/* XXX: we implement it at the target level to avoid having to
396 handle cross basic blocks temporaries */
397static void tcg_out_brcond2(TCGContext *s,
398 const TCGArg *args, const int *const_args)
399{
400 int label_next;
401 label_next = gen_new_label();
402 switch(args[4]) {
403 case TCG_COND_EQ:
404 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
405 tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
406 break;
407 case TCG_COND_NE:
408 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
409 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
410 break;
411 case TCG_COND_LT:
412 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
413 tcg_out_jxx(s, JCC_JNE, label_next);
414 tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
415 break;
416 case TCG_COND_LE:
417 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
418 tcg_out_jxx(s, JCC_JNE, label_next);
419 tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
420 break;
421 case TCG_COND_GT:
422 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
423 tcg_out_jxx(s, JCC_JNE, label_next);
424 tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
425 break;
426 case TCG_COND_GE:
427 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
428 tcg_out_jxx(s, JCC_JNE, label_next);
429 tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
430 break;
431 case TCG_COND_LTU:
432 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
433 tcg_out_jxx(s, JCC_JNE, label_next);
434 tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
435 break;
436 case TCG_COND_LEU:
437 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
438 tcg_out_jxx(s, JCC_JNE, label_next);
439 tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
440 break;
441 case TCG_COND_GTU:
442 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
443 tcg_out_jxx(s, JCC_JNE, label_next);
444 tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
445 break;
446 case TCG_COND_GEU:
447 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
448 tcg_out_jxx(s, JCC_JNE, label_next);
449 tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
450 break;
451 default:
452 tcg_abort();
453 }
454 tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
455}
456
457#if defined(CONFIG_SOFTMMU)
458
459#include "../../softmmu_defs.h"
460
461static void *qemu_ld_helpers[4] = {
462 __ldb_mmu,
463 __ldw_mmu,
464 __ldl_mmu,
465 __ldq_mmu,
466};
467
468static void *qemu_st_helpers[4] = {
469 __stb_mmu,
470 __stw_mmu,
471 __stl_mmu,
472 __stq_mmu,
473};
474#endif
475
476#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
477static void *vbox_ld_helpers[] = {
478 __ldub_vbox_phys,
479 __lduw_vbox_phys,
480 __ldul_vbox_phys,
481 __ldq_vbox_phys,
482 __ldb_vbox_phys,
483 __ldw_vbox_phys,
484 __ldl_vbox_phys,
485 __ldq_vbox_phys,
486};
487
488static void *vbox_st_helpers[] = {
489 __stb_vbox_phys,
490 __stw_vbox_phys,
491 __stl_vbox_phys,
492 __stq_vbox_phys
493};
494
495static void tcg_out_vbox_phys_read(TCGContext *s, int index,
496 int addr_reg,
497 int data_reg, int data_reg2)
498{
499 int useReg2 = ((index & 3) == 3);
500
501 /** @todo: should we make phys address accessors fastcalls - probably not a big deal */
502 /* out parameter (address), note that phys address is always 64-bit */
503 AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
504
505#if 0
506 tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
507 tcg_out_push(s, addr_reg);
508#else
509 /* mov addr_reg, %eax */
510 tcg_out_mov(s, TCG_REG_EAX, addr_reg);
511#endif
512
513 tcg_out_long_call(s, vbox_ld_helpers[index]);
514
515 /* mov %eax, data_reg */
516 tcg_out_mov(s, data_reg, TCG_REG_EAX);
517
518 /* returned 64-bit value */
519 if (useReg2)
520 tcg_out_mov(s, data_reg2, TCG_REG_EDX);
521}
522
523static void tcg_out_vbox_phys_write(TCGContext *s, int index,
524 int addr_reg,
525 int val_reg, int val_reg2) {
526 int useReg2 = ((index & 3) == 3);
527
528#if 0
529 /* out parameter (value2) */
530 if (useReg2)
531 tcg_out_push(s, val_reg2);
532 /* out parameter (value) */
533 tcg_out_push(s, val_reg);
534 /* out parameter (address), note that phys address is always 64-bit */
535 AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
536 tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
537 tcg_out_push(s, addr_reg);
538#else
539 Assert(val_reg != TCG_REG_EAX && (!useReg2 || (val_reg2 != TCG_REG_EAX)));
540 /* mov addr_reg, %eax */
541 tcg_out_mov(s, TCG_REG_EAX, addr_reg);
542 Assert(!useReg2 || (val_reg2 != TCG_REG_EDX));
543 /* mov val_reg, %edx */
544 tcg_out_mov(s, TCG_REG_EDX, val_reg);
545 if (useReg2)
546 tcg_out_mov(s, TCG_REG_ECX, val_reg2);
547
548#endif
549 /* call it */
550 tcg_out_long_call(s, vbox_st_helpers[index]);
551
552 /* clean stack after us */
553#if 0
554 tcg_out_addi(s, TCG_REG_ESP, 8 + (useReg2 ? 8 : 4));
555# endif
556}
557
558#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
559
560/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
561 EAX. It will be useful once fixed registers globals are less
562 common. */
563static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
564 int opc)
565{
566 int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
567#if defined(CONFIG_SOFTMMU)
568 uint8_t *label1_ptr, *label2_ptr;
569#endif
570#if TARGET_LONG_BITS == 64
571#if defined(CONFIG_SOFTMMU)
572 uint8_t *label3_ptr;
573#endif
574 int addr_reg2;
575#endif
576
577 data_reg = *args++;
578 if (opc == 3)
579 data_reg2 = *args++;
580 else
581 data_reg2 = 0;
582 addr_reg = *args++;
583#if TARGET_LONG_BITS == 64
584 addr_reg2 = *args++;
585#endif
586 mem_index = *args;
587 s_bits = opc & 3;
588
589 r0 = TCG_REG_EAX;
590 r1 = TCG_REG_EDX;
591
592#if defined(CONFIG_SOFTMMU)
593 tcg_out_mov(s, r1, addr_reg);
594
595 tcg_out_mov(s, r0, addr_reg);
596
597 tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
598 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
599
600 tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
601 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
602
603 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
604 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
605
606#ifndef VBOX
607 tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
608 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
609 tcg_out8(s, (5 << 3) | r1);
610 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
611#else
612 tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
613 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
614 tcg_out8(s, (TCG_AREG0 << 3) | r1);
615 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
616#endif
617
618 /* cmp 0(r1), r0 */
619 tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
620
621 tcg_out_mov(s, r0, addr_reg);
622
623#if TARGET_LONG_BITS == 32
624 /* je label1 */
625 tcg_out8(s, 0x70 + JCC_JE);
626 label1_ptr = s->code_ptr;
627 s->code_ptr++;
628#else
629 /* jne label3 */
630 tcg_out8(s, 0x70 + JCC_JNE);
631 label3_ptr = s->code_ptr;
632 s->code_ptr++;
633
634 /* cmp 4(r1), addr_reg2 */
635 tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
636
637 /* je label1 */
638 tcg_out8(s, 0x70 + JCC_JE);
639 label1_ptr = s->code_ptr;
640 s->code_ptr++;
641
642 /* label3: */
643 *label3_ptr = s->code_ptr - label3_ptr - 1;
644#endif
645
646 /* XXX: move that code at the end of the TB */
647#if TARGET_LONG_BITS == 32
648 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
649#else
650 tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
651 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
652#endif
653#ifdef VBOX
654 tcg_gen_stack_alignment_check(s);
655#endif
656 tcg_out8(s, 0xe8);
657 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
658 (tcg_target_long)s->code_ptr - 4);
659
660 switch(opc) {
661 case 0 | 4:
662 /* movsbl */
663 tcg_out_modrm(s, 0xbe | P_EXT, data_reg, TCG_REG_EAX);
664 break;
665 case 1 | 4:
666 /* movswl */
667 tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX);
668 break;
669 case 0:
670 /* movzbl */
671 tcg_out_modrm(s, 0xb6 | P_EXT, data_reg, TCG_REG_EAX);
672 break;
673 case 1:
674 /* movzwl */
675 tcg_out_modrm(s, 0xb7 | P_EXT, data_reg, TCG_REG_EAX);
676 break;
677 case 2:
678 default:
679 tcg_out_mov(s, data_reg, TCG_REG_EAX);
680 break;
681 case 3:
682 if (data_reg == TCG_REG_EDX) {
683 tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
684 tcg_out_mov(s, data_reg2, TCG_REG_EAX);
685 } else {
686 tcg_out_mov(s, data_reg, TCG_REG_EAX);
687 tcg_out_mov(s, data_reg2, TCG_REG_EDX);
688 }
689 break;
690 }
691
692 /* jmp label2 */
693 tcg_out8(s, 0xeb);
694 label2_ptr = s->code_ptr;
695 s->code_ptr++;
696
697 /* label1: */
698 *label1_ptr = s->code_ptr - label1_ptr - 1;
699
700 /* add x(r1), r0 */
701 tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
702 offsetof(CPUTLBEntry, addr_read));
703#else
704 r0 = addr_reg;
705#endif
706
707#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
708#ifdef TARGET_WORDS_BIGENDIAN
709 bswap = 1;
710#else
711 bswap = 0;
712#endif
713 switch(opc) {
714 case 0:
715 /* movzbl */
716 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
717 break;
718 case 0 | 4:
719 /* movsbl */
720 tcg_out_modrm_offset(s, 0xbe | P_EXT, data_reg, r0, 0);
721 break;
722 case 1:
723 /* movzwl */
724 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
725 if (bswap) {
726 /* rolw $8, data_reg */
727 tcg_out8(s, 0x66);
728 tcg_out_modrm(s, 0xc1, 0, data_reg);
729 tcg_out8(s, 8);
730 }
731 break;
732 case 1 | 4:
733 /* movswl */
734 tcg_out_modrm_offset(s, 0xbf | P_EXT, data_reg, r0, 0);
735 if (bswap) {
736 /* rolw $8, data_reg */
737 tcg_out8(s, 0x66);
738 tcg_out_modrm(s, 0xc1, 0, data_reg);
739 tcg_out8(s, 8);
740
741 /* movswl data_reg, data_reg */
742 tcg_out_modrm(s, 0xbf | P_EXT, data_reg, data_reg);
743 }
744 break;
745 case 2:
746 /* movl (r0), data_reg */
747 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
748 if (bswap) {
749 /* bswap */
750 tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
751 }
752 break;
753 case 3:
754 /* XXX: could be nicer */
755 if (r0 == data_reg) {
756 r1 = TCG_REG_EDX;
757 if (r1 == data_reg)
758 r1 = TCG_REG_EAX;
759 tcg_out_mov(s, r1, r0);
760 r0 = r1;
761 }
762 if (!bswap) {
763 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
764 tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
765 } else {
766 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
767 tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
768
769 tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
770 /* bswap */
771 tcg_out_opc(s, (0xc8 + data_reg2) | P_EXT);
772 }
773 break;
774 default:
775 tcg_abort();
776 }
777#else /* VBOX */
778 tcg_out_vbox_phys_read(s, opc, r0, data_reg, data_reg2);
779#endif
780
781
782#if defined(CONFIG_SOFTMMU)
783 /* label2: */
784 *label2_ptr = s->code_ptr - label2_ptr - 1;
785# ifdef VBOX
786 Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
787# endif
788#endif
789}
790
791
792static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
793 int opc)
794{
795 int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
796#if defined(CONFIG_SOFTMMU)
797 uint8_t *label1_ptr, *label2_ptr;
798#endif
799#if TARGET_LONG_BITS == 64
800#if defined(CONFIG_SOFTMMU)
801 uint8_t *label3_ptr;
802#endif
803 int addr_reg2;
804#endif
805#ifdef VBOX
806# ifdef RT_OS_DARWIN
807 int bias1 = 12, bias3 = 4;/** @todo TCG_TARGET_STACK_ALIGN. */
808# else
809 int bias1 = 0, bias3 = 0;
810# endif
811 NOREF(bias3);
812#endif
813
814 data_reg = *args++;
815 if (opc == 3)
816 data_reg2 = *args++;
817 else
818 data_reg2 = 0;
819 addr_reg = *args++;
820#if TARGET_LONG_BITS == 64
821 addr_reg2 = *args++;
822#endif
823 mem_index = *args;
824
825 s_bits = opc;
826
827 r0 = TCG_REG_EAX;
828 r1 = TCG_REG_EDX;
829
830#if defined(CONFIG_SOFTMMU)
831 tcg_out_mov(s, r1, addr_reg);
832
833 tcg_out_mov(s, r0, addr_reg);
834
835 tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
836 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
837
838 tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
839 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
840
841 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
842 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
843
844#ifndef VBOX
845 tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
846 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
847 tcg_out8(s, (5 << 3) | r1);
848 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
849#else
850 tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
851 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
852 tcg_out8(s, (TCG_AREG0 << 3) | r1);
853 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
854#endif
855
856 /* cmp 0(r1), r0 */
857 tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
858
859 tcg_out_mov(s, r0, addr_reg);
860
861#if TARGET_LONG_BITS == 32
862 /* je label1 */
863 tcg_out8(s, 0x70 + JCC_JE);
864 label1_ptr = s->code_ptr;
865 s->code_ptr++;
866#else
867 /* jne label3 */
868 tcg_out8(s, 0x70 + JCC_JNE);
869 label3_ptr = s->code_ptr;
870 s->code_ptr++;
871
872 /* cmp 4(r1), addr_reg2 */
873 tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
874
875 /* je label1 */
876 tcg_out8(s, 0x70 + JCC_JE);
877 label1_ptr = s->code_ptr;
878 s->code_ptr++;
879
880 /* label3: */
881 *label3_ptr = s->code_ptr - label3_ptr - 1;
882#endif
883
884 /* XXX: move that code at the end of the TB */
885#if TARGET_LONG_BITS == 32
886 if (opc == 3) {
887 tcg_out_mov(s, TCG_REG_EDX, data_reg);
888 tcg_out_mov(s, TCG_REG_ECX, data_reg2);
889#ifdef VBOX
890 tcg_out_subi(s, TCG_REG_ESP, bias1);
891#endif
892 tcg_out8(s, 0x6a); /* push Ib */
893 tcg_out8(s, mem_index);
894# ifdef VBOX
895 tcg_gen_stack_alignment_check(s);
896# endif
897 tcg_out8(s, 0xe8);
898 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
899 (tcg_target_long)s->code_ptr - 4);
900#ifdef VBOX
901 tcg_out_addi(s, TCG_REG_ESP, 4+bias1);
902#else
903 tcg_out_addi(s, TCG_REG_ESP, 4);
904#endif
905 } else {
906 switch(opc) {
907 case 0:
908 /* movzbl */
909 tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_EDX, data_reg);
910 break;
911 case 1:
912 /* movzwl */
913 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_EDX, data_reg);
914 break;
915 case 2:
916 tcg_out_mov(s, TCG_REG_EDX, data_reg);
917 break;
918 }
919 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
920# ifdef VBOX
921 tcg_gen_stack_alignment_check(s);
922# endif
923 tcg_out8(s, 0xe8);
924 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
925 (tcg_target_long)s->code_ptr - 4);
926 }
927#else
928 if (opc == 3) {
929 tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
930# ifdef VBOX
931 tcg_out_subi(s, TCG_REG_ESP, bias3);
932# endif
933 tcg_out8(s, 0x6a); /* push Ib */
934 tcg_out8(s, mem_index);
935 tcg_out_opc(s, 0x50 + data_reg2); /* push */
936 tcg_out_opc(s, 0x50 + data_reg); /* push */
937# ifdef VBOX
938 tcg_gen_stack_alignment_check(s);
939# endif
940 tcg_out8(s, 0xe8);
941 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
942 (tcg_target_long)s->code_ptr - 4);
943#ifdef VBOX
944 tcg_out_addi(s, TCG_REG_ESP, 12+bias3);
945#else
946 tcg_out_addi(s, TCG_REG_ESP, 12);
947#endif
948 } else {
949 tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
950 switch(opc) {
951 case 0:
952 /* movzbl */
953 tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_ECX, data_reg);
954 break;
955 case 1:
956 /* movzwl */
957 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_ECX, data_reg);
958 break;
959 case 2:
960 tcg_out_mov(s, TCG_REG_ECX, data_reg);
961 break;
962 }
963# ifdef VBOX
964 tcg_out_subi(s, TCG_REG_ESP, bias1);
965# endif
966 tcg_out8(s, 0x6a); /* push Ib */
967 tcg_out8(s, mem_index);
968# ifdef VBOX
969 tcg_gen_stack_alignment_check(s);
970# endif
971 tcg_out8(s, 0xe8);
972 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
973 (tcg_target_long)s->code_ptr - 4);
974# if defined(VBOX)
975 tcg_out_addi(s, TCG_REG_ESP, 4 + bias1);
976# else
977 tcg_out_addi(s, TCG_REG_ESP, 4);
978# endif
979 }
980#endif
981
982 /* jmp label2 */
983 tcg_out8(s, 0xeb);
984 label2_ptr = s->code_ptr;
985 s->code_ptr++;
986
987 /* label1: */
988 *label1_ptr = s->code_ptr - label1_ptr - 1;
989
990 /* add x(r1), r0 */
991 tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
992 offsetof(CPUTLBEntry, addr_write));
993#else
994 r0 = addr_reg;
995#endif
996
997#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
998#ifdef TARGET_WORDS_BIGENDIAN
999 bswap = 1;
1000#else
1001 bswap = 0;
1002#endif
1003 switch(opc) {
1004 case 0:
1005 /* movb */
1006 tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
1007 break;
1008 case 1:
1009 if (bswap) {
1010 tcg_out_mov(s, r1, data_reg);
1011 tcg_out8(s, 0x66); /* rolw $8, %ecx */
1012 tcg_out_modrm(s, 0xc1, 0, r1);
1013 tcg_out8(s, 8);
1014 data_reg = r1;
1015 }
1016 /* movw */
1017 tcg_out8(s, 0x66);
1018 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1019 break;
1020 case 2:
1021 if (bswap) {
1022 tcg_out_mov(s, r1, data_reg);
1023 /* bswap data_reg */
1024 tcg_out_opc(s, (0xc8 + r1) | P_EXT);
1025 data_reg = r1;
1026 }
1027 /* movl */
1028 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1029 break;
1030 case 3:
1031 if (bswap) {
1032 tcg_out_mov(s, r1, data_reg2);
1033 /* bswap data_reg */
1034 tcg_out_opc(s, (0xc8 + r1) | P_EXT);
1035 tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
1036 tcg_out_mov(s, r1, data_reg);
1037 /* bswap data_reg */
1038 tcg_out_opc(s, (0xc8 + r1) | P_EXT);
1039 tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
1040 } else {
1041 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1042 tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
1043 }
1044 break;
1045 default:
1046 tcg_abort();
1047 }
1048#else /* VBOX && REM_PHYS_ADDR_IN_TLB */
1049 tcg_out_vbox_phys_write(s, opc, r0, data_reg, data_reg2);
1050#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
1051
1052#if defined(CONFIG_SOFTMMU)
1053 /* label2: */
1054 *label2_ptr = s->code_ptr - label2_ptr - 1;
1055# ifdef VBOX
1056 Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
1057# endif
1058#endif
1059}
1060
1061static inline void tcg_out_op(TCGContext *s, int opc,
1062 const TCGArg *args, const int *const_args)
1063{
1064 int c;
1065
1066 switch(opc) {
1067 case INDEX_op_exit_tb:
1068 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
1069 tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
1070 tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
1071 break;
1072 case INDEX_op_goto_tb:
1073 if (s->tb_jmp_offset) {
1074 /* direct jump method */
1075 tcg_out8(s, 0xe9); /* jmp im */
1076 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1077 tcg_out32(s, 0);
1078 } else {
1079 /* indirect jump method */
1080 /* jmp Ev */
1081 tcg_out_modrm_offset(s, 0xff, 4, -1,
1082 (tcg_target_long)(s->tb_next + args[0]));
1083 }
1084 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1085 break;
1086 case INDEX_op_call:
1087#ifdef VBOX
1088 tcg_gen_stack_alignment_check(s);
1089#endif
1090 if (const_args[0]) {
1091 tcg_out8(s, 0xe8);
1092 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1093 } else {
1094 tcg_out_modrm(s, 0xff, 2, args[0]);
1095 }
1096 break;
1097 case INDEX_op_jmp:
1098 if (const_args[0]) {
1099 tcg_out8(s, 0xe9);
1100 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1101 } else {
1102 tcg_out_modrm(s, 0xff, 4, args[0]);
1103 }
1104 break;
1105 case INDEX_op_br:
1106 tcg_out_jxx(s, JCC_JMP, args[0]);
1107 break;
1108 case INDEX_op_movi_i32:
1109 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1110 break;
1111 case INDEX_op_ld8u_i32:
1112 /* movzbl */
1113 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
1114 break;
1115 case INDEX_op_ld8s_i32:
1116 /* movsbl */
1117 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
1118 break;
1119 case INDEX_op_ld16u_i32:
1120 /* movzwl */
1121 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
1122 break;
1123 case INDEX_op_ld16s_i32:
1124 /* movswl */
1125 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
1126 break;
1127 case INDEX_op_ld_i32:
1128 /* movl */
1129 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1130 break;
1131 case INDEX_op_st8_i32:
1132 /* movb */
1133 tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
1134 break;
1135 case INDEX_op_st16_i32:
1136 /* movw */
1137 tcg_out8(s, 0x66);
1138 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1139 break;
1140 case INDEX_op_st_i32:
1141 /* movl */
1142 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1143 break;
1144 case INDEX_op_sub_i32:
1145 c = ARITH_SUB;
1146 goto gen_arith;
1147 case INDEX_op_and_i32:
1148 c = ARITH_AND;
1149 goto gen_arith;
1150 case INDEX_op_or_i32:
1151 c = ARITH_OR;
1152 goto gen_arith;
1153 case INDEX_op_xor_i32:
1154 c = ARITH_XOR;
1155 goto gen_arith;
1156 case INDEX_op_add_i32:
1157 c = ARITH_ADD;
1158 gen_arith:
1159 if (const_args[2]) {
1160 tgen_arithi(s, c, args[0], args[2]);
1161 } else {
1162 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
1163 }
1164 break;
1165 case INDEX_op_mul_i32:
1166 if (const_args[2]) {
1167 int32_t val;
1168 val = args[2];
1169 if (val == (int8_t)val) {
1170 tcg_out_modrm(s, 0x6b, args[0], args[0]);
1171 tcg_out8(s, val);
1172 } else {
1173 tcg_out_modrm(s, 0x69, args[0], args[0]);
1174 tcg_out32(s, val);
1175 }
1176 } else {
1177 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1178 }
1179 break;
1180 case INDEX_op_mulu2_i32:
1181 tcg_out_modrm(s, 0xf7, 4, args[3]);
1182 break;
1183 case INDEX_op_div2_i32:
1184 tcg_out_modrm(s, 0xf7, 7, args[4]);
1185 break;
1186 case INDEX_op_divu2_i32:
1187 tcg_out_modrm(s, 0xf7, 6, args[4]);
1188 break;
1189 case INDEX_op_shl_i32:
1190 c = SHIFT_SHL;
1191 gen_shift32:
1192 if (const_args[2]) {
1193 if (args[2] == 1) {
1194 tcg_out_modrm(s, 0xd1, c, args[0]);
1195 } else {
1196 tcg_out_modrm(s, 0xc1, c, args[0]);
1197 tcg_out8(s, args[2]);
1198 }
1199 } else {
1200 tcg_out_modrm(s, 0xd3, c, args[0]);
1201 }
1202 break;
1203 case INDEX_op_shr_i32:
1204 c = SHIFT_SHR;
1205 goto gen_shift32;
1206 case INDEX_op_sar_i32:
1207 c = SHIFT_SAR;
1208 goto gen_shift32;
1209 case INDEX_op_rotl_i32:
1210 c = SHIFT_ROL;
1211 goto gen_shift32;
1212 case INDEX_op_rotr_i32:
1213 c = SHIFT_ROR;
1214 goto gen_shift32;
1215
1216 case INDEX_op_add2_i32:
1217 if (const_args[4])
1218 tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1219 else
1220 tcg_out_modrm(s, 0x01 | (ARITH_ADD << 3), args[4], args[0]);
1221 if (const_args[5])
1222 tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1223 else
1224 tcg_out_modrm(s, 0x01 | (ARITH_ADC << 3), args[5], args[1]);
1225 break;
1226 case INDEX_op_sub2_i32:
1227 if (const_args[4])
1228 tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1229 else
1230 tcg_out_modrm(s, 0x01 | (ARITH_SUB << 3), args[4], args[0]);
1231 if (const_args[5])
1232 tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1233 else
1234 tcg_out_modrm(s, 0x01 | (ARITH_SBB << 3), args[5], args[1]);
1235 break;
1236 case INDEX_op_brcond_i32:
1237 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1238 break;
1239 case INDEX_op_brcond2_i32:
1240 tcg_out_brcond2(s, args, const_args);
1241 break;
1242
1243 case INDEX_op_bswap16_i32:
1244 tcg_out8(s, 0x66);
1245 tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
1246 tcg_out8(s, 8);
1247 break;
1248 case INDEX_op_bswap32_i32:
1249 tcg_out_opc(s, (0xc8 + args[0]) | P_EXT);
1250 break;
1251
1252 case INDEX_op_neg_i32:
1253 tcg_out_modrm(s, 0xf7, 3, args[0]);
1254 break;
1255
1256 case INDEX_op_not_i32:
1257 tcg_out_modrm(s, 0xf7, 2, args[0]);
1258 break;
1259
1260 case INDEX_op_ext8s_i32:
1261 tcg_out_modrm(s, 0xbe | P_EXT, args[0], args[1]);
1262 break;
1263 case INDEX_op_ext16s_i32:
1264 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1265 break;
1266
1267 case INDEX_op_qemu_ld8u:
1268 tcg_out_qemu_ld(s, args, 0);
1269 break;
1270 case INDEX_op_qemu_ld8s:
1271 tcg_out_qemu_ld(s, args, 0 | 4);
1272 break;
1273 case INDEX_op_qemu_ld16u:
1274 tcg_out_qemu_ld(s, args, 1);
1275 break;
1276 case INDEX_op_qemu_ld16s:
1277 tcg_out_qemu_ld(s, args, 1 | 4);
1278 break;
1279 case INDEX_op_qemu_ld32u:
1280 tcg_out_qemu_ld(s, args, 2);
1281 break;
1282 case INDEX_op_qemu_ld64:
1283 tcg_out_qemu_ld(s, args, 3);
1284 break;
1285
1286 case INDEX_op_qemu_st8:
1287 tcg_out_qemu_st(s, args, 0);
1288 break;
1289 case INDEX_op_qemu_st16:
1290 tcg_out_qemu_st(s, args, 1);
1291 break;
1292 case INDEX_op_qemu_st32:
1293 tcg_out_qemu_st(s, args, 2);
1294 break;
1295 case INDEX_op_qemu_st64:
1296 tcg_out_qemu_st(s, args, 3);
1297 break;
1298
1299 default:
1300 tcg_abort();
1301 }
1302}
1303
1304static const TCGTargetOpDef x86_op_defs[] = {
1305 { INDEX_op_exit_tb, {"", "" } },
1306 { INDEX_op_goto_tb, {"", "" } },
1307 { INDEX_op_call, { "ri", "", } },
1308 { INDEX_op_jmp, { "ri", ""} },
1309 { INDEX_op_br, {"", "" } },
1310 { INDEX_op_mov_i32, { "r", "r" } },
1311 { INDEX_op_movi_i32, { "r" } },
1312 { INDEX_op_ld8u_i32, { "r", "r" } },
1313 { INDEX_op_ld8s_i32, { "r", "r" } },
1314 { INDEX_op_ld16u_i32, { "r", "r" } },
1315 { INDEX_op_ld16s_i32, { "r", "r" } },
1316 { INDEX_op_ld_i32, { "r", "r" } },
1317 { INDEX_op_st8_i32, { "q", "r" } },
1318 { INDEX_op_st16_i32, { "r", "r" } },
1319 { INDEX_op_st_i32, { "r", "r" } },
1320
1321 { INDEX_op_add_i32, { "r", "0", "ri" } },
1322 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1323 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1324 { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1325 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1326 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1327 { INDEX_op_and_i32, { "r", "0", "ri" } },
1328 { INDEX_op_or_i32, { "r", "0", "ri" } },
1329 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1330
1331 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1332 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1333 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1334 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1335 { INDEX_op_rotl_i32, { "r", "0", "ci" } },
1336 { INDEX_op_rotr_i32, { "r", "0", "ci" } },
1337
1338 { INDEX_op_brcond_i32, { "r", "ri" } },
1339
1340 { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1341 { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1342 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1343
1344 { INDEX_op_bswap16_i32, { "r", "0" } },
1345 { INDEX_op_bswap32_i32, { "r", "0" } },
1346
1347 { INDEX_op_neg_i32, { "r", "0" } },
1348
1349 { INDEX_op_not_i32, { "r", "0" } },
1350
1351 { INDEX_op_ext8s_i32, { "r", "q" } },
1352 { INDEX_op_ext16s_i32, { "r", "r" } },
1353
1354#if TARGET_LONG_BITS == 32
1355 { INDEX_op_qemu_ld8u, { "r", "L" } },
1356 { INDEX_op_qemu_ld8s, { "r", "L" } },
1357 { INDEX_op_qemu_ld16u, { "r", "L" } },
1358 { INDEX_op_qemu_ld16s, { "r", "L" } },
1359 { INDEX_op_qemu_ld32u, { "r", "L" } },
1360 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1361
1362 { INDEX_op_qemu_st8, { "cb", "L" } },
1363 { INDEX_op_qemu_st16, { "L", "L" } },
1364 { INDEX_op_qemu_st32, { "L", "L" } },
1365 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1366#else
1367 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1368 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1369 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1370 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1371 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1372 { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1373
1374 { INDEX_op_qemu_st8, { "cb", "L", "L" } },
1375 { INDEX_op_qemu_st16, { "L", "L", "L" } },
1376 { INDEX_op_qemu_st32, { "L", "L", "L" } },
1377 { INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1378#endif
1379#ifndef VBOX
1380 { -1 },
1381#else
1382 { -1, {"", "", "", ""} },
1383#endif
1384};
1385
1386static int tcg_target_callee_save_regs[] = {
1387#ifndef VBOX
1388 /* TCG_REG_EBP, */ /* currently used for the global env, so no
1389 need to save */
1390 TCG_REG_EBX,
1391 TCG_REG_ESI,
1392 TCG_REG_EDI,
1393#else
1394 TCG_REG_EBP,
1395 TCG_REG_EBX,
1396 /* TCG_REG_ESI, */ /* currently used for the global env, so no
1397 need to save */
1398 TCG_REG_EDI,
1399#endif
1400};
1401
1402static inline void tcg_out_push(TCGContext *s, int reg)
1403{
1404 tcg_out_opc(s, 0x50 + reg);
1405}
1406
1407static inline void tcg_out_pop(TCGContext *s, int reg)
1408{
1409 tcg_out_opc(s, 0x58 + reg);
1410}
1411
1412/* Generate global QEMU prologue and epilogue code */
1413void tcg_target_qemu_prologue(TCGContext *s)
1414{
1415 int i, frame_size, push_size, stack_addend;
1416
1417 /* TB prologue */
1418 /* save all callee saved registers */
1419 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1420 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1421 }
1422 /* reserve some stack space */
1423 push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1424 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1425 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1426 ~(TCG_TARGET_STACK_ALIGN - 1);
1427 stack_addend = frame_size - push_size;
1428 tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1429# ifdef VBOX
1430 tcg_gen_stack_alignment_check(s);
1431# endif
1432
1433 tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp *%eax */
1434
1435 /* TB epilogue */
1436 tb_ret_addr = s->code_ptr;
1437 tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1438 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1439 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1440 }
1441 tcg_out8(s, 0xc3); /* ret */
1442}
1443
1444void tcg_target_init(TCGContext *s)
1445{
1446 /* fail safe */
1447 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1448 tcg_abort();
1449
1450 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1451 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1452 (1 << TCG_REG_EAX) |
1453 (1 << TCG_REG_EDX) |
1454 (1 << TCG_REG_ECX));
1455
1456 tcg_regset_clear(s->reserved_regs);
1457 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1458
1459 tcg_add_target_add_op_defs(x86_op_defs);
1460}
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