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source: vbox/trunk/src/recompiler/tcg/tcg-dyngen.c@ 38716

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1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#ifndef VBOX
26#include <assert.h>
27#include <stdarg.h>
28#include <stdlib.h>
29#include <stdio.h>
30#include <string.h>
31#include <inttypes.h>
32#else
33# include <stdio.h>
34# include "osdep.h"
35#endif
36
37#include "config.h"
38#include "osdep.h"
39
40#include "tcg.h"
41
42int __op_param1, __op_param2, __op_param3;
43#if defined(__sparc__) || defined(__arm__)
44 void __op_gen_label1(){}
45 void __op_gen_label2(){}
46 void __op_gen_label3(){}
47#else
48 int __op_gen_label1, __op_gen_label2, __op_gen_label3;
49#endif
50int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
51
52#if 0
53#if defined(__s390__)
54static inline void flush_icache_range(unsigned long start, unsigned long stop)
55{
56}
57#elif defined(__ia64__)
58static inline void flush_icache_range(unsigned long start, unsigned long stop)
59{
60 while (start < stop) {
61 asm volatile ("fc %0" :: "r"(start));
62 start += 32;
63 }
64 asm volatile (";;sync.i;;srlz.i;;");
65}
66#elif defined(__powerpc__)
67
68#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
69
70static inline void flush_icache_range(unsigned long start, unsigned long stop)
71{
72 unsigned long p;
73
74 start &= ~(MIN_CACHE_LINE_SIZE - 1);
75 stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
76
77 for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
78 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
79 }
80 asm volatile ("sync" : : : "memory");
81 for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
82 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
83 }
84 asm volatile ("sync" : : : "memory");
85 asm volatile ("isync" : : : "memory");
86}
87#elif defined(__alpha__)
88static inline void flush_icache_range(unsigned long start, unsigned long stop)
89{
90 asm ("imb");
91}
92#elif defined(__sparc__)
93static inline void flush_icache_range(unsigned long start, unsigned long stop)
94{
95 unsigned long p;
96
97 p = start & ~(8UL - 1UL);
98 stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
99
100 for (; p < stop; p += 8)
101 __asm__ __volatile__("flush\t%0" : : "r" (p));
102}
103#elif defined(__arm__)
104static inline void flush_icache_range(unsigned long start, unsigned long stop)
105{
106 register unsigned long _beg __asm ("a1") = start;
107 register unsigned long _end __asm ("a2") = stop;
108 register unsigned long _flg __asm ("a3") = 0;
109 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
110}
111#elif defined(__mc68000)
112
113# include <asm/cachectl.h>
114static inline void flush_icache_range(unsigned long start, unsigned long stop)
115{
116 cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
117}
118#elif defined(__mips__)
119
120#include <sys/cachectl.h>
121static inline void flush_icache_range(unsigned long start, unsigned long stop)
122{
123 _flush_cache ((void *)start, stop - start, BCACHE);
124}
125#else
126#error unsupported CPU
127#endif
128
129#ifdef __alpha__
130
131register int gp asm("$29");
132
133static inline void immediate_ldah(void *p, int val) {
134 uint32_t *dest = p;
135 long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff;
136
137 *dest &= ~0xffff;
138 *dest |= high;
139 *dest |= 31 << 16;
140}
141static inline void immediate_lda(void *dest, int val) {
142 *(uint16_t *) dest = val;
143}
144void fix_bsr(void *p, int offset) {
145 uint32_t *dest = p;
146 *dest &= ~((1 << 21) - 1);
147 *dest |= (offset >> 2) & ((1 << 21) - 1);
148}
149
150#endif /* __alpha__ */
151
152#ifdef __ia64
153
154/* Patch instruction with "val" where "mask" has 1 bits. */
155static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
156{
157 uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
158# define insn_mask ((1UL << 41) - 1)
159 unsigned long shift;
160
161 b0 = b[0]; b1 = b[1];
162 shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */
163 if (shift >= 64) {
164 m1 = mask << (shift - 64);
165 v1 = val << (shift - 64);
166 } else {
167 m0 = mask << shift; m1 = mask >> (64 - shift);
168 v0 = val << shift; v1 = val >> (64 - shift);
169 b[0] = (b0 & ~m0) | (v0 & m0);
170 }
171 b[1] = (b1 & ~m1) | (v1 & m1);
172}
173
174static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val)
175{
176 ia64_patch(insn_addr,
177 0x011ffffe000UL,
178 ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
179 | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
180 ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18);
181}
182
183static inline void ia64_imm64 (void *insn, uint64_t val)
184{
185 /* Ignore the slot number of the relocation; GCC and Intel
186 toolchains differed for some time on whether IMM64 relocs are
187 against slot 1 (Intel) or slot 2 (GCC). */
188 uint64_t insn_addr = (uint64_t) insn & ~3UL;
189
190 ia64_patch(insn_addr + 2,
191 0x01fffefe000UL,
192 ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
193 | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */
194 | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */
195 | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */
196 | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)
197 );
198 ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
199}
200
201static inline void ia64_imm60b (void *insn, uint64_t val)
202{
203 /* Ignore the slot number of the relocation; GCC and Intel
204 toolchains differed for some time on whether IMM64 relocs are
205 against slot 1 (Intel) or slot 2 (GCC). */
206 uint64_t insn_addr = (uint64_t) insn & ~3UL;
207
208 if (val + ((uint64_t) 1 << 59) >= (1UL << 60))
209 fprintf(stderr, "%s: value %ld out of IMM60 range\n",
210 __FUNCTION__, (int64_t) val);
211 ia64_patch_imm60(insn_addr + 2, val);
212}
213
214static inline void ia64_imm22 (void *insn, uint64_t val)
215{
216 if (val + (1 << 21) >= (1 << 22))
217 fprintf(stderr, "%s: value %li out of IMM22 range\n",
218 __FUNCTION__, (int64_t)val);
219 ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
220 ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
221 | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */
222 | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */
223 | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */));
224}
225
226/* Like ia64_imm22(), but also clear bits 20-21. For addl, this has
227 the effect of turning "addl rX=imm22,rY" into "addl
228 rX=imm22,r0". */
229static inline void ia64_imm22_r0 (void *insn, uint64_t val)
230{
231 if (val + (1 << 21) >= (1 << 22))
232 fprintf(stderr, "%s: value %li out of IMM22 range\n",
233 __FUNCTION__, (int64_t)val);
234 ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20),
235 ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
236 | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */
237 | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */
238 | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */));
239}
240
241static inline void ia64_imm21b (void *insn, uint64_t val)
242{
243 if (val + (1 << 20) >= (1 << 21))
244 fprintf(stderr, "%s: value %li out of IMM21b range\n",
245 __FUNCTION__, (int64_t)val);
246 ia64_patch((uint64_t) insn, 0x11ffffe000UL,
247 ( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */
248 | ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */));
249}
250
251static inline void ia64_nop_b (void *insn)
252{
253 ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37);
254}
255
256static inline void ia64_ldxmov(void *insn, uint64_t val)
257{
258 if (val + (1 << 21) < (1 << 22))
259 ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37);
260}
261
262static inline int ia64_patch_ltoff(void *insn, uint64_t val,
263 int relaxable)
264{
265 if (relaxable && (val + (1 << 21) < (1 << 22))) {
266 ia64_imm22_r0(insn, val);
267 return 0;
268 }
269 return 1;
270}
271
272struct ia64_fixup {
273 struct ia64_fixup *next;
274 void *addr; /* address that needs to be patched */
275 long value;
276};
277
278#define IA64_PLT(insn, plt_index) \
279do { \
280 struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \
281 fixup->next = plt_fixes; \
282 plt_fixes = fixup; \
283 fixup->addr = (insn); \
284 fixup->value = (plt_index); \
285 plt_offset[(plt_index)] = 1; \
286} while (0)
287
288#define IA64_LTOFF(insn, val, relaxable) \
289do { \
290 if (ia64_patch_ltoff(insn, val, relaxable)) { \
291 struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \
292 fixup->next = ltoff_fixes; \
293 ltoff_fixes = fixup; \
294 fixup->addr = (insn); \
295 fixup->value = (val); \
296 } \
297} while (0)
298
299static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
300 struct ia64_fixup *ltoff_fixes,
301 uint64_t gp,
302 struct ia64_fixup *plt_fixes,
303 int num_plts,
304 unsigned long *plt_target,
305 unsigned int *plt_offset)
306{
307 static const uint8_t plt_bundle[] = {
308 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */
309 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60,
310
311 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */
312 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0
313 };
314 uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start;
315 uint64_t *vp;
316 struct ia64_fixup *fixup;
317 unsigned int offset = 0;
318 struct fdesc {
319 long ip;
320 long gp;
321 } *fdesc;
322 int i;
323
324 if (plt_fixes) {
325 plt_start = gen_code_ptr;
326
327 for (i = 0; i < num_plts; ++i) {
328 if (plt_offset[i]) {
329 plt_offset[i] = offset;
330 offset += sizeof(plt_bundle);
331
332 fdesc = (struct fdesc *) plt_target[i];
333 memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
334 ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
335 ia64_imm60b(gen_code_ptr + 0x12,
336 (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4);
337 gen_code_ptr += sizeof(plt_bundle);
338 }
339 }
340
341 for (fixup = plt_fixes; fixup; fixup = fixup->next)
342 ia64_imm21b(fixup->addr,
343 ((long) plt_start + plt_offset[fixup->value]
344 - ((long) fixup->addr & ~0xf)) >> 4);
345 }
346
347 got_start = gen_code_ptr;
348
349 /* First, create the GOT: */
350 for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
351 /* first check if we already have this value in the GOT: */
352 for (vp = (uint64_t *) got_start; vp < (uint64_t *) gen_code_ptr; ++vp)
353 if (*vp == fixup->value)
354 break;
355 if (vp == (uint64_t *) gen_code_ptr) {
356 /* Nope, we need to put the value in the GOT: */
357 *vp = fixup->value;
358 gen_code_ptr += 8;
359 }
360 ia64_imm22(fixup->addr, (long) vp - gp);
361 }
362 /* Keep code ptr aligned. */
363 if ((long) gen_code_ptr & 15)
364 gen_code_ptr += 8;
365 *gen_code_pp = gen_code_ptr;
366}
367#endif
368#endif
369
370#ifdef CONFIG_DYNGEN_OP
371
372#if defined __hppa__
373struct hppa_branch_stub {
374 uint32_t *location;
375 long target;
376 struct hppa_branch_stub *next;
377};
378
379#define HPPA_RECORD_BRANCH(LIST, LOC, TARGET) \
380do { \
381 struct hppa_branch_stub *stub = alloca(sizeof(struct hppa_branch_stub)); \
382 stub->location = LOC; \
383 stub->target = TARGET; \
384 stub->next = LIST; \
385 LIST = stub; \
386} while (0)
387
388static inline void hppa_process_stubs(struct hppa_branch_stub *stub,
389 uint8_t **gen_code_pp)
390{
391 uint32_t *s = (uint32_t *)*gen_code_pp;
392 uint32_t *p = s + 1;
393
394 if (!stub) return;
395
396 for (; stub != NULL; stub = stub->next) {
397 unsigned long l = (unsigned long)p;
398 /* stub:
399 * ldil L'target, %r1
400 * be,n R'target(%sr4,%r1)
401 */
402 *p++ = 0x20200000 | reassemble_21(lrsel(stub->target, 0));
403 *p++ = 0xe0202002 | (reassemble_17(rrsel(stub->target, 0) >> 2));
404 hppa_patch17f(stub->location, l, 0);
405 }
406 /* b,l,n stub,%r0 */
407 *s = 0xe8000002 | reassemble_17((p - s) - 2);
408 *gen_code_pp = (uint8_t *)p;
409}
410#endif /* __hppa__ */
411
412const TCGArg *dyngen_op(TCGContext *s, int opc, const TCGArg *opparam_ptr)
413{
414 uint8_t *gen_code_ptr;
415
416#ifdef __hppa__
417 struct hppa_branch_stub *hppa_stubs = NULL;
418#endif
419
420 gen_code_ptr = s->code_ptr;
421 switch(opc) {
422
423/* op.h is dynamically generated by dyngen.c from op.c */
424#include "op.h"
425
426 default:
427 tcg_abort();
428 }
429
430#ifdef __hppa__
431 hppa_process_stubs(hppa_stubs, &gen_code_ptr);
432#endif
433
434 s->code_ptr = gen_code_ptr;
435 return opparam_ptr;
436}
437#endif
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