1 | /*
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2 | * Tiny Code Generator for QEMU
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3 | *
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4 | * Copyright (c) 2008 Fabrice Bellard
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5 | *
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6 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | * of this software and associated documentation files (the "Software"), to deal
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8 | * in the Software without restriction, including without limitation the rights
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9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | * copies of the Software, and to permit persons to whom the Software is
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11 | * furnished to do so, subject to the following conditions:
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12 | *
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13 | * The above copyright notice and this permission notice shall be included in
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14 | * all copies or substantial portions of the Software.
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15 | *
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | * THE SOFTWARE.
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23 | */
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24 |
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25 | #ifndef NDEBUG
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26 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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27 | "%rax",
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28 | "%rcx",
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29 | "%rdx",
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30 | "%rbx",
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31 | "%rsp",
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32 | "%rbp",
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33 | "%rsi",
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34 | "%rdi",
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35 | "%r8",
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36 | "%r9",
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37 | "%r10",
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38 | "%r11",
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39 | "%r12",
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40 | "%r13",
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41 | "%r14",
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42 | "%r15",
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43 | };
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44 | #endif
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45 |
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46 | static const int tcg_target_reg_alloc_order[] = {
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47 | TCG_REG_RBP,
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48 | TCG_REG_RBX,
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49 | TCG_REG_R12,
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50 | TCG_REG_R13,
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51 | TCG_REG_R14,
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52 | TCG_REG_R15,
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53 | TCG_REG_R10,
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54 | TCG_REG_R11,
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55 | TCG_REG_R9,
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56 | TCG_REG_R8,
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57 | TCG_REG_RCX,
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58 | TCG_REG_RDX,
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59 | TCG_REG_RSI,
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60 | TCG_REG_RDI,
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61 | TCG_REG_RAX,
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62 | };
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63 |
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64 | static const int tcg_target_call_iarg_regs[6] = {
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65 | TCG_REG_RDI,
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66 | TCG_REG_RSI,
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67 | TCG_REG_RDX,
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68 | TCG_REG_RCX,
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69 | TCG_REG_R8,
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70 | TCG_REG_R9,
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71 | };
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72 |
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73 | static const int tcg_target_call_oarg_regs[2] = {
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74 | TCG_REG_RAX,
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75 | TCG_REG_RDX
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76 | };
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77 |
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78 | static uint8_t *tb_ret_addr;
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79 |
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80 | static void patch_reloc(uint8_t *code_ptr, int type,
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81 | tcg_target_long value, tcg_target_long addend)
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82 | {
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83 | value += addend;
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84 | switch(type) {
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85 | case R_X86_64_32:
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86 | if (value != (uint32_t)value)
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87 | tcg_abort();
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88 | *(uint32_t *)code_ptr = value;
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89 | break;
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90 | case R_X86_64_32S:
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91 | if (value != (int32_t)value)
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92 | tcg_abort();
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93 | *(uint32_t *)code_ptr = value;
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94 | break;
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95 | case R_386_PC32:
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96 | value -= (long)code_ptr;
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97 | if (value != (int32_t)value)
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98 | tcg_abort();
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99 | *(uint32_t *)code_ptr = value;
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100 | break;
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101 | default:
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102 | tcg_abort();
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103 | }
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104 | }
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105 |
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106 | /* maximum number of register used for input function arguments */
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107 | static inline int tcg_target_get_call_iarg_regs_count(int flags)
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108 | {
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109 | return 6;
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110 | }
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111 |
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112 | /* parse target specific constraints */
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113 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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114 | {
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115 | const char *ct_str;
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116 |
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117 | ct_str = *pct_str;
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118 | switch(ct_str[0]) {
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119 | case 'a':
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120 | ct->ct |= TCG_CT_REG;
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121 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
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122 | break;
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123 | case 'b':
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124 | ct->ct |= TCG_CT_REG;
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125 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
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126 | break;
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127 | case 'c':
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128 | ct->ct |= TCG_CT_REG;
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129 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
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130 | break;
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131 | case 'd':
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132 | ct->ct |= TCG_CT_REG;
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133 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
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134 | break;
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135 | case 'S':
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136 | ct->ct |= TCG_CT_REG;
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137 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
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138 | break;
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139 | case 'D':
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140 | ct->ct |= TCG_CT_REG;
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141 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
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142 | break;
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143 | case 'q':
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144 | ct->ct |= TCG_CT_REG;
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145 | tcg_regset_set32(ct->u.regs, 0, 0xf);
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146 | break;
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147 | case 'r':
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148 | ct->ct |= TCG_CT_REG;
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149 | tcg_regset_set32(ct->u.regs, 0, 0xffff);
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150 | break;
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151 | case 'L': /* qemu_ld/st constraint */
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152 | ct->ct |= TCG_CT_REG;
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153 | tcg_regset_set32(ct->u.regs, 0, 0xffff);
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154 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
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155 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
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156 | break;
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157 | case 'e':
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158 | ct->ct |= TCG_CT_CONST_S32;
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159 | break;
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160 | case 'Z':
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161 | ct->ct |= TCG_CT_CONST_U32;
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162 | break;
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163 | default:
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164 | return -1;
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165 | }
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166 | ct_str++;
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167 | *pct_str = ct_str;
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168 | return 0;
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169 | }
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170 |
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171 | /* test if a constant matches the constraint */
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172 | static inline int tcg_target_const_match(tcg_target_long val,
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173 | const TCGArgConstraint *arg_ct)
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174 | {
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175 | int ct;
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176 | ct = arg_ct->ct;
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177 | if (ct & TCG_CT_CONST)
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178 | return 1;
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179 | else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
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180 | return 1;
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181 | else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
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182 | return 1;
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183 | else
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184 | return 0;
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185 | }
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186 |
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187 | #define ARITH_ADD 0
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188 | #define ARITH_OR 1
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189 | #define ARITH_ADC 2
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190 | #define ARITH_SBB 3
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191 | #define ARITH_AND 4
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192 | #define ARITH_SUB 5
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193 | #define ARITH_XOR 6
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194 | #define ARITH_CMP 7
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195 |
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196 | #define SHIFT_ROL 0
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197 | #define SHIFT_ROR 1
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198 | #define SHIFT_SHL 4
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199 | #define SHIFT_SHR 5
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200 | #define SHIFT_SAR 7
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201 |
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202 | #define JCC_JMP (-1)
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203 | #define JCC_JO 0x0
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204 | #define JCC_JNO 0x1
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205 | #define JCC_JB 0x2
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206 | #define JCC_JAE 0x3
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207 | #define JCC_JE 0x4
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208 | #define JCC_JNE 0x5
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209 | #define JCC_JBE 0x6
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210 | #define JCC_JA 0x7
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211 | #define JCC_JS 0x8
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212 | #define JCC_JNS 0x9
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213 | #define JCC_JP 0xa
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214 | #define JCC_JNP 0xb
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215 | #define JCC_JL 0xc
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216 | #define JCC_JGE 0xd
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217 | #define JCC_JLE 0xe
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218 | #define JCC_JG 0xf
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219 |
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220 | #define P_EXT 0x100 /* 0x0f opcode prefix */
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221 | #define P_REXW 0x200 /* set rex.w = 1 */
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222 | #define P_REXB 0x400 /* force rex use for byte registers */
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223 |
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224 | static const uint8_t tcg_cond_to_jcc[10] = {
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225 | [TCG_COND_EQ] = JCC_JE,
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226 | [TCG_COND_NE] = JCC_JNE,
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227 | [TCG_COND_LT] = JCC_JL,
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228 | [TCG_COND_GE] = JCC_JGE,
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229 | [TCG_COND_LE] = JCC_JLE,
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230 | [TCG_COND_GT] = JCC_JG,
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231 | [TCG_COND_LTU] = JCC_JB,
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232 | [TCG_COND_GEU] = JCC_JAE,
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233 | [TCG_COND_LEU] = JCC_JBE,
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234 | [TCG_COND_GTU] = JCC_JA,
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235 | };
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236 |
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237 | static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
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238 | {
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239 | int rex;
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240 | rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
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241 | ((x >> 2) & 2) | ((rm >> 3) & 1);
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242 | if (rex || (opc & P_REXB)) {
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243 | tcg_out8(s, rex | 0x40);
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244 | }
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245 | if (opc & P_EXT)
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246 | tcg_out8(s, 0x0f);
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247 | tcg_out8(s, opc & 0xff);
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248 | }
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249 |
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250 | static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
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251 | {
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252 | tcg_out_opc(s, opc, r, rm, 0);
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253 | tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
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254 | }
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255 |
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256 | /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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257 | static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
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258 | tcg_target_long offset)
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259 | {
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260 | if (rm < 0) {
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261 | tcg_target_long val;
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262 | tcg_out_opc(s, opc, r, 0, 0);
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263 | val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
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264 | if (val == (int32_t)val) {
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265 | /* eip relative */
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266 | tcg_out8(s, 0x05 | ((r & 7) << 3));
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267 | tcg_out32(s, val);
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268 | } else if (offset == (int32_t)offset) {
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269 | tcg_out8(s, 0x04 | ((r & 7) << 3));
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270 | tcg_out8(s, 0x25); /* sib */
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271 | tcg_out32(s, offset);
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272 | } else {
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273 | tcg_abort();
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274 | }
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275 | } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
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276 | tcg_out_opc(s, opc, r, rm, 0);
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277 | if ((rm & 7) == TCG_REG_RSP) {
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278 | tcg_out8(s, 0x04 | ((r & 7) << 3));
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279 | tcg_out8(s, 0x24);
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280 | } else {
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281 | tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
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282 | }
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283 | } else if ((int8_t)offset == offset) {
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284 | tcg_out_opc(s, opc, r, rm, 0);
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285 | if ((rm & 7) == TCG_REG_RSP) {
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286 | tcg_out8(s, 0x44 | ((r & 7) << 3));
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287 | tcg_out8(s, 0x24);
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288 | } else {
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289 | tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
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290 | }
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291 | tcg_out8(s, offset);
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292 | } else {
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293 | tcg_out_opc(s, opc, r, rm, 0);
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294 | if ((rm & 7) == TCG_REG_RSP) {
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295 | tcg_out8(s, 0x84 | ((r & 7) << 3));
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296 | tcg_out8(s, 0x24);
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297 | } else {
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298 | tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
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299 | }
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300 | tcg_out32(s, offset);
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301 | }
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302 | }
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303 |
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304 | #if defined(CONFIG_SOFTMMU)
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305 | /* XXX: incomplete. index must be different from ESP */
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306 | static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
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307 | int index, int shift,
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308 | tcg_target_long offset)
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309 | {
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310 | int mod;
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311 | if (rm == -1)
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312 | tcg_abort();
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313 | if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
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314 | mod = 0;
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315 | } else if (offset == (int8_t)offset) {
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316 | mod = 0x40;
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317 | } else if (offset == (int32_t)offset) {
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318 | mod = 0x80;
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319 | } else {
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320 | tcg_abort();
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321 | }
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322 | if (index == -1) {
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323 | tcg_out_opc(s, opc, r, rm, 0);
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324 | if ((rm & 7) == TCG_REG_RSP) {
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325 | tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
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326 | tcg_out8(s, 0x04 | (rm & 7));
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327 | } else {
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328 | tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
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329 | }
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330 | } else {
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331 | tcg_out_opc(s, opc, r, rm, index);
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332 | tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
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333 | tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
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334 | }
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335 | if (mod == 0x40) {
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336 | tcg_out8(s, offset);
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337 | } else if (mod == 0x80) {
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338 | tcg_out32(s, offset);
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339 | }
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340 | }
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341 | #endif
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342 |
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343 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
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344 | {
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345 | tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
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346 | }
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347 |
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348 | static inline void tcg_out_movi(TCGContext *s, TCGType type,
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349 | int ret, tcg_target_long arg)
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350 | {
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351 | if (arg == 0) {
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352 | tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
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353 | } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
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354 | tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
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355 | tcg_out32(s, arg);
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356 | } else if (arg == (int32_t)arg) {
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357 | tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
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358 | tcg_out32(s, arg);
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359 | } else {
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360 | tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
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361 | tcg_out32(s, arg);
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362 | tcg_out32(s, arg >> 32);
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363 | }
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364 | }
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365 |
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366 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
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367 | int arg1, tcg_target_long arg2)
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368 | {
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369 | if (type == TCG_TYPE_I32)
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370 | tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
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371 | else
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372 | tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
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373 | }
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374 |
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375 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
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376 | int arg1, tcg_target_long arg2)
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377 | {
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378 | if (type == TCG_TYPE_I32)
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379 | tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
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380 | else
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381 | tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
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382 | }
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383 |
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384 | static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
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385 | {
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386 | if (val == (int8_t)val) {
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387 | tcg_out_modrm(s, 0x83, c, r0);
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388 | tcg_out8(s, val);
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389 | } else if (c == ARITH_AND && val == 0xffu) {
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390 | /* movzbl */
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391 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
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392 | } else if (c == ARITH_AND && val == 0xffffu) {
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393 | /* movzwl */
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394 | tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
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395 | } else {
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396 | tcg_out_modrm(s, 0x81, c, r0);
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397 | tcg_out32(s, val);
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398 | }
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399 | }
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400 |
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401 | static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
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402 | {
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403 | if (val == (int8_t)val) {
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404 | tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
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405 | tcg_out8(s, val);
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406 | } else if (c == ARITH_AND && val == 0xffu) {
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407 | /* movzbl */
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408 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
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409 | } else if (c == ARITH_AND && val == 0xffffu) {
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410 | /* movzwl */
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411 | tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
|
---|
412 | } else if (c == ARITH_AND && val == 0xffffffffu) {
|
---|
413 | /* 32-bit mov zero extends */
|
---|
414 | tcg_out_modrm(s, 0x8b, r0, r0);
|
---|
415 | } else if (val == (int32_t)val) {
|
---|
416 | tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
|
---|
417 | tcg_out32(s, val);
|
---|
418 | } else if (c == ARITH_AND && val == (uint32_t)val) {
|
---|
419 | tcg_out_modrm(s, 0x81, c, r0);
|
---|
420 | tcg_out32(s, val);
|
---|
421 | } else {
|
---|
422 | tcg_abort();
|
---|
423 | }
|
---|
424 | }
|
---|
425 |
|
---|
426 | static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
|
---|
427 | {
|
---|
428 | if (val != 0)
|
---|
429 | tgen_arithi64(s, ARITH_ADD, reg, val);
|
---|
430 | }
|
---|
431 |
|
---|
432 | static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
|
---|
433 | {
|
---|
434 | int32_t val, val1;
|
---|
435 | TCGLabel *l = &s->labels[label_index];
|
---|
436 |
|
---|
437 | if (l->has_value) {
|
---|
438 | val = l->u.value - (tcg_target_long)s->code_ptr;
|
---|
439 | val1 = val - 2;
|
---|
440 | if ((int8_t)val1 == val1) {
|
---|
441 | if (opc == -1)
|
---|
442 | tcg_out8(s, 0xeb);
|
---|
443 | else
|
---|
444 | tcg_out8(s, 0x70 + opc);
|
---|
445 | tcg_out8(s, val1);
|
---|
446 | } else {
|
---|
447 | if (opc == -1) {
|
---|
448 | tcg_out8(s, 0xe9);
|
---|
449 | tcg_out32(s, val - 5);
|
---|
450 | } else {
|
---|
451 | tcg_out8(s, 0x0f);
|
---|
452 | tcg_out8(s, 0x80 + opc);
|
---|
453 | tcg_out32(s, val - 6);
|
---|
454 | }
|
---|
455 | }
|
---|
456 | } else {
|
---|
457 | if (opc == -1) {
|
---|
458 | tcg_out8(s, 0xe9);
|
---|
459 | } else {
|
---|
460 | tcg_out8(s, 0x0f);
|
---|
461 | tcg_out8(s, 0x80 + opc);
|
---|
462 | }
|
---|
463 | tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
|
---|
464 | s->code_ptr += 4;
|
---|
465 | }
|
---|
466 | }
|
---|
467 |
|
---|
468 | static void tcg_out_brcond(TCGContext *s, int cond,
|
---|
469 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
---|
470 | int label_index, int rexw)
|
---|
471 | {
|
---|
472 | if (const_arg2) {
|
---|
473 | if (arg2 == 0) {
|
---|
474 | /* test r, r */
|
---|
475 | tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
|
---|
476 | } else {
|
---|
477 | if (rexw)
|
---|
478 | tgen_arithi64(s, ARITH_CMP, arg1, arg2);
|
---|
479 | else
|
---|
480 | tgen_arithi32(s, ARITH_CMP, arg1, arg2);
|
---|
481 | }
|
---|
482 | } else {
|
---|
483 | tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
|
---|
484 | }
|
---|
485 | tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
|
---|
486 | }
|
---|
487 |
|
---|
488 | #ifdef VBOX
|
---|
489 |
|
---|
490 | DECLINLINE(void) tcg_out_pushq(TCGContext *s, tcg_target_long val)
|
---|
491 | {
|
---|
492 | tcg_out8(s, 0x68); /* push imm32, subs 8 from rsp */
|
---|
493 | tcg_out32(s, val); /* imm32 */
|
---|
494 | if ((val >> 32) != 0)
|
---|
495 | {
|
---|
496 | tcg_out8(s, 0xc7); /* mov imm32, 4(%rsp) */
|
---|
497 | tcg_out8(s, 0x44);
|
---|
498 | tcg_out8(s, 0x24);
|
---|
499 | tcg_out8(s, 0x04);
|
---|
500 | tcg_out32(s, ((uint64_t)val) >> 32); /* imm32 */
|
---|
501 | }
|
---|
502 | }
|
---|
503 |
|
---|
504 | DECLINLINE(void) tcg_out_long_call(TCGContext *s, tcg_target_long dst)
|
---|
505 | {
|
---|
506 | intptr_t disp = dst - (tcg_target_long)s->code_ptr - 5;
|
---|
507 | /* can do normal call */
|
---|
508 | if (disp < 2LL * _1G && disp > -2LL * _1G)
|
---|
509 | {
|
---|
510 | tcg_out8(s, 0xe8); /* call disp32 */
|
---|
511 | tcg_out32(s, disp); /* disp32 */
|
---|
512 | }
|
---|
513 | else
|
---|
514 | {
|
---|
515 | # if 0
|
---|
516 | /* Somewhat tricky, but allows long jump not touching registers */
|
---|
517 | int off = 5 /* push imm32 */ + 5 /* push imm32 */ + 1 /* ret */;
|
---|
518 | if ((((uint64_t)s->code_ptr) + 32) >> 32)
|
---|
519 | off += 8;
|
---|
520 | if (dst >> 32)
|
---|
521 | off += 8;
|
---|
522 | /* return address */
|
---|
523 | tcg_out_pushq(s, (tcg_target_long)s->code_ptr+off);
|
---|
524 | /* destination */
|
---|
525 | tcg_out_pushq(s, dst);
|
---|
526 | tcg_out8(s, 0xc3); /* ret, used as call */
|
---|
527 | # else
|
---|
528 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
|
---|
529 | tcg_out8(s, 0xff); /* call *%eax */
|
---|
530 | tcg_out8(s, 0xd0);
|
---|
531 | # endif
|
---|
532 | }
|
---|
533 | }
|
---|
534 |
|
---|
535 | DECLINLINE(void) tcg_out_long_jmp(TCGContext *s, tcg_target_long dst)
|
---|
536 | {
|
---|
537 | intptr_t disp;
|
---|
538 |
|
---|
539 | disp = dst - (tcg_target_long)s->code_ptr - 2;
|
---|
540 | /* can do short relative jump */
|
---|
541 | if (disp < 0x7f && disp > -0x7f)
|
---|
542 | {
|
---|
543 | tcg_out8(s, 0xeb); /* short jmp */
|
---|
544 | tcg_out8(s, (int8_t)disp);
|
---|
545 | return;
|
---|
546 | }
|
---|
547 |
|
---|
548 | disp = dst - (tcg_target_long)s->code_ptr - 5;
|
---|
549 | if (disp < 2LL * _1G && disp > -2LL * _1G)
|
---|
550 | {
|
---|
551 | tcg_out8(s, 0xe9); /* jmp */
|
---|
552 | tcg_out32(s, (int32_t)disp);
|
---|
553 | return;
|
---|
554 | }
|
---|
555 | # if 0
|
---|
556 | tcg_out_pushq(s, dst);
|
---|
557 | tcg_out8(s, 0xc3); /* ret */
|
---|
558 | # else
|
---|
559 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
|
---|
560 | tcg_out8(s, 0xff); /* jmp *%eax */
|
---|
561 | tcg_out8(s, 0xe0);
|
---|
562 | # endif
|
---|
563 | }
|
---|
564 |
|
---|
565 | #endif /* VBOX */
|
---|
566 |
|
---|
567 | #if defined(CONFIG_SOFTMMU)
|
---|
568 |
|
---|
569 | #include "../../softmmu_defs.h"
|
---|
570 |
|
---|
571 | static void *qemu_ld_helpers[4] = {
|
---|
572 | __ldb_mmu,
|
---|
573 | __ldw_mmu,
|
---|
574 | __ldl_mmu,
|
---|
575 | __ldq_mmu,
|
---|
576 | };
|
---|
577 |
|
---|
578 | static void *qemu_st_helpers[4] = {
|
---|
579 | __stb_mmu,
|
---|
580 | __stw_mmu,
|
---|
581 | __stl_mmu,
|
---|
582 | __stq_mmu,
|
---|
583 | };
|
---|
584 | #endif
|
---|
585 |
|
---|
586 | #if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
|
---|
587 | static void *vbox_ld_helpers[] = {
|
---|
588 | __ldub_vbox_phys,
|
---|
589 | __lduw_vbox_phys,
|
---|
590 | __ldul_vbox_phys,
|
---|
591 | __ldq_vbox_phys,
|
---|
592 | __ldb_vbox_phys,
|
---|
593 | __ldw_vbox_phys,
|
---|
594 | __ldl_vbox_phys,
|
---|
595 | __ldq_vbox_phys,
|
---|
596 | };
|
---|
597 |
|
---|
598 | static void *vbox_st_helpers[] = {
|
---|
599 | __stb_vbox_phys,
|
---|
600 | __stw_vbox_phys,
|
---|
601 | __stl_vbox_phys,
|
---|
602 | __stq_vbox_phys
|
---|
603 | };
|
---|
604 |
|
---|
605 | static void tcg_out_vbox_phys_read(TCGContext *s, int index, int addr_reg, int data_reg) {
|
---|
606 | if (addr_reg != TCG_REG_RDI)
|
---|
607 | /* mov addr_reg, %rdi */
|
---|
608 | tcg_out_modrm(s, 0x8b | P_REXW, TCG_REG_RDI, addr_reg);
|
---|
609 |
|
---|
610 | tcg_out_long_call(s, (tcg_target_long)vbox_ld_helpers[index]);
|
---|
611 | /* mov %rax, data_reg*/
|
---|
612 | tcg_out_modrm(s, 0x8b | P_REXW, data_reg, TCG_REG_RAX);
|
---|
613 | }
|
---|
614 |
|
---|
615 | static void tcg_out_vbox_phys_write(TCGContext *s, int index, int addr_reg, int val_reg) {
|
---|
616 | if (addr_reg != TCG_REG_RDI)
|
---|
617 | /* mov addr_reg, %rdi */
|
---|
618 | tcg_out_modrm(s, 0x8b | P_REXW, TCG_REG_RDI, addr_reg);
|
---|
619 | if (val_reg != TCG_REG_RSI)
|
---|
620 | /* mov addr_reg, %rsi */
|
---|
621 | tcg_out_modrm(s, 0x8b | P_REXW, TCG_REG_RSI, val_reg);
|
---|
622 | tcg_out_long_call(s, (tcg_target_long)vbox_st_helpers[index]);
|
---|
623 | }
|
---|
624 |
|
---|
625 | #endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
|
---|
626 |
|
---|
627 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
|
---|
628 | int opc)
|
---|
629 | {
|
---|
630 | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
---|
631 | #if defined(CONFIG_SOFTMMU)
|
---|
632 | uint8_t *label1_ptr, *label2_ptr;
|
---|
633 | #endif
|
---|
634 |
|
---|
635 | data_reg = *args++;
|
---|
636 | addr_reg = *args++;
|
---|
637 | mem_index = *args;
|
---|
638 | s_bits = opc & 3;
|
---|
639 |
|
---|
640 | r0 = TCG_REG_RDI;
|
---|
641 | r1 = TCG_REG_RSI;
|
---|
642 |
|
---|
643 | #if TARGET_LONG_BITS == 32
|
---|
644 | rexw = 0;
|
---|
645 | #else
|
---|
646 | rexw = P_REXW;
|
---|
647 | #endif
|
---|
648 | #if defined(CONFIG_SOFTMMU)
|
---|
649 | /* mov */
|
---|
650 | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
---|
651 |
|
---|
652 | /* mov */
|
---|
653 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
---|
654 |
|
---|
655 | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
|
---|
656 | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
|
---|
657 |
|
---|
658 | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
|
---|
659 | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
|
---|
660 |
|
---|
661 | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
|
---|
662 | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
---|
663 |
|
---|
664 | /* lea offset(r1, env), r1 */
|
---|
665 | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
|
---|
666 | offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
---|
667 |
|
---|
668 | /* cmp 0(r1), r0 */
|
---|
669 | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
|
---|
670 |
|
---|
671 | /* mov */
|
---|
672 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
---|
673 |
|
---|
674 | /* je label1 */
|
---|
675 | tcg_out8(s, 0x70 + JCC_JE);
|
---|
676 | label1_ptr = s->code_ptr;
|
---|
677 | s->code_ptr++;
|
---|
678 |
|
---|
679 | /* XXX: move that code at the end of the TB */
|
---|
680 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
|
---|
681 | #ifndef VBOX
|
---|
682 | tcg_out8(s, 0xe8);
|
---|
683 | tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
|
---|
684 | (tcg_target_long)s->code_ptr - 4);
|
---|
685 | #else
|
---|
686 | tcg_out_long_call(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
|
---|
687 | #endif
|
---|
688 |
|
---|
689 | switch(opc) {
|
---|
690 | case 0 | 4:
|
---|
691 | /* movsbq */
|
---|
692 | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
---|
693 | break;
|
---|
694 | case 1 | 4:
|
---|
695 | /* movswq */
|
---|
696 | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
---|
697 | break;
|
---|
698 | case 2 | 4:
|
---|
699 | /* movslq */
|
---|
700 | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
|
---|
701 | break;
|
---|
702 | case 0:
|
---|
703 | /* movzbq */
|
---|
704 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
---|
705 | break;
|
---|
706 | case 1:
|
---|
707 | /* movzwq */
|
---|
708 | tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
---|
709 | break;
|
---|
710 | case 2:
|
---|
711 | default:
|
---|
712 | /* movl */
|
---|
713 | tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
|
---|
714 | break;
|
---|
715 | case 3:
|
---|
716 | tcg_out_mov(s, data_reg, TCG_REG_RAX);
|
---|
717 | break;
|
---|
718 | }
|
---|
719 |
|
---|
720 | /* jmp label2 */
|
---|
721 | tcg_out8(s, 0xeb);
|
---|
722 | label2_ptr = s->code_ptr;
|
---|
723 | s->code_ptr++;
|
---|
724 |
|
---|
725 | /* label1: */
|
---|
726 | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
---|
727 |
|
---|
728 | /* add x(r1), r0 */
|
---|
729 | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
---|
730 | offsetof(CPUTLBEntry, addr_read));
|
---|
731 | #else
|
---|
732 | r0 = addr_reg;
|
---|
733 | #endif
|
---|
734 |
|
---|
735 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
736 |
|
---|
737 | #ifdef TARGET_WORDS_BIGENDIAN
|
---|
738 | bswap = 1;
|
---|
739 | #else
|
---|
740 | bswap = 0;
|
---|
741 | #endif
|
---|
742 | switch(opc) {
|
---|
743 | case 0:
|
---|
744 | /* movzbl */
|
---|
745 | tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
|
---|
746 | break;
|
---|
747 | case 0 | 4:
|
---|
748 | /* movsbX */
|
---|
749 | tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
|
---|
750 | break;
|
---|
751 | case 1:
|
---|
752 | /* movzwl */
|
---|
753 | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
|
---|
754 | if (bswap) {
|
---|
755 | /* rolw $8, data_reg */
|
---|
756 | tcg_out8(s, 0x66);
|
---|
757 | tcg_out_modrm(s, 0xc1, 0, data_reg);
|
---|
758 | tcg_out8(s, 8);
|
---|
759 | }
|
---|
760 | break;
|
---|
761 | case 1 | 4:
|
---|
762 | if (bswap) {
|
---|
763 | /* movzwl */
|
---|
764 | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
|
---|
765 | /* rolw $8, data_reg */
|
---|
766 | tcg_out8(s, 0x66);
|
---|
767 | tcg_out_modrm(s, 0xc1, 0, data_reg);
|
---|
768 | tcg_out8(s, 8);
|
---|
769 |
|
---|
770 | /* movswX data_reg, data_reg */
|
---|
771 | tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
|
---|
772 | } else {
|
---|
773 | /* movswX */
|
---|
774 | tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
|
---|
775 | }
|
---|
776 | break;
|
---|
777 | case 2:
|
---|
778 | /* movl (r0), data_reg */
|
---|
779 | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
|
---|
780 | if (bswap) {
|
---|
781 | /* bswap */
|
---|
782 | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
|
---|
783 | }
|
---|
784 | break;
|
---|
785 | case 2 | 4:
|
---|
786 | if (bswap) {
|
---|
787 | /* movl (r0), data_reg */
|
---|
788 | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
|
---|
789 | /* bswap */
|
---|
790 | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
|
---|
791 | /* movslq */
|
---|
792 | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
|
---|
793 | } else {
|
---|
794 | /* movslq */
|
---|
795 | tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
|
---|
796 | }
|
---|
797 | break;
|
---|
798 | case 3:
|
---|
799 | /* movq (r0), data_reg */
|
---|
800 | tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
|
---|
801 | if (bswap) {
|
---|
802 | /* bswap */
|
---|
803 | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
|
---|
804 | }
|
---|
805 | break;
|
---|
806 | default:
|
---|
807 | tcg_abort();
|
---|
808 | }
|
---|
809 | #else /* VBOX && REM_PHYS_ADDR_IN_TLB */
|
---|
810 | tcg_out_vbox_phys_read(s, opc, r0, data_reg);
|
---|
811 | #endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
|
---|
812 |
|
---|
813 | #if defined(CONFIG_SOFTMMU)
|
---|
814 | /* label2: */
|
---|
815 | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
---|
816 | #endif
|
---|
817 | }
|
---|
818 |
|
---|
819 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
|
---|
820 | int opc)
|
---|
821 | {
|
---|
822 | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
---|
823 | #if defined(CONFIG_SOFTMMU)
|
---|
824 | uint8_t *label1_ptr, *label2_ptr;
|
---|
825 | #endif
|
---|
826 |
|
---|
827 | data_reg = *args++;
|
---|
828 | addr_reg = *args++;
|
---|
829 | mem_index = *args;
|
---|
830 |
|
---|
831 | s_bits = opc;
|
---|
832 |
|
---|
833 | r0 = TCG_REG_RDI;
|
---|
834 | r1 = TCG_REG_RSI;
|
---|
835 |
|
---|
836 | #if TARGET_LONG_BITS == 32
|
---|
837 | rexw = 0;
|
---|
838 | #else
|
---|
839 | rexw = P_REXW;
|
---|
840 | #endif
|
---|
841 | #if defined(CONFIG_SOFTMMU)
|
---|
842 | /* mov */
|
---|
843 | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
---|
844 |
|
---|
845 | /* mov */
|
---|
846 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
---|
847 |
|
---|
848 | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
|
---|
849 | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
|
---|
850 |
|
---|
851 | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
|
---|
852 | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
|
---|
853 |
|
---|
854 | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
|
---|
855 | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
---|
856 |
|
---|
857 | /* lea offset(r1, env), r1 */
|
---|
858 | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
|
---|
859 | offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
---|
860 |
|
---|
861 | /* cmp 0(r1), r0 */
|
---|
862 | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
|
---|
863 |
|
---|
864 | /* mov */
|
---|
865 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
---|
866 |
|
---|
867 | /* je label1 */
|
---|
868 | tcg_out8(s, 0x70 + JCC_JE);
|
---|
869 | label1_ptr = s->code_ptr;
|
---|
870 | s->code_ptr++;
|
---|
871 |
|
---|
872 | /* XXX: move that code at the end of the TB */
|
---|
873 | switch(opc) {
|
---|
874 | case 0:
|
---|
875 | /* movzbl */
|
---|
876 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
|
---|
877 | break;
|
---|
878 | case 1:
|
---|
879 | /* movzwl */
|
---|
880 | tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
|
---|
881 | break;
|
---|
882 | case 2:
|
---|
883 | /* movl */
|
---|
884 | tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
|
---|
885 | break;
|
---|
886 | default:
|
---|
887 | case 3:
|
---|
888 | tcg_out_mov(s, TCG_REG_RSI, data_reg);
|
---|
889 | break;
|
---|
890 | }
|
---|
891 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
|
---|
892 | #ifndef VBOX
|
---|
893 | tcg_out8(s, 0xe8);
|
---|
894 | tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
|
---|
895 | (tcg_target_long)s->code_ptr - 4);
|
---|
896 | #else
|
---|
897 | tcg_out_long_call(s, (tcg_target_long)qemu_st_helpers[s_bits]);
|
---|
898 | #endif
|
---|
899 |
|
---|
900 | /* jmp label2 */
|
---|
901 | tcg_out8(s, 0xeb);
|
---|
902 | label2_ptr = s->code_ptr;
|
---|
903 | s->code_ptr++;
|
---|
904 |
|
---|
905 | /* label1: */
|
---|
906 | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
---|
907 |
|
---|
908 | /* add x(r1), r0 */
|
---|
909 | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
---|
910 | offsetof(CPUTLBEntry, addr_write));
|
---|
911 | #else
|
---|
912 | r0 = addr_reg;
|
---|
913 | #endif
|
---|
914 |
|
---|
915 | #if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
916 | #ifdef TARGET_WORDS_BIGENDIAN
|
---|
917 | bswap = 1;
|
---|
918 | #else
|
---|
919 | bswap = 0;
|
---|
920 | #endif
|
---|
921 | switch(opc) {
|
---|
922 | case 0:
|
---|
923 | /* movb */
|
---|
924 | tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, 0);
|
---|
925 | break;
|
---|
926 | case 1:
|
---|
927 | if (bswap) {
|
---|
928 | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
|
---|
929 | tcg_out8(s, 0x66); /* rolw $8, %ecx */
|
---|
930 | tcg_out_modrm(s, 0xc1, 0, r1);
|
---|
931 | tcg_out8(s, 8);
|
---|
932 | data_reg = r1;
|
---|
933 | }
|
---|
934 | /* movw */
|
---|
935 | tcg_out8(s, 0x66);
|
---|
936 | tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
|
---|
937 | break;
|
---|
938 | case 2:
|
---|
939 | if (bswap) {
|
---|
940 | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
|
---|
941 | /* bswap data_reg */
|
---|
942 | tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
|
---|
943 | data_reg = r1;
|
---|
944 | }
|
---|
945 | /* movl */
|
---|
946 | tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
|
---|
947 | break;
|
---|
948 | case 3:
|
---|
949 | if (bswap) {
|
---|
950 | tcg_out_mov(s, r1, data_reg);
|
---|
951 | /* bswap data_reg */
|
---|
952 | tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
|
---|
953 | data_reg = r1;
|
---|
954 | }
|
---|
955 | /* movq */
|
---|
956 | tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
|
---|
957 | break;
|
---|
958 | default:
|
---|
959 | tcg_abort();
|
---|
960 | }
|
---|
961 | #else /* VBOX && REM_PHYS_ADDR_IN_TLB */
|
---|
962 | tcg_out_vbox_phys_write(s, opc, r0, data_reg);
|
---|
963 | #endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
|
---|
964 |
|
---|
965 | #if defined(CONFIG_SOFTMMU)
|
---|
966 | /* label2: */
|
---|
967 | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
---|
968 | #endif
|
---|
969 | }
|
---|
970 |
|
---|
971 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
|
---|
972 | const int *const_args)
|
---|
973 | {
|
---|
974 | int c;
|
---|
975 |
|
---|
976 | switch(opc) {
|
---|
977 | case INDEX_op_exit_tb:
|
---|
978 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
|
---|
979 | #ifndef VBOX
|
---|
980 | tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
|
---|
981 | tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
|
---|
982 | #else
|
---|
983 | tcg_out_long_jmp(s, (tcg_target_long)tb_ret_addr);
|
---|
984 | #endif
|
---|
985 | break;
|
---|
986 | case INDEX_op_goto_tb:
|
---|
987 | if (s->tb_jmp_offset) {
|
---|
988 | /* direct jump method */
|
---|
989 | tcg_out8(s, 0xe9); /* jmp im */
|
---|
990 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
---|
991 | tcg_out32(s, 0);
|
---|
992 | } else {
|
---|
993 | /* indirect jump method */
|
---|
994 | /* jmp Ev */
|
---|
995 | #ifndef VBOX
|
---|
996 | tcg_out_modrm_offset(s, 0xff, 4, -1,
|
---|
997 | (tcg_target_long)(s->tb_next +
|
---|
998 | args[0]));
|
---|
999 | #else
|
---|
1000 | /** @todo: can we clobber RAX here? */
|
---|
1001 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX,
|
---|
1002 | (tcg_target_long)&(s->tb_next[args[0]]));
|
---|
1003 | tcg_out8(s, 0xff); tcg_out8(s, 0x20 | TCG_REG_RAX); /* jmp *(%rax) */
|
---|
1004 | #endif
|
---|
1005 | }
|
---|
1006 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
---|
1007 | break;
|
---|
1008 | case INDEX_op_call:
|
---|
1009 | if (const_args[0]) {
|
---|
1010 | #ifndef VBOX
|
---|
1011 | tcg_out8(s, 0xe8);
|
---|
1012 | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
|
---|
1013 | #else
|
---|
1014 | tcg_out_long_call(s, args[0]);
|
---|
1015 | #endif
|
---|
1016 | } else {
|
---|
1017 | tcg_out_modrm(s, 0xff, 2, args[0]);
|
---|
1018 | }
|
---|
1019 | break;
|
---|
1020 | case INDEX_op_jmp:
|
---|
1021 | if (const_args[0]) {
|
---|
1022 | tcg_out8(s, 0xe9);
|
---|
1023 | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
|
---|
1024 | } else {
|
---|
1025 | tcg_out_modrm(s, 0xff, 4, args[0]);
|
---|
1026 | }
|
---|
1027 | break;
|
---|
1028 | case INDEX_op_br:
|
---|
1029 | tcg_out_jxx(s, JCC_JMP, args[0]);
|
---|
1030 | break;
|
---|
1031 | case INDEX_op_movi_i32:
|
---|
1032 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
|
---|
1033 | break;
|
---|
1034 | case INDEX_op_movi_i64:
|
---|
1035 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
|
---|
1036 | break;
|
---|
1037 | case INDEX_op_ld8u_i32:
|
---|
1038 | case INDEX_op_ld8u_i64:
|
---|
1039 | /* movzbl */
|
---|
1040 | tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
|
---|
1041 | break;
|
---|
1042 | case INDEX_op_ld8s_i32:
|
---|
1043 | /* movsbl */
|
---|
1044 | tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
|
---|
1045 | break;
|
---|
1046 | case INDEX_op_ld8s_i64:
|
---|
1047 | /* movsbq */
|
---|
1048 | tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
|
---|
1049 | break;
|
---|
1050 | case INDEX_op_ld16u_i32:
|
---|
1051 | case INDEX_op_ld16u_i64:
|
---|
1052 | /* movzwl */
|
---|
1053 | tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
|
---|
1054 | break;
|
---|
1055 | case INDEX_op_ld16s_i32:
|
---|
1056 | /* movswl */
|
---|
1057 | tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
|
---|
1058 | break;
|
---|
1059 | case INDEX_op_ld16s_i64:
|
---|
1060 | /* movswq */
|
---|
1061 | tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
|
---|
1062 | break;
|
---|
1063 | case INDEX_op_ld_i32:
|
---|
1064 | case INDEX_op_ld32u_i64:
|
---|
1065 | /* movl */
|
---|
1066 | tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
|
---|
1067 | break;
|
---|
1068 | case INDEX_op_ld32s_i64:
|
---|
1069 | /* movslq */
|
---|
1070 | tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
|
---|
1071 | break;
|
---|
1072 | case INDEX_op_ld_i64:
|
---|
1073 | /* movq */
|
---|
1074 | tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
|
---|
1075 | break;
|
---|
1076 |
|
---|
1077 | case INDEX_op_st8_i32:
|
---|
1078 | case INDEX_op_st8_i64:
|
---|
1079 | /* movb */
|
---|
1080 | tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
|
---|
1081 | break;
|
---|
1082 | case INDEX_op_st16_i32:
|
---|
1083 | case INDEX_op_st16_i64:
|
---|
1084 | /* movw */
|
---|
1085 | tcg_out8(s, 0x66);
|
---|
1086 | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
|
---|
1087 | break;
|
---|
1088 | case INDEX_op_st_i32:
|
---|
1089 | case INDEX_op_st32_i64:
|
---|
1090 | /* movl */
|
---|
1091 | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
|
---|
1092 | break;
|
---|
1093 | case INDEX_op_st_i64:
|
---|
1094 | /* movq */
|
---|
1095 | tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
|
---|
1096 | break;
|
---|
1097 |
|
---|
1098 | case INDEX_op_sub_i32:
|
---|
1099 | c = ARITH_SUB;
|
---|
1100 | goto gen_arith32;
|
---|
1101 | case INDEX_op_and_i32:
|
---|
1102 | c = ARITH_AND;
|
---|
1103 | goto gen_arith32;
|
---|
1104 | case INDEX_op_or_i32:
|
---|
1105 | c = ARITH_OR;
|
---|
1106 | goto gen_arith32;
|
---|
1107 | case INDEX_op_xor_i32:
|
---|
1108 | c = ARITH_XOR;
|
---|
1109 | goto gen_arith32;
|
---|
1110 | case INDEX_op_add_i32:
|
---|
1111 | c = ARITH_ADD;
|
---|
1112 | gen_arith32:
|
---|
1113 | if (const_args[2]) {
|
---|
1114 | tgen_arithi32(s, c, args[0], args[2]);
|
---|
1115 | } else {
|
---|
1116 | tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
|
---|
1117 | }
|
---|
1118 | break;
|
---|
1119 |
|
---|
1120 | case INDEX_op_sub_i64:
|
---|
1121 | c = ARITH_SUB;
|
---|
1122 | goto gen_arith64;
|
---|
1123 | case INDEX_op_and_i64:
|
---|
1124 | c = ARITH_AND;
|
---|
1125 | goto gen_arith64;
|
---|
1126 | case INDEX_op_or_i64:
|
---|
1127 | c = ARITH_OR;
|
---|
1128 | goto gen_arith64;
|
---|
1129 | case INDEX_op_xor_i64:
|
---|
1130 | c = ARITH_XOR;
|
---|
1131 | goto gen_arith64;
|
---|
1132 | case INDEX_op_add_i64:
|
---|
1133 | c = ARITH_ADD;
|
---|
1134 | gen_arith64:
|
---|
1135 | if (const_args[2]) {
|
---|
1136 | tgen_arithi64(s, c, args[0], args[2]);
|
---|
1137 | } else {
|
---|
1138 | tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
|
---|
1139 | }
|
---|
1140 | break;
|
---|
1141 |
|
---|
1142 | case INDEX_op_mul_i32:
|
---|
1143 | if (const_args[2]) {
|
---|
1144 | int32_t val;
|
---|
1145 | val = args[2];
|
---|
1146 | if (val == (int8_t)val) {
|
---|
1147 | tcg_out_modrm(s, 0x6b, args[0], args[0]);
|
---|
1148 | tcg_out8(s, val);
|
---|
1149 | } else {
|
---|
1150 | tcg_out_modrm(s, 0x69, args[0], args[0]);
|
---|
1151 | tcg_out32(s, val);
|
---|
1152 | }
|
---|
1153 | } else {
|
---|
1154 | tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
|
---|
1155 | }
|
---|
1156 | break;
|
---|
1157 | case INDEX_op_mul_i64:
|
---|
1158 | if (const_args[2]) {
|
---|
1159 | int32_t val;
|
---|
1160 | val = args[2];
|
---|
1161 | if (val == (int8_t)val) {
|
---|
1162 | tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
|
---|
1163 | tcg_out8(s, val);
|
---|
1164 | } else {
|
---|
1165 | tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
|
---|
1166 | tcg_out32(s, val);
|
---|
1167 | }
|
---|
1168 | } else {
|
---|
1169 | tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
|
---|
1170 | }
|
---|
1171 | break;
|
---|
1172 | case INDEX_op_div2_i32:
|
---|
1173 | tcg_out_modrm(s, 0xf7, 7, args[4]);
|
---|
1174 | break;
|
---|
1175 | case INDEX_op_divu2_i32:
|
---|
1176 | tcg_out_modrm(s, 0xf7, 6, args[4]);
|
---|
1177 | break;
|
---|
1178 | case INDEX_op_div2_i64:
|
---|
1179 | tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
|
---|
1180 | break;
|
---|
1181 | case INDEX_op_divu2_i64:
|
---|
1182 | tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
|
---|
1183 | break;
|
---|
1184 |
|
---|
1185 | case INDEX_op_shl_i32:
|
---|
1186 | c = SHIFT_SHL;
|
---|
1187 | gen_shift32:
|
---|
1188 | if (const_args[2]) {
|
---|
1189 | if (args[2] == 1) {
|
---|
1190 | tcg_out_modrm(s, 0xd1, c, args[0]);
|
---|
1191 | } else {
|
---|
1192 | tcg_out_modrm(s, 0xc1, c, args[0]);
|
---|
1193 | tcg_out8(s, args[2]);
|
---|
1194 | }
|
---|
1195 | } else {
|
---|
1196 | tcg_out_modrm(s, 0xd3, c, args[0]);
|
---|
1197 | }
|
---|
1198 | break;
|
---|
1199 | case INDEX_op_shr_i32:
|
---|
1200 | c = SHIFT_SHR;
|
---|
1201 | goto gen_shift32;
|
---|
1202 | case INDEX_op_sar_i32:
|
---|
1203 | c = SHIFT_SAR;
|
---|
1204 | goto gen_shift32;
|
---|
1205 | case INDEX_op_rotl_i32:
|
---|
1206 | c = SHIFT_ROL;
|
---|
1207 | goto gen_shift32;
|
---|
1208 | case INDEX_op_rotr_i32:
|
---|
1209 | c = SHIFT_ROR;
|
---|
1210 | goto gen_shift32;
|
---|
1211 |
|
---|
1212 | case INDEX_op_shl_i64:
|
---|
1213 | c = SHIFT_SHL;
|
---|
1214 | gen_shift64:
|
---|
1215 | if (const_args[2]) {
|
---|
1216 | if (args[2] == 1) {
|
---|
1217 | tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
|
---|
1218 | } else {
|
---|
1219 | tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
|
---|
1220 | tcg_out8(s, args[2]);
|
---|
1221 | }
|
---|
1222 | } else {
|
---|
1223 | tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
|
---|
1224 | }
|
---|
1225 | break;
|
---|
1226 | case INDEX_op_shr_i64:
|
---|
1227 | c = SHIFT_SHR;
|
---|
1228 | goto gen_shift64;
|
---|
1229 | case INDEX_op_sar_i64:
|
---|
1230 | c = SHIFT_SAR;
|
---|
1231 | goto gen_shift64;
|
---|
1232 | case INDEX_op_rotl_i64:
|
---|
1233 | c = SHIFT_ROL;
|
---|
1234 | goto gen_shift64;
|
---|
1235 | case INDEX_op_rotr_i64:
|
---|
1236 | c = SHIFT_ROR;
|
---|
1237 | goto gen_shift64;
|
---|
1238 |
|
---|
1239 | case INDEX_op_brcond_i32:
|
---|
1240 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
|
---|
1241 | args[3], 0);
|
---|
1242 | break;
|
---|
1243 | case INDEX_op_brcond_i64:
|
---|
1244 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
|
---|
1245 | args[3], P_REXW);
|
---|
1246 | break;
|
---|
1247 |
|
---|
1248 | case INDEX_op_bswap16_i32:
|
---|
1249 | case INDEX_op_bswap16_i64:
|
---|
1250 | tcg_out8(s, 0x66);
|
---|
1251 | tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
|
---|
1252 | tcg_out8(s, 8);
|
---|
1253 | break;
|
---|
1254 | case INDEX_op_bswap32_i32:
|
---|
1255 | case INDEX_op_bswap32_i64:
|
---|
1256 | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
|
---|
1257 | break;
|
---|
1258 | case INDEX_op_bswap64_i64:
|
---|
1259 | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
|
---|
1260 | break;
|
---|
1261 |
|
---|
1262 | case INDEX_op_neg_i32:
|
---|
1263 | tcg_out_modrm(s, 0xf7, 3, args[0]);
|
---|
1264 | break;
|
---|
1265 | case INDEX_op_neg_i64:
|
---|
1266 | tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
|
---|
1267 | break;
|
---|
1268 |
|
---|
1269 | case INDEX_op_not_i32:
|
---|
1270 | tcg_out_modrm(s, 0xf7, 2, args[0]);
|
---|
1271 | break;
|
---|
1272 | case INDEX_op_not_i64:
|
---|
1273 | tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
|
---|
1274 | break;
|
---|
1275 |
|
---|
1276 | case INDEX_op_ext8s_i32:
|
---|
1277 | tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
|
---|
1278 | break;
|
---|
1279 | case INDEX_op_ext16s_i32:
|
---|
1280 | tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
|
---|
1281 | break;
|
---|
1282 | case INDEX_op_ext8s_i64:
|
---|
1283 | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
|
---|
1284 | break;
|
---|
1285 | case INDEX_op_ext16s_i64:
|
---|
1286 | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
|
---|
1287 | break;
|
---|
1288 | case INDEX_op_ext32s_i64:
|
---|
1289 | tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
|
---|
1290 | break;
|
---|
1291 |
|
---|
1292 | case INDEX_op_qemu_ld8u:
|
---|
1293 | tcg_out_qemu_ld(s, args, 0);
|
---|
1294 | break;
|
---|
1295 | case INDEX_op_qemu_ld8s:
|
---|
1296 | tcg_out_qemu_ld(s, args, 0 | 4);
|
---|
1297 | break;
|
---|
1298 | case INDEX_op_qemu_ld16u:
|
---|
1299 | tcg_out_qemu_ld(s, args, 1);
|
---|
1300 | break;
|
---|
1301 | case INDEX_op_qemu_ld16s:
|
---|
1302 | tcg_out_qemu_ld(s, args, 1 | 4);
|
---|
1303 | break;
|
---|
1304 | case INDEX_op_qemu_ld32u:
|
---|
1305 | tcg_out_qemu_ld(s, args, 2);
|
---|
1306 | break;
|
---|
1307 | case INDEX_op_qemu_ld32s:
|
---|
1308 | tcg_out_qemu_ld(s, args, 2 | 4);
|
---|
1309 | break;
|
---|
1310 | case INDEX_op_qemu_ld64:
|
---|
1311 | tcg_out_qemu_ld(s, args, 3);
|
---|
1312 | break;
|
---|
1313 |
|
---|
1314 | case INDEX_op_qemu_st8:
|
---|
1315 | tcg_out_qemu_st(s, args, 0);
|
---|
1316 | break;
|
---|
1317 | case INDEX_op_qemu_st16:
|
---|
1318 | tcg_out_qemu_st(s, args, 1);
|
---|
1319 | break;
|
---|
1320 | case INDEX_op_qemu_st32:
|
---|
1321 | tcg_out_qemu_st(s, args, 2);
|
---|
1322 | break;
|
---|
1323 | case INDEX_op_qemu_st64:
|
---|
1324 | tcg_out_qemu_st(s, args, 3);
|
---|
1325 | break;
|
---|
1326 |
|
---|
1327 | default:
|
---|
1328 | tcg_abort();
|
---|
1329 | }
|
---|
1330 | }
|
---|
1331 |
|
---|
1332 | static int tcg_target_callee_save_regs[] = {
|
---|
1333 | TCG_REG_RBP,
|
---|
1334 | TCG_REG_RBX,
|
---|
1335 | TCG_REG_R12,
|
---|
1336 | TCG_REG_R13,
|
---|
1337 | /* TCG_REG_R14, */ /* currently used for the global env, so no
|
---|
1338 | need to save */
|
---|
1339 | TCG_REG_R15,
|
---|
1340 | };
|
---|
1341 |
|
---|
1342 | static inline void tcg_out_push(TCGContext *s, int reg)
|
---|
1343 | {
|
---|
1344 | tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
|
---|
1345 | }
|
---|
1346 |
|
---|
1347 | static inline void tcg_out_pop(TCGContext *s, int reg)
|
---|
1348 | {
|
---|
1349 | tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
|
---|
1350 | }
|
---|
1351 |
|
---|
1352 | /* Generate global QEMU prologue and epilogue code */
|
---|
1353 | void tcg_target_qemu_prologue(TCGContext *s)
|
---|
1354 | {
|
---|
1355 | int i, frame_size, push_size, stack_addend;
|
---|
1356 |
|
---|
1357 | /* TB prologue */
|
---|
1358 | /* save all callee saved registers */
|
---|
1359 | for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
|
---|
1360 | tcg_out_push(s, tcg_target_callee_save_regs[i]);
|
---|
1361 |
|
---|
1362 | }
|
---|
1363 | /* reserve some stack space */
|
---|
1364 | push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
|
---|
1365 | frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
|
---|
1366 | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
---|
1367 | ~(TCG_TARGET_STACK_ALIGN - 1);
|
---|
1368 | stack_addend = frame_size - push_size;
|
---|
1369 | tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
|
---|
1370 |
|
---|
1371 | tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
|
---|
1372 |
|
---|
1373 | /* TB epilogue */
|
---|
1374 | tb_ret_addr = s->code_ptr;
|
---|
1375 | tcg_out_addi(s, TCG_REG_RSP, stack_addend);
|
---|
1376 | for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
|
---|
1377 | tcg_out_pop(s, tcg_target_callee_save_regs[i]);
|
---|
1378 | }
|
---|
1379 | tcg_out8(s, 0xc3); /* ret */
|
---|
1380 | }
|
---|
1381 |
|
---|
1382 | static const TCGTargetOpDef x86_64_op_defs[] = {
|
---|
1383 | { INDEX_op_exit_tb, { } },
|
---|
1384 | { INDEX_op_goto_tb, { } },
|
---|
1385 | { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
|
---|
1386 | { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
|
---|
1387 | { INDEX_op_br, { } },
|
---|
1388 |
|
---|
1389 | { INDEX_op_mov_i32, { "r", "r" } },
|
---|
1390 | { INDEX_op_movi_i32, { "r" } },
|
---|
1391 | { INDEX_op_ld8u_i32, { "r", "r" } },
|
---|
1392 | { INDEX_op_ld8s_i32, { "r", "r" } },
|
---|
1393 | { INDEX_op_ld16u_i32, { "r", "r" } },
|
---|
1394 | { INDEX_op_ld16s_i32, { "r", "r" } },
|
---|
1395 | { INDEX_op_ld_i32, { "r", "r" } },
|
---|
1396 | { INDEX_op_st8_i32, { "r", "r" } },
|
---|
1397 | { INDEX_op_st16_i32, { "r", "r" } },
|
---|
1398 | { INDEX_op_st_i32, { "r", "r" } },
|
---|
1399 |
|
---|
1400 | { INDEX_op_add_i32, { "r", "0", "ri" } },
|
---|
1401 | { INDEX_op_mul_i32, { "r", "0", "ri" } },
|
---|
1402 | { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
|
---|
1403 | { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
|
---|
1404 | { INDEX_op_sub_i32, { "r", "0", "ri" } },
|
---|
1405 | { INDEX_op_and_i32, { "r", "0", "ri" } },
|
---|
1406 | { INDEX_op_or_i32, { "r", "0", "ri" } },
|
---|
1407 | { INDEX_op_xor_i32, { "r", "0", "ri" } },
|
---|
1408 |
|
---|
1409 | { INDEX_op_shl_i32, { "r", "0", "ci" } },
|
---|
1410 | { INDEX_op_shr_i32, { "r", "0", "ci" } },
|
---|
1411 | { INDEX_op_sar_i32, { "r", "0", "ci" } },
|
---|
1412 | { INDEX_op_rotl_i32, { "r", "0", "ci" } },
|
---|
1413 | { INDEX_op_rotr_i32, { "r", "0", "ci" } },
|
---|
1414 |
|
---|
1415 | { INDEX_op_brcond_i32, { "r", "ri" } },
|
---|
1416 |
|
---|
1417 | { INDEX_op_mov_i64, { "r", "r" } },
|
---|
1418 | { INDEX_op_movi_i64, { "r" } },
|
---|
1419 | { INDEX_op_ld8u_i64, { "r", "r" } },
|
---|
1420 | { INDEX_op_ld8s_i64, { "r", "r" } },
|
---|
1421 | { INDEX_op_ld16u_i64, { "r", "r" } },
|
---|
1422 | { INDEX_op_ld16s_i64, { "r", "r" } },
|
---|
1423 | { INDEX_op_ld32u_i64, { "r", "r" } },
|
---|
1424 | { INDEX_op_ld32s_i64, { "r", "r" } },
|
---|
1425 | { INDEX_op_ld_i64, { "r", "r" } },
|
---|
1426 | { INDEX_op_st8_i64, { "r", "r" } },
|
---|
1427 | { INDEX_op_st16_i64, { "r", "r" } },
|
---|
1428 | { INDEX_op_st32_i64, { "r", "r" } },
|
---|
1429 | { INDEX_op_st_i64, { "r", "r" } },
|
---|
1430 |
|
---|
1431 | { INDEX_op_add_i64, { "r", "0", "re" } },
|
---|
1432 | { INDEX_op_mul_i64, { "r", "0", "re" } },
|
---|
1433 | { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
|
---|
1434 | { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
|
---|
1435 | { INDEX_op_sub_i64, { "r", "0", "re" } },
|
---|
1436 | { INDEX_op_and_i64, { "r", "0", "reZ" } },
|
---|
1437 | { INDEX_op_or_i64, { "r", "0", "re" } },
|
---|
1438 | { INDEX_op_xor_i64, { "r", "0", "re" } },
|
---|
1439 |
|
---|
1440 | { INDEX_op_shl_i64, { "r", "0", "ci" } },
|
---|
1441 | { INDEX_op_shr_i64, { "r", "0", "ci" } },
|
---|
1442 | { INDEX_op_sar_i64, { "r", "0", "ci" } },
|
---|
1443 | { INDEX_op_rotl_i64, { "r", "0", "ci" } },
|
---|
1444 | { INDEX_op_rotr_i64, { "r", "0", "ci" } },
|
---|
1445 |
|
---|
1446 | { INDEX_op_brcond_i64, { "r", "re" } },
|
---|
1447 |
|
---|
1448 | { INDEX_op_bswap16_i32, { "r", "0" } },
|
---|
1449 | { INDEX_op_bswap16_i64, { "r", "0" } },
|
---|
1450 | { INDEX_op_bswap32_i32, { "r", "0" } },
|
---|
1451 | { INDEX_op_bswap32_i64, { "r", "0" } },
|
---|
1452 | { INDEX_op_bswap64_i64, { "r", "0" } },
|
---|
1453 |
|
---|
1454 | { INDEX_op_neg_i32, { "r", "0" } },
|
---|
1455 | { INDEX_op_neg_i64, { "r", "0" } },
|
---|
1456 |
|
---|
1457 | { INDEX_op_not_i32, { "r", "0" } },
|
---|
1458 | { INDEX_op_not_i64, { "r", "0" } },
|
---|
1459 |
|
---|
1460 | { INDEX_op_ext8s_i32, { "r", "r"} },
|
---|
1461 | { INDEX_op_ext16s_i32, { "r", "r"} },
|
---|
1462 | { INDEX_op_ext8s_i64, { "r", "r"} },
|
---|
1463 | { INDEX_op_ext16s_i64, { "r", "r"} },
|
---|
1464 | { INDEX_op_ext32s_i64, { "r", "r"} },
|
---|
1465 |
|
---|
1466 | { INDEX_op_qemu_ld8u, { "r", "L" } },
|
---|
1467 | { INDEX_op_qemu_ld8s, { "r", "L" } },
|
---|
1468 | { INDEX_op_qemu_ld16u, { "r", "L" } },
|
---|
1469 | { INDEX_op_qemu_ld16s, { "r", "L" } },
|
---|
1470 | { INDEX_op_qemu_ld32u, { "r", "L" } },
|
---|
1471 | { INDEX_op_qemu_ld32s, { "r", "L" } },
|
---|
1472 | { INDEX_op_qemu_ld64, { "r", "L" } },
|
---|
1473 |
|
---|
1474 | { INDEX_op_qemu_st8, { "L", "L" } },
|
---|
1475 | { INDEX_op_qemu_st16, { "L", "L" } },
|
---|
1476 | { INDEX_op_qemu_st32, { "L", "L" } },
|
---|
1477 | { INDEX_op_qemu_st64, { "L", "L", "L" } },
|
---|
1478 |
|
---|
1479 | { -1 },
|
---|
1480 | };
|
---|
1481 |
|
---|
1482 | void tcg_target_init(TCGContext *s)
|
---|
1483 | {
|
---|
1484 | /* fail safe */
|
---|
1485 | if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
|
---|
1486 | tcg_abort();
|
---|
1487 |
|
---|
1488 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
|
---|
1489 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
|
---|
1490 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
---|
1491 | (1 << TCG_REG_RDI) |
|
---|
1492 | (1 << TCG_REG_RSI) |
|
---|
1493 | (1 << TCG_REG_RDX) |
|
---|
1494 | (1 << TCG_REG_RCX) |
|
---|
1495 | (1 << TCG_REG_R8) |
|
---|
1496 | (1 << TCG_REG_R9) |
|
---|
1497 | (1 << TCG_REG_RAX) |
|
---|
1498 | (1 << TCG_REG_R10) |
|
---|
1499 | (1 << TCG_REG_R11));
|
---|
1500 |
|
---|
1501 | tcg_regset_clear(s->reserved_regs);
|
---|
1502 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
|
---|
1503 |
|
---|
1504 | tcg_add_target_add_op_defs(x86_64_op_defs);
|
---|
1505 | }
|
---|