test-i386.c@ 25722

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1	/*
2	* x86 CPU test
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	*/
20
21	/*
22	* Sun GPL Disclaimer: For the avoidance of doubt, except that if any license choice
23	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
24	* the General Public License version 2 (GPLv2) at this time for any software where
25	* a choice of GPL license versions is made available with the language indicating
26	* that GPLv2 or any later version may be used, or where a choice of which version
27	* of the GPL is applied is otherwise unspecified.
28	*/
29	#define _GNU_SOURCE
30	#include <stdlib.h>
31	#include <stdio.h>
32	#include <string.h>
33	#include <inttypes.h>
34	#include <math.h>
35	#include <signal.h>
36	#include <setjmp.h>
37	#include <errno.h>
38	#include <sys/ucontext.h>
39	#include <sys/mman.h>
40
41	#if !defined(__x86_64__)
42	#define TEST_VM86
43	#define TEST_SEGS
44	#endif
45	//#define LINUX_VM86_IOPL_FIX
46	//#define TEST_P4_FLAGS
47	#if defined(__x86_64__)
48	#define TEST_SSE
49	#define TEST_CMOV 1
50	#define TEST_FCOMI 1
51	#else
52	//#define TEST_SSE
53	#define TEST_CMOV 0
54	#define TEST_FCOMI 0
55	#endif
56
57	#if defined(__x86_64__)
58	#define FMT64X "%016lx"
59	#define FMTLX "%016lx"
60	#define X86_64_ONLY(x) x
61	#else
62	#define FMT64X "%016" PRIx64
63	#define FMTLX "%08lx"
64	#define X86_64_ONLY(x)
65	#endif
66
67	#ifdef TEST_VM86
68	#include <asm/vm86.h>
69	#endif
70
71	#define xglue(x, y) x ## y
72	#define glue(x, y) xglue(x, y)
73	#define stringify(s) tostring(s)
74	#define tostring(s) #s
75
76	#define CC_C 0x0001
77	#define CC_P 0x0004
78	#define CC_A 0x0010
79	#define CC_Z 0x0040
80	#define CC_S 0x0080
81	#define CC_O 0x0800
82
83	#define __init_call __attribute__ ((unused,__section__ ("initcall")))
84
85	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)
86
87	#if defined(__x86_64__)
88	static inline long i2l(long v)
89	{
90	return v \| ((v ^ 0xabcd) << 32);
91	}
92	#else
93	static inline long i2l(long v)
94	{
95	return v;
96	}
97	#endif
98
99	#define OP add
100	#include "test-i386.h"
101
102	#define OP sub
103	#include "test-i386.h"
104
105	#define OP xor
106	#include "test-i386.h"
107
108	#define OP and
109	#include "test-i386.h"
110
111	#define OP or
112	#include "test-i386.h"
113
114	#define OP cmp
115	#include "test-i386.h"
116
117	#define OP adc
118	#define OP_CC
119	#include "test-i386.h"
120
121	#define OP sbb
122	#define OP_CC
123	#include "test-i386.h"
124
125	#define OP inc
126	#define OP_CC
127	#define OP1
128	#include "test-i386.h"
129
130	#define OP dec
131	#define OP_CC
132	#define OP1
133	#include "test-i386.h"
134
135	#define OP neg
136	#define OP_CC
137	#define OP1
138	#include "test-i386.h"
139
140	#define OP not
141	#define OP_CC
142	#define OP1
143	#include "test-i386.h"
144
145	#undef CC_MASK
146	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O)
147
148	#define OP shl
149	#include "test-i386-shift.h"
150
151	#define OP shr
152	#include "test-i386-shift.h"
153
154	#define OP sar
155	#include "test-i386-shift.h"
156
157	#define OP rol
158	#include "test-i386-shift.h"
159
160	#define OP ror
161	#include "test-i386-shift.h"
162
163	#define OP rcr
164	#define OP_CC
165	#include "test-i386-shift.h"
166
167	#define OP rcl
168	#define OP_CC
169	#include "test-i386-shift.h"
170
171	#define OP shld
172	#define OP_SHIFTD
173	#define OP_NOBYTE
174	#include "test-i386-shift.h"
175
176	#define OP shrd
177	#define OP_SHIFTD
178	#define OP_NOBYTE
179	#include "test-i386-shift.h"
180
181	/* XXX: should be more precise ? */
182	#undef CC_MASK
183	#define CC_MASK (CC_C)
184
185	#define OP bt
186	#define OP_NOBYTE
187	#include "test-i386-shift.h"
188
189	#define OP bts
190	#define OP_NOBYTE
191	#include "test-i386-shift.h"
192
193	#define OP btr
194	#define OP_NOBYTE
195	#include "test-i386-shift.h"
196
197	#define OP btc
198	#define OP_NOBYTE
199	#include "test-i386-shift.h"
200
201	/* lea test (modrm support) */
202	#define TEST_LEAQ(STR)\
203	{\
204	asm("lea " STR ", %0"\
205	: "=r" (res)\
206	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
207	printf("lea %s = " FMTLX "\n", STR, res);\
208	}
209
210	#define TEST_LEA(STR)\
211	{\
212	asm("lea " STR ", %0"\
213	: "=r" (res)\
214	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
215	printf("lea %s = " FMTLX "\n", STR, res);\
216	}
217
218	#define TEST_LEA16(STR)\
219	{\
220	asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
221	: "=wq" (res)\
222	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
223	printf("lea %s = %08lx\n", STR, res);\
224	}
225
226
227	void test_lea(void)
228	{
229	long eax, ebx, ecx, edx, esi, edi, res;
230	eax = i2l(0x0001);
231	ebx = i2l(0x0002);
232	ecx = i2l(0x0004);
233	edx = i2l(0x0008);
234	esi = i2l(0x0010);
235	edi = i2l(0x0020);
236
237	TEST_LEA("0x4000");
238
239	TEST_LEA("(%%eax)");
240	TEST_LEA("(%%ebx)");
241	TEST_LEA("(%%ecx)");
242	TEST_LEA("(%%edx)");
243	TEST_LEA("(%%esi)");
244	TEST_LEA("(%%edi)");
245
246	TEST_LEA("0x40(%%eax)");
247	TEST_LEA("0x40(%%ebx)");
248	TEST_LEA("0x40(%%ecx)");
249	TEST_LEA("0x40(%%edx)");
250	TEST_LEA("0x40(%%esi)");
251	TEST_LEA("0x40(%%edi)");
252
253	TEST_LEA("0x4000(%%eax)");
254	TEST_LEA("0x4000(%%ebx)");
255	TEST_LEA("0x4000(%%ecx)");
256	TEST_LEA("0x4000(%%edx)");
257	TEST_LEA("0x4000(%%esi)");
258	TEST_LEA("0x4000(%%edi)");
259
260	TEST_LEA("(%%eax, %%ecx)");
261	TEST_LEA("(%%ebx, %%edx)");
262	TEST_LEA("(%%ecx, %%ecx)");
263	TEST_LEA("(%%edx, %%ecx)");
264	TEST_LEA("(%%esi, %%ecx)");
265	TEST_LEA("(%%edi, %%ecx)");
266
267	TEST_LEA("0x40(%%eax, %%ecx)");
268	TEST_LEA("0x4000(%%ebx, %%edx)");
269
270	TEST_LEA("(%%ecx, %%ecx, 2)");
271	TEST_LEA("(%%edx, %%ecx, 4)");
272	TEST_LEA("(%%esi, %%ecx, 8)");
273
274	TEST_LEA("(,%%eax, 2)");
275	TEST_LEA("(,%%ebx, 4)");
276	TEST_LEA("(,%%ecx, 8)");
277
278	TEST_LEA("0x40(,%%eax, 2)");
279	TEST_LEA("0x40(,%%ebx, 4)");
280	TEST_LEA("0x40(,%%ecx, 8)");
281
282
283	TEST_LEA("-10(%%ecx, %%ecx, 2)");
284	TEST_LEA("-10(%%edx, %%ecx, 4)");
285	TEST_LEA("-10(%%esi, %%ecx, 8)");
286
287	TEST_LEA("0x4000(%%ecx, %%ecx, 2)");
288	TEST_LEA("0x4000(%%edx, %%ecx, 4)");
289	TEST_LEA("0x4000(%%esi, %%ecx, 8)");
290
291	#if defined(__x86_64__)
292	TEST_LEAQ("0x4000");
293	TEST_LEAQ("0x4000(%%rip)");
294
295	TEST_LEAQ("(%%rax)");
296	TEST_LEAQ("(%%rbx)");
297	TEST_LEAQ("(%%rcx)");
298	TEST_LEAQ("(%%rdx)");
299	TEST_LEAQ("(%%rsi)");
300	TEST_LEAQ("(%%rdi)");
301
302	TEST_LEAQ("0x40(%%rax)");
303	TEST_LEAQ("0x40(%%rbx)");
304	TEST_LEAQ("0x40(%%rcx)");
305	TEST_LEAQ("0x40(%%rdx)");
306	TEST_LEAQ("0x40(%%rsi)");
307	TEST_LEAQ("0x40(%%rdi)");
308
309	TEST_LEAQ("0x4000(%%rax)");
310	TEST_LEAQ("0x4000(%%rbx)");
311	TEST_LEAQ("0x4000(%%rcx)");
312	TEST_LEAQ("0x4000(%%rdx)");
313	TEST_LEAQ("0x4000(%%rsi)");
314	TEST_LEAQ("0x4000(%%rdi)");
315
316	TEST_LEAQ("(%%rax, %%rcx)");
317	TEST_LEAQ("(%%rbx, %%rdx)");
318	TEST_LEAQ("(%%rcx, %%rcx)");
319	TEST_LEAQ("(%%rdx, %%rcx)");
320	TEST_LEAQ("(%%rsi, %%rcx)");
321	TEST_LEAQ("(%%rdi, %%rcx)");
322
323	TEST_LEAQ("0x40(%%rax, %%rcx)");
324	TEST_LEAQ("0x4000(%%rbx, %%rdx)");
325
326	TEST_LEAQ("(%%rcx, %%rcx, 2)");
327	TEST_LEAQ("(%%rdx, %%rcx, 4)");
328	TEST_LEAQ("(%%rsi, %%rcx, 8)");
329
330	TEST_LEAQ("(,%%rax, 2)");
331	TEST_LEAQ("(,%%rbx, 4)");
332	TEST_LEAQ("(,%%rcx, 8)");
333
334	TEST_LEAQ("0x40(,%%rax, 2)");
335	TEST_LEAQ("0x40(,%%rbx, 4)");
336	TEST_LEAQ("0x40(,%%rcx, 8)");
337
338
339	TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
340	TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
341	TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
342
343	TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
344	TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
345	TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
346	#else
347	/* limited 16 bit addressing test */
348	TEST_LEA16("0x4000");
349	TEST_LEA16("(%%bx)");
350	TEST_LEA16("(%%si)");
351	TEST_LEA16("(%%di)");
352	TEST_LEA16("0x40(%%bx)");
353	TEST_LEA16("0x40(%%si)");
354	TEST_LEA16("0x40(%%di)");
355	TEST_LEA16("0x4000(%%bx)");
356	TEST_LEA16("0x4000(%%si)");
357	TEST_LEA16("(%%bx,%%si)");
358	TEST_LEA16("(%%bx,%%di)");
359	TEST_LEA16("0x40(%%bx,%%si)");
360	TEST_LEA16("0x40(%%bx,%%di)");
361	TEST_LEA16("0x4000(%%bx,%%si)");
362	TEST_LEA16("0x4000(%%bx,%%di)");
363	#endif
364	}
365
366	#define TEST_JCC(JCC, v1, v2)\
367	{\
368	int res;\
369	asm("movl $1, %0\n\t"\
370	"cmpl %2, %1\n\t"\
371	"j" JCC " 1f\n\t"\
372	"movl $0, %0\n\t"\
373	"1:\n\t"\
374	: "=r" (res)\
375	: "r" (v1), "r" (v2));\
376	printf("%-10s %d\n", "j" JCC, res);\
377	\
378	asm("movl $0, %0\n\t"\
379	"cmpl %2, %1\n\t"\
380	"set" JCC " %b0\n\t"\
381	: "=r" (res)\
382	: "r" (v1), "r" (v2));\
383	printf("%-10s %d\n", "set" JCC, res);\
384	if (TEST_CMOV) {\
385	long val = i2l(1);\
386	long res = i2l(0x12345678);\
387	X86_64_ONLY(\
388	asm("cmpl %2, %1\n\t"\
389	"cmov" JCC "q %3, %0\n\t"\
390	: "=r" (res)\
391	: "r" (v1), "r" (v2), "m" (val), "0" (res));\
392	printf("%-10s R=" FMTLX "\n", "cmov" JCC "q", res);)\
393	asm("cmpl %2, %1\n\t"\
394	"cmov" JCC "l %k3, %k0\n\t"\
395	: "=r" (res)\
396	: "r" (v1), "r" (v2), "m" (val), "0" (res));\
397	printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
398	asm("cmpl %2, %1\n\t"\
399	"cmov" JCC "w %w3, %w0\n\t"\
400	: "=r" (res)\
401	: "r" (v1), "r" (v2), "r" (1), "0" (res));\
402	printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
403	} \
404	}
405
406	/* various jump tests */
407	void test_jcc(void)
408	{
409	TEST_JCC("ne", 1, 1);
410	TEST_JCC("ne", 1, 0);
411
412	TEST_JCC("e", 1, 1);
413	TEST_JCC("e", 1, 0);
414
415	TEST_JCC("l", 1, 1);
416	TEST_JCC("l", 1, 0);
417	TEST_JCC("l", 1, -1);
418
419	TEST_JCC("le", 1, 1);
420	TEST_JCC("le", 1, 0);
421	TEST_JCC("le", 1, -1);
422
423	TEST_JCC("ge", 1, 1);
424	TEST_JCC("ge", 1, 0);
425	TEST_JCC("ge", -1, 1);
426
427	TEST_JCC("g", 1, 1);
428	TEST_JCC("g", 1, 0);
429	TEST_JCC("g", 1, -1);
430
431	TEST_JCC("b", 1, 1);
432	TEST_JCC("b", 1, 0);
433	TEST_JCC("b", 1, -1);
434
435	TEST_JCC("be", 1, 1);
436	TEST_JCC("be", 1, 0);
437	TEST_JCC("be", 1, -1);
438
439	TEST_JCC("ae", 1, 1);
440	TEST_JCC("ae", 1, 0);
441	TEST_JCC("ae", 1, -1);
442
443	TEST_JCC("a", 1, 1);
444	TEST_JCC("a", 1, 0);
445	TEST_JCC("a", 1, -1);
446
447
448	TEST_JCC("p", 1, 1);
449	TEST_JCC("p", 1, 0);
450
451	TEST_JCC("np", 1, 1);
452	TEST_JCC("np", 1, 0);
453
454	TEST_JCC("o", 0x7fffffff, 0);
455	TEST_JCC("o", 0x7fffffff, -1);
456
457	TEST_JCC("no", 0x7fffffff, 0);
458	TEST_JCC("no", 0x7fffffff, -1);
459
460	TEST_JCC("s", 0, 1);
461	TEST_JCC("s", 0, -1);
462	TEST_JCC("s", 0, 0);
463
464	TEST_JCC("ns", 0, 1);
465	TEST_JCC("ns", 0, -1);
466	TEST_JCC("ns", 0, 0);
467	}
468
469	#undef CC_MASK
470	#ifdef TEST_P4_FLAGS
471	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)
472	#else
473	#define CC_MASK (CC_O \| CC_C)
474	#endif
475
476	#define OP mul
477	#include "test-i386-muldiv.h"
478
479	#define OP imul
480	#include "test-i386-muldiv.h"
481
482	void test_imulw2(long op0, long op1)
483	{
484	long res, s1, s0, flags;
485	s0 = op0;
486	s1 = op1;
487	res = s0;
488	flags = 0;
489	asm volatile ("push %4\n\t"
490	"popf\n\t"
491	"imulw %w2, %w0\n\t"
492	"pushf\n\t"
493	"pop %1\n\t"
494	: "=q" (res), "=g" (flags)
495	: "q" (s1), "0" (res), "1" (flags));
496	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
497	"imulw", s0, s1, res, flags & CC_MASK);
498	}
499
500	void test_imull2(long op0, long op1)
501	{
502	long res, s1, s0, flags;
503	s0 = op0;
504	s1 = op1;
505	res = s0;
506	flags = 0;
507	asm volatile ("push %4\n\t"
508	"popf\n\t"
509	"imull %k2, %k0\n\t"
510	"pushf\n\t"
511	"pop %1\n\t"
512	: "=q" (res), "=g" (flags)
513	: "q" (s1), "0" (res), "1" (flags));
514	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
515	"imull", s0, s1, res, flags & CC_MASK);
516	}
517
518	#if defined(__x86_64__)
519	void test_imulq2(long op0, long op1)
520	{
521	long res, s1, s0, flags;
522	s0 = op0;
523	s1 = op1;
524	res = s0;
525	flags = 0;
526	asm volatile ("push %4\n\t"
527	"popf\n\t"
528	"imulq %2, %0\n\t"
529	"pushf\n\t"
530	"pop %1\n\t"
531	: "=q" (res), "=g" (flags)
532	: "q" (s1), "0" (res), "1" (flags));
533	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
534	"imulq", s0, s1, res, flags & CC_MASK);
535	}
536	#endif
537
538	#define TEST_IMUL_IM(size, rsize, op0, op1)\
539	{\
540	long res, flags, s1;\
541	flags = 0;\
542	res = 0;\
543	s1 = op1;\
544	asm volatile ("push %3\n\t"\
545	"popf\n\t"\
546	"imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
547	"pushf\n\t"\
548	"pop %1\n\t"\
549	: "=r" (res), "=g" (flags)\
550	: "r" (s1), "1" (flags), "0" (res));\
551	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
552	"imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
553	}
554
555
556	#undef CC_MASK
557	#define CC_MASK (0)
558
559	#define OP div
560	#include "test-i386-muldiv.h"
561
562	#define OP idiv
563	#include "test-i386-muldiv.h"
564
565	void test_mul(void)
566	{
567	test_imulb(0x1234561d, 4);
568	test_imulb(3, -4);
569	test_imulb(0x80, 0x80);
570	test_imulb(0x10, 0x10);
571
572	test_imulw(0, 0x1234001d, 45);
573	test_imulw(0, 23, -45);
574	test_imulw(0, 0x8000, 0x8000);
575	test_imulw(0, 0x100, 0x100);
576
577	test_imull(0, 0x1234001d, 45);
578	test_imull(0, 23, -45);
579	test_imull(0, 0x80000000, 0x80000000);
580	test_imull(0, 0x10000, 0x10000);
581
582	test_mulb(0x1234561d, 4);
583	test_mulb(3, -4);
584	test_mulb(0x80, 0x80);
585	test_mulb(0x10, 0x10);
586
587	test_mulw(0, 0x1234001d, 45);
588	test_mulw(0, 23, -45);
589	test_mulw(0, 0x8000, 0x8000);
590	test_mulw(0, 0x100, 0x100);
591
592	test_mull(0, 0x1234001d, 45);
593	test_mull(0, 23, -45);
594	test_mull(0, 0x80000000, 0x80000000);
595	test_mull(0, 0x10000, 0x10000);
596
597	test_imulw2(0x1234001d, 45);
598	test_imulw2(23, -45);
599	test_imulw2(0x8000, 0x8000);
600	test_imulw2(0x100, 0x100);
601
602	test_imull2(0x1234001d, 45);
603	test_imull2(23, -45);
604	test_imull2(0x80000000, 0x80000000);
605	test_imull2(0x10000, 0x10000);
606
607	TEST_IMUL_IM("w", "w", 45, 0x1234);
608	TEST_IMUL_IM("w", "w", -45, 23);
609	TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
610	TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
611
612	TEST_IMUL_IM("l", "k", 45, 0x1234);
613	TEST_IMUL_IM("l", "k", -45, 23);
614	TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
615	TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
616
617	test_idivb(0x12341678, 0x127e);
618	test_idivb(0x43210123, -5);
619	test_idivb(0x12340004, -1);
620
621	test_idivw(0, 0x12345678, 12347);
622	test_idivw(0, -23223, -45);
623	test_idivw(0, 0x12348000, -1);
624	test_idivw(0x12343, 0x12345678, 0x81238567);
625
626	test_idivl(0, 0x12345678, 12347);
627	test_idivl(0, -233223, -45);
628	test_idivl(0, 0x80000000, -1);
629	test_idivl(0x12343, 0x12345678, 0x81234567);
630
631	test_divb(0x12341678, 0x127e);
632	test_divb(0x43210123, -5);
633	test_divb(0x12340004, -1);
634
635	test_divw(0, 0x12345678, 12347);
636	test_divw(0, -23223, -45);
637	test_divw(0, 0x12348000, -1);
638	test_divw(0x12343, 0x12345678, 0x81238567);
639
640	test_divl(0, 0x12345678, 12347);
641	test_divl(0, -233223, -45);
642	test_divl(0, 0x80000000, -1);
643	test_divl(0x12343, 0x12345678, 0x81234567);
644
645	#if defined(__x86_64__)
646	test_imulq(0, 0x1234001d1234001d, 45);
647	test_imulq(0, 23, -45);
648	test_imulq(0, 0x8000000000000000, 0x8000000000000000);
649	test_imulq(0, 0x100000000, 0x100000000);
650
651	test_mulq(0, 0x1234001d1234001d, 45);
652	test_mulq(0, 23, -45);
653	test_mulq(0, 0x8000000000000000, 0x8000000000000000);
654	test_mulq(0, 0x100000000, 0x100000000);
655
656	test_imulq2(0x1234001d1234001d, 45);
657	test_imulq2(23, -45);
658	test_imulq2(0x8000000000000000, 0x8000000000000000);
659	test_imulq2(0x100000000, 0x100000000);
660
661	TEST_IMUL_IM("q", "", 45, 0x12341234);
662	TEST_IMUL_IM("q", "", -45, 23);
663	TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
664	TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
665
666	test_idivq(0, 0x12345678abcdef, 12347);
667	test_idivq(0, -233223, -45);
668	test_idivq(0, 0x8000000000000000, -1);
669	test_idivq(0x12343, 0x12345678, 0x81234567);
670
671	test_divq(0, 0x12345678abcdef, 12347);
672	test_divq(0, -233223, -45);
673	test_divq(0, 0x8000000000000000, -1);
674	test_divq(0x12343, 0x12345678, 0x81234567);
675	#endif
676	}
677
678	#define TEST_BSX(op, size, op0)\
679	{\
680	long res, val, resz;\
681	val = op0;\
682	asm("xor %1, %1\n"\
683	"mov $0x12345678, %0\n"\
684	#op " %" size "2, %" size "0 ; setz %b1" \
685	: "=r" (res), "=q" (resz)\
686	: "g" (val));\
687	printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
688	}
689
690	void test_bsx(void)
691	{
692	TEST_BSX(bsrw, "w", 0);
693	TEST_BSX(bsrw, "w", 0x12340128);
694	TEST_BSX(bsfw, "w", 0);
695	TEST_BSX(bsfw, "w", 0x12340128);
696	TEST_BSX(bsrl, "k", 0);
697	TEST_BSX(bsrl, "k", 0x00340128);
698	TEST_BSX(bsfl, "k", 0);
699	TEST_BSX(bsfl, "k", 0x00340128);
700	#if defined(__x86_64__)
701	TEST_BSX(bsrq, "", 0);
702	TEST_BSX(bsrq, "", 0x003401281234);
703	TEST_BSX(bsfq, "", 0);
704	TEST_BSX(bsfq, "", 0x003401281234);
705	#endif
706	}
707
708	/**********************************************/
709
710	union float64u {
711	double d;
712	uint64_t l;
713	};
714
715	union float64u q_nan = { .l = 0xFFF8000000000000 };
716	union float64u s_nan = { .l = 0xFFF0000000000000 };
717
718	void test_fops(double a, double b)
719	{
720	printf("a=%f b=%f a+b=%f\n", a, b, a + b);
721	printf("a=%f b=%f a-b=%f\n", a, b, a - b);
722	printf("a=%f b=%f ab=%f\n", a, b, a b);
723	printf("a=%f b=%f a/b=%f\n", a, b, a / b);
724	printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
725	printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
726	printf("a=%f sin(a)=%f\n", a, sin(a));
727	printf("a=%f cos(a)=%f\n", a, cos(a));
728	printf("a=%f tan(a)=%f\n", a, tan(a));
729	printf("a=%f log(a)=%f\n", a, log(a));
730	printf("a=%f exp(a)=%f\n", a, exp(a));
731	printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
732	/* just to test some op combining */
733	printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
734	printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
735	printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
736
737	}
738
739	void fpu_clear_exceptions(void)
740	{
741	struct __attribute__((packed)) {
742	uint16_t fpuc;
743	uint16_t dummy1;
744	uint16_t fpus;
745	uint16_t dummy2;
746	uint16_t fptag;
747	uint16_t dummy3;
748	uint32_t ignored[4];
749	long double fpregs[8];
750	} float_env32;
751
752	asm volatile ("fnstenv %0\n" : : "m" (float_env32));
753	float_env32.fpus &= ~0x7f;
754	asm volatile ("fldenv %0\n" : : "m" (float_env32));
755	}
756
757	/* XXX: display exception bits when supported */
758	#define FPUS_EMASK 0x0000
759	//#define FPUS_EMASK 0x007f
760
761	void test_fcmp(double a, double b)
762	{
763	long eflags, fpus;
764
765	fpu_clear_exceptions();
766	asm("fcom %2\n"
767	"fstsw %%ax\n"
768	: "=a" (fpus)
769	: "t" (a), "u" (b));
770	printf("fcom(%f %f)=%04lx \n",
771	a, b, fpus & (0x4500 \| FPUS_EMASK));
772	fpu_clear_exceptions();
773	asm("fucom %2\n"
774	"fstsw %%ax\n"
775	: "=a" (fpus)
776	: "t" (a), "u" (b));
777	printf("fucom(%f %f)=%04lx\n",
778	a, b, fpus & (0x4500 \| FPUS_EMASK));
779	if (TEST_FCOMI) {
780	/* test f(u)comi instruction */
781	fpu_clear_exceptions();
782	asm("fcomi %3, %2\n"
783	"fstsw %%ax\n"
784	"pushf\n"
785	"pop %0\n"
786	: "=r" (eflags), "=a" (fpus)
787	: "t" (a), "u" (b));
788	printf("fcomi(%f %f)=%04lx %02lx\n",
789	a, b, fpus & FPUS_EMASK, eflags & (CC_Z \| CC_P \| CC_C));
790	fpu_clear_exceptions();
791	asm("fucomi %3, %2\n"
792	"fstsw %%ax\n"
793	"pushf\n"
794	"pop %0\n"
795	: "=r" (eflags), "=a" (fpus)
796	: "t" (a), "u" (b));
797	printf("fucomi(%f %f)=%04lx %02lx\n",
798	a, b, fpus & FPUS_EMASK, eflags & (CC_Z \| CC_P \| CC_C));
799	}
800	fpu_clear_exceptions();
801	asm volatile("fxam\n"
802	"fstsw %%ax\n"
803	: "=a" (fpus)
804	: "t" (a));
805	printf("fxam(%f)=%04lx\n", a, fpus & 0x4700);
806	fpu_clear_exceptions();
807	}
808
809	void test_fcvt(double a)
810	{
811	float fa;
812	long double la;
813	int16_t fpuc;
814	int i;
815	int64_t lla;
816	int ia;
817	int16_t wa;
818	double ra;
819
820	fa = a;
821	la = a;
822	printf("(float)%f = %f\n", a, fa);
823	printf("(long double)%f = %Lf\n", a, la);
824	printf("a=" FMT64X "\n", (uint64_t )&a);
825	printf("la=" FMT64X " %04x\n", (uint64_t )&la,
826	(unsigned short )((char *)(&la) + 8));
827
828	/* test all roundings */
829	asm volatile ("fstcw %0" : "=m" (fpuc));
830	for(i=0;i<4;i++) {
831	asm volatile ("fldcw %0" : : "m" ((fpuc & ~0x0c00) \| (i << 10)));
832	asm volatile ("fist %0" : "=m" (wa) : "t" (a));
833	asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
834	asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
835	asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
836	asm volatile ("fldcw %0" : : "m" (fpuc));
837	printf("(short)a = %d\n", wa);
838	printf("(int)a = %d\n", ia);
839	printf("(int64_t)a = " FMT64X "\n", lla);
840	printf("rint(a) = %f\n", ra);
841	}
842	}
843
844	#define TEST(N) \
845	asm("fld" #N : "=t" (a)); \
846	printf("fld" #N "= %f\n", a);
847
848	void test_fconst(void)
849	{
850	double a;
851	TEST(1);
852	TEST(l2t);
853	TEST(l2e);
854	TEST(pi);
855	TEST(lg2);
856	TEST(ln2);
857	TEST(z);
858	}
859
860	void test_fbcd(double a)
861	{
862	unsigned short bcd[5];
863	double b;
864
865	asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
866	asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
867	printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
868	a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
869	}
870
871	#define TEST_ENV(env, save, restore)\
872	{\
873	memset((env), 0xaa, sizeof(*(env)));\
874	for(i=0;i<5;i++)\
875	asm volatile ("fldl %0" : : "m" (dtab[i]));\
876	asm volatile (save " %0\n" : : "m" (*(env)));\
877	asm volatile (restore " %0\n": : "m" (*(env)));\
878	for(i=0;i<5;i++)\
879	asm volatile ("fstpl %0" : "=m" (rtab[i]));\
880	for(i=0;i<5;i++)\
881	printf("res[%d]=%f\n", i, rtab[i]);\
882	printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
883	(env)->fpuc,\
884	(env)->fpus & 0xff00,\
885	(env)->fptag);\
886	}
887
888	void test_fenv(void)
889	{
890	struct __attribute__((packed)) {
891	uint16_t fpuc;
892	uint16_t dummy1;
893	uint16_t fpus;
894	uint16_t dummy2;
895	uint16_t fptag;
896	uint16_t dummy3;
897	uint32_t ignored[4];
898	long double fpregs[8];
899	} float_env32;
900	struct __attribute__((packed)) {
901	uint16_t fpuc;
902	uint16_t fpus;
903	uint16_t fptag;
904	uint16_t ignored[4];
905	long double fpregs[8];
906	} float_env16;
907	double dtab[8];
908	double rtab[8];
909	int i;
910
911	for(i=0;i<8;i++)
912	dtab[i] = i + 1;
913
914	TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
915	TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
916	TEST_ENV(&float_env32, "fnstenv", "fldenv");
917	TEST_ENV(&float_env32, "fnsave", "frstor");
918
919	/* test for ffree */
920	for(i=0;i<5;i++)
921	asm volatile ("fldl %0" : : "m" (dtab[i]));
922	asm volatile("ffree %st(2)");
923	asm volatile ("fnstenv %0\n" : : "m" (float_env32));
924	asm volatile ("fninit");
925	printf("fptag=%04x\n", float_env32.fptag);
926	}
927
928
929	#define TEST_FCMOV(a, b, eflags, CC)\
930	{\
931	double res;\
932	asm("push %3\n"\
933	"popf\n"\
934	"fcmov" CC " %2, %0\n"\
935	: "=t" (res)\
936	: "0" (a), "u" (b), "g" (eflags));\
937	printf("fcmov%s eflags=0x%04lx-> %f\n", \
938	CC, (long)eflags, res);\
939	}
940
941	void test_fcmov(void)
942	{
943	double a, b;
944	long eflags, i;
945
946	a = 1.0;
947	b = 2.0;
948	for(i = 0; i < 4; i++) {
949	eflags = 0;
950	if (i & 1)
951	eflags \|= CC_C;
952	if (i & 2)
953	eflags \|= CC_Z;
954	TEST_FCMOV(a, b, eflags, "b");
955	TEST_FCMOV(a, b, eflags, "e");
956	TEST_FCMOV(a, b, eflags, "be");
957	TEST_FCMOV(a, b, eflags, "nb");
958	TEST_FCMOV(a, b, eflags, "ne");
959	TEST_FCMOV(a, b, eflags, "nbe");
960	}
961	TEST_FCMOV(a, b, 0, "u");
962	TEST_FCMOV(a, b, CC_P, "u");
963	TEST_FCMOV(a, b, 0, "nu");
964	TEST_FCMOV(a, b, CC_P, "nu");
965	}
966
967	void test_floats(void)
968	{
969	test_fops(2, 3);
970	test_fops(1.4, -5);
971	test_fcmp(2, -1);
972	test_fcmp(2, 2);
973	test_fcmp(2, 3);
974	test_fcmp(2, q_nan.d);
975	test_fcmp(q_nan.d, -1);
976	test_fcmp(-1.0/0.0, -1);
977	test_fcmp(1.0/0.0, -1);
978	test_fcvt(0.5);
979	test_fcvt(-0.5);
980	test_fcvt(1.0/7.0);
981	test_fcvt(-1.0/9.0);
982	test_fcvt(32768);
983	test_fcvt(-1e20);
984	test_fcvt(-1.0/0.0);
985	test_fcvt(1.0/0.0);
986	test_fcvt(q_nan.d);
987	test_fconst();
988	test_fbcd(1234567890123456);
989	test_fbcd(-123451234567890);
990	test_fenv();
991	if (TEST_CMOV) {
992	test_fcmov();
993	}
994	}
995
996	/**********************************************/
997	#if !defined(__x86_64__)
998
999	#define TEST_BCD(op, op0, cc_in, cc_mask)\
1000	{\
1001	int res, flags;\
1002	res = op0;\
1003	flags = cc_in;\
1004	asm ("push %3\n\t"\
1005	"popf\n\t"\
1006	#op "\n\t"\
1007	"pushf\n\t"\
1008	"pop %1\n\t"\
1009	: "=a" (res), "=g" (flags)\
1010	: "0" (res), "1" (flags));\
1011	printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",\
1012	#op, op0, res, cc_in, flags & cc_mask);\
1013	}
1014
1015	void test_bcd(void)
1016	{
1017	TEST_BCD(daa, 0x12340503, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1018	TEST_BCD(daa, 0x12340506, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1019	TEST_BCD(daa, 0x12340507, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1020	TEST_BCD(daa, 0x12340559, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1021	TEST_BCD(daa, 0x12340560, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1022	TEST_BCD(daa, 0x1234059f, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1023	TEST_BCD(daa, 0x123405a0, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1024	TEST_BCD(daa, 0x12340503, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1025	TEST_BCD(daa, 0x12340506, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1026	TEST_BCD(daa, 0x12340503, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1027	TEST_BCD(daa, 0x12340506, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1028	TEST_BCD(daa, 0x12340503, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1029	TEST_BCD(daa, 0x12340506, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1030
1031	TEST_BCD(das, 0x12340503, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1032	TEST_BCD(das, 0x12340506, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1033	TEST_BCD(das, 0x12340507, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1034	TEST_BCD(das, 0x12340559, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1035	TEST_BCD(das, 0x12340560, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1036	TEST_BCD(das, 0x1234059f, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1037	TEST_BCD(das, 0x123405a0, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1038	TEST_BCD(das, 0x12340503, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1039	TEST_BCD(das, 0x12340506, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1040	TEST_BCD(das, 0x12340503, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1041	TEST_BCD(das, 0x12340506, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1042	TEST_BCD(das, 0x12340503, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1043	TEST_BCD(das, 0x12340506, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1044
1045	TEST_BCD(aaa, 0x12340205, CC_A, (CC_C \| CC_A));
1046	TEST_BCD(aaa, 0x12340306, CC_A, (CC_C \| CC_A));
1047	TEST_BCD(aaa, 0x1234040a, CC_A, (CC_C \| CC_A));
1048	TEST_BCD(aaa, 0x123405fa, CC_A, (CC_C \| CC_A));
1049	TEST_BCD(aaa, 0x12340205, 0, (CC_C \| CC_A));
1050	TEST_BCD(aaa, 0x12340306, 0, (CC_C \| CC_A));
1051	TEST_BCD(aaa, 0x1234040a, 0, (CC_C \| CC_A));
1052	TEST_BCD(aaa, 0x123405fa, 0, (CC_C \| CC_A));
1053
1054	TEST_BCD(aas, 0x12340205, CC_A, (CC_C \| CC_A));
1055	TEST_BCD(aas, 0x12340306, CC_A, (CC_C \| CC_A));
1056	TEST_BCD(aas, 0x1234040a, CC_A, (CC_C \| CC_A));
1057	TEST_BCD(aas, 0x123405fa, CC_A, (CC_C \| CC_A));
1058	TEST_BCD(aas, 0x12340205, 0, (CC_C \| CC_A));
1059	TEST_BCD(aas, 0x12340306, 0, (CC_C \| CC_A));
1060	TEST_BCD(aas, 0x1234040a, 0, (CC_C \| CC_A));
1061	TEST_BCD(aas, 0x123405fa, 0, (CC_C \| CC_A));
1062
1063	TEST_BCD(aam, 0x12340547, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));
1064	TEST_BCD(aad, 0x12340407, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));
1065	}
1066	#endif
1067
1068	#define TEST_XCHG(op, size, opconst)\
1069	{\
1070	long op0, op1;\
1071	op0 = i2l(0x12345678);\
1072	op1 = i2l(0xfbca7654);\
1073	asm(#op " %" size "0, %" size "1" \
1074	: "=q" (op0), opconst (op1) \
1075	: "0" (op0), "1" (op1));\
1076	printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
1077	#op, op0, op1);\
1078	}
1079
1080	#define TEST_CMPXCHG(op, size, opconst, eax)\
1081	{\
1082	long op0, op1, op2;\
1083	op0 = i2l(0x12345678);\
1084	op1 = i2l(0xfbca7654);\
1085	op2 = i2l(eax);\
1086	asm(#op " %" size "0, %" size "1" \
1087	: "=q" (op0), opconst (op1) \
1088	: "0" (op0), "1" (op1), "a" (op2));\
1089	printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
1090	#op, op2, op0, op1);\
1091	}
1092
1093	void test_xchg(void)
1094	{
1095	#if defined(__x86_64__)
1096	TEST_XCHG(xchgq, "", "=q");
1097	#endif
1098	TEST_XCHG(xchgl, "k", "=q");
1099	TEST_XCHG(xchgw, "w", "=q");
1100	TEST_XCHG(xchgb, "b", "=q");
1101
1102	#if defined(__x86_64__)
1103	TEST_XCHG(xchgq, "", "=m");
1104	#endif
1105	TEST_XCHG(xchgl, "k", "=m");
1106	TEST_XCHG(xchgw, "w", "=m");
1107	TEST_XCHG(xchgb, "b", "=m");
1108
1109	#if defined(__x86_64__)
1110	TEST_XCHG(xaddq, "", "=q");
1111	#endif
1112	TEST_XCHG(xaddl, "k", "=q");
1113	TEST_XCHG(xaddw, "w", "=q");
1114	TEST_XCHG(xaddb, "b", "=q");
1115
1116	{
1117	int res;
1118	res = 0x12345678;
1119	asm("xaddl %1, %0" : "=r" (res) : "0" (res));
1120	printf("xaddl same res=%08x\n", res);
1121	}
1122
1123	#if defined(__x86_64__)
1124	TEST_XCHG(xaddq, "", "=m");
1125	#endif
1126	TEST_XCHG(xaddl, "k", "=m");
1127	TEST_XCHG(xaddw, "w", "=m");
1128	TEST_XCHG(xaddb, "b", "=m");
1129
1130	#if defined(__x86_64__)
1131	TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfbca7654);
1132	#endif
1133	TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfbca7654);
1134	TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfbca7654);
1135	TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfbca7654);
1136
1137	#if defined(__x86_64__)
1138	TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfffefdfc);
1139	#endif
1140	TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfffefdfc);
1141	TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfffefdfc);
1142	TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfffefdfc);
1143
1144	#if defined(__x86_64__)
1145	TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfbca7654);
1146	#endif
1147	TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfbca7654);
1148	TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfbca7654);
1149	TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfbca7654);
1150
1151	#if defined(__x86_64__)
1152	TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfffefdfc);
1153	#endif
1154	TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfffefdfc);
1155	TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfffefdfc);
1156	TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfffefdfc);
1157
1158	{
1159	uint64_t op0, op1, op2;
1160	long i, eflags;
1161
1162	for(i = 0; i < 2; i++) {
1163	op0 = 0x123456789abcd;
1164	if (i == 0)
1165	op1 = 0xfbca765423456;
1166	else
1167	op1 = op0;
1168	op2 = 0x6532432432434;
1169	asm("cmpxchg8b %1\n"
1170	"pushf\n"
1171	"pop %2\n"
1172	: "=A" (op0), "=m" (op1), "=g" (eflags)
1173	: "0" (op0), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
1174	printf("cmpxchg8b: op0=" FMT64X " op1=" FMT64X " CC=%02lx\n",
1175	op0, op1, eflags & CC_Z);
1176	}
1177	}
1178	}
1179
1180	#ifdef TEST_SEGS
1181	/**********************************************/
1182	/* segmentation tests */
1183
1184	#include <asm/ldt.h>
1185	#include <linux/unistd.h>
1186	#include <linux/version.h>
1187
1188	_syscall3(int, modify_ldt, int, func, void *, ptr, unsigned long, bytecount)
1189
1190	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
1191	#define modify_ldt_ldt_s user_desc
1192	#endif
1193
1194	#define MK_SEL(n) (((n) << 3) \| 7)
1195
1196	uint8_t seg_data1[4096];
1197	uint8_t seg_data2[4096];
1198
1199	#define TEST_LR(op, size, seg, mask)\
1200	{\
1201	int res, res2;\
1202	res = 0x12345678;\
1203	asm (op " %" size "2, %" size "0\n" \
1204	"movl $0, %1\n"\
1205	"jnz 1f\n"\
1206	"movl $1, %1\n"\
1207	"1:\n"\
1208	: "=r" (res), "=r" (res2) : "m" (seg), "0" (res));\
1209	printf(op ": Z=%d %08x\n", res2, res & ~(mask));\
1210	}
1211
1212	/* NOTE: we use Linux modify_ldt syscall */
1213	void test_segs(void)
1214	{
1215	struct modify_ldt_ldt_s ldt;
1216	long long ldt_table[3];
1217	int res, res2;
1218	char tmp;
1219	struct {
1220	uint32_t offset;
1221	uint16_t seg;
1222	} __attribute__((packed)) segoff;
1223
1224	ldt.entry_number = 1;
1225	ldt.base_addr = (unsigned long)&seg_data1;
1226	ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1227	ldt.seg_32bit = 1;
1228	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1229	ldt.read_exec_only = 0;
1230	ldt.limit_in_pages = 1;
1231	ldt.seg_not_present = 0;
1232	ldt.useable = 1;
1233	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1234
1235	ldt.entry_number = 2;
1236	ldt.base_addr = (unsigned long)&seg_data2;
1237	ldt.limit = (sizeof(seg_data2) + 0xfff) >> 12;
1238	ldt.seg_32bit = 1;
1239	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1240	ldt.read_exec_only = 0;
1241	ldt.limit_in_pages = 1;
1242	ldt.seg_not_present = 0;
1243	ldt.useable = 1;
1244	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1245
1246	modify_ldt(0, &ldt_table, sizeof(ldt_table)); /* read ldt entries */
1247	#if 0
1248	{
1249	int i;
1250	for(i=0;i<3;i++)
1251	printf("%d: %016Lx\n", i, ldt_table[i]);
1252	}
1253	#endif
1254	/* do some tests with fs or gs */
1255	asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1256
1257	seg_data1[1] = 0xaa;
1258	seg_data2[1] = 0x55;
1259
1260	asm volatile ("fs movzbl 0x1, %0" : "=r" (res));
1261	printf("FS[1] = %02x\n", res);
1262
1263	asm volatile ("pushl %%gs\n"
1264	"movl %1, %%gs\n"
1265	"gs movzbl 0x1, %0\n"
1266	"popl %%gs\n"
1267	: "=r" (res)
1268	: "r" (MK_SEL(2)));
1269	printf("GS[1] = %02x\n", res);
1270
1271	/* tests with ds/ss (implicit segment case) */
1272	tmp = 0xa5;
1273	asm volatile ("pushl %%ebp\n\t"
1274	"pushl %%ds\n\t"
1275	"movl %2, %%ds\n\t"
1276	"movl %3, %%ebp\n\t"
1277	"movzbl 0x1, %0\n\t"
1278	"movzbl (%%ebp), %1\n\t"
1279	"popl %%ds\n\t"
1280	"popl %%ebp\n\t"
1281	: "=r" (res), "=r" (res2)
1282	: "r" (MK_SEL(1)), "r" (&tmp));
1283	printf("DS[1] = %02x\n", res);
1284	printf("SS[tmp] = %02x\n", res2);
1285
1286	segoff.seg = MK_SEL(2);
1287	segoff.offset = 0xabcdef12;
1288	asm volatile("lfs %2, %0\n\t"
1289	"movl %%fs, %1\n\t"
1290	: "=r" (res), "=g" (res2)
1291	: "m" (segoff));
1292	printf("FS:reg = %04x:%08x\n", res2, res);
1293
1294	TEST_LR("larw", "w", MK_SEL(2), 0x0100);
1295	TEST_LR("larl", "", MK_SEL(2), 0x0100);
1296	TEST_LR("lslw", "w", MK_SEL(2), 0);
1297	TEST_LR("lsll", "", MK_SEL(2), 0);
1298
1299	TEST_LR("larw", "w", 0xfff8, 0);
1300	TEST_LR("larl", "", 0xfff8, 0);
1301	TEST_LR("lslw", "w", 0xfff8, 0);
1302	TEST_LR("lsll", "", 0xfff8, 0);
1303	}
1304
1305	/* 16 bit code test */
1306	extern char code16_start, code16_end;
1307	extern char code16_func1;
1308	extern char code16_func2;
1309	extern char code16_func3;
1310
1311	void test_code16(void)
1312	{
1313	struct modify_ldt_ldt_s ldt;
1314	int res, res2;
1315
1316	/* build a code segment */
1317	ldt.entry_number = 1;
1318	ldt.base_addr = (unsigned long)&code16_start;
1319	ldt.limit = &code16_end - &code16_start;
1320	ldt.seg_32bit = 0;
1321	ldt.contents = MODIFY_LDT_CONTENTS_CODE;
1322	ldt.read_exec_only = 0;
1323	ldt.limit_in_pages = 0;
1324	ldt.seg_not_present = 0;
1325	ldt.useable = 1;
1326	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1327
1328	/* call the first function */
1329	asm volatile ("lcall %1, %2"
1330	: "=a" (res)
1331	: "i" (MK_SEL(1)), "i" (&code16_func1): "memory", "cc");
1332	printf("func1() = 0x%08x\n", res);
1333	asm volatile ("lcall %2, %3"
1334	: "=a" (res), "=c" (res2)
1335	: "i" (MK_SEL(1)), "i" (&code16_func2): "memory", "cc");
1336	printf("func2() = 0x%08x spdec=%d\n", res, res2);
1337	asm volatile ("lcall %1, %2"
1338	: "=a" (res)
1339	: "i" (MK_SEL(1)), "i" (&code16_func3): "memory", "cc");
1340	printf("func3() = 0x%08x\n", res);
1341	}
1342	#endif
1343
1344	#if defined(__x86_64__)
1345	asm(".globl func_lret\n"
1346	"func_lret:\n"
1347	"movl $0x87654641, %eax\n"
1348	"lretq\n");
1349	#else
1350	asm(".globl func_lret\n"
1351	"func_lret:\n"
1352	"movl $0x87654321, %eax\n"
1353	"lret\n"
1354
1355	".globl func_iret\n"
1356	"func_iret:\n"
1357	"movl $0xabcd4321, %eax\n"
1358	"iret\n");
1359	#endif
1360
1361	extern char func_lret;
1362	extern char func_iret;
1363
1364	void test_misc(void)
1365	{
1366	char table[256];
1367	long res, i;
1368
1369	for(i=0;i<256;i++) table[i] = 256 - i;
1370	res = 0x12345678;
1371	asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
1372	printf("xlat: EAX=" FMTLX "\n", res);
1373
1374	#if defined(__x86_64__)
1375	{
1376	static struct __attribute__((packed)) {
1377	uint32_t offset;
1378	uint16_t seg;
1379	} desc;
1380	long cs_sel;
1381
1382	asm volatile ("mov %%cs, %0" : "=r" (cs_sel));
1383
1384	asm volatile ("push %1\n"
1385	"call func_lret\n"
1386	: "=a" (res)
1387	: "r" (cs_sel) : "memory", "cc");
1388	printf("func_lret=" FMTLX "\n", res);
1389
1390	/* NOTE: we assume that &func_lret < 4GB */
1391	desc.offset = (long)&func_lret;
1392	desc.seg = cs_sel;
1393
1394	asm volatile ("xor %%rax, %%rax\n"
1395	"rex64 lcall %1\n"
1396	: "=a" (res)
1397	: "m" (desc)
1398	: "memory", "cc");
1399	printf("func_lret2=" FMTLX "\n", res);
1400
1401	asm volatile ("push %2\n"
1402	"mov $ 1f, %%rax\n"
1403	"push %%rax\n"
1404	"ljmp %1\n"
1405	"1:\n"
1406	: "=a" (res)
1407	: "m" (desc), "b" (cs_sel)
1408	: "memory", "cc");
1409	printf("func_lret3=" FMTLX "\n", res);
1410	}
1411	#else
1412	asm volatile ("push %%cs ; call %1"
1413	: "=a" (res)
1414	: "m" (func_lret): "memory", "cc");
1415	printf("func_lret=" FMTLX "\n", res);
1416
1417	asm volatile ("pushf ; push %%cs ; call %1"
1418	: "=a" (res)
1419	: "m" (func_iret): "memory", "cc");
1420	printf("func_iret=" FMTLX "\n", res);
1421	#endif
1422
1423	#if defined(__x86_64__)
1424	/* specific popl test */
1425	asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
1426	: "=g" (res));
1427	printf("popl esp=" FMTLX "\n", res);
1428	#else
1429	/* specific popl test */
1430	asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
1431	: "=g" (res));
1432	printf("popl esp=" FMTLX "\n", res);
1433
1434	/* specific popw test */
1435	asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
1436	: "=g" (res));
1437	printf("popw esp=" FMTLX "\n", res);
1438	#endif
1439	}
1440
1441	uint8_t str_buffer[4096];
1442
1443	#define TEST_STRING1(OP, size, DF, REP)\
1444	{\
1445	long esi, edi, eax, ecx, eflags;\
1446	\
1447	esi = (long)(str_buffer + sizeof(str_buffer) / 2);\
1448	edi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
1449	eax = i2l(0x12345678);\
1450	ecx = 17;\
1451	\
1452	asm volatile ("push $0\n\t"\
1453	"popf\n\t"\
1454	DF "\n\t"\
1455	REP #OP size "\n\t"\
1456	"cld\n\t"\
1457	"pushf\n\t"\
1458	"pop %4\n\t"\
1459	: "=S" (esi), "=D" (edi), "=a" (eax), "=c" (ecx), "=g" (eflags)\
1460	: "0" (esi), "1" (edi), "2" (eax), "3" (ecx));\
1461	printf("%-10s ESI=" FMTLX " EDI=" FMTLX " EAX=" FMTLX " ECX=" FMTLX " EFL=%04x\n",\
1462	REP #OP size, esi, edi, eax, ecx,\
1463	(int)(eflags & (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)));\
1464	}
1465
1466	#define TEST_STRING(OP, REP)\
1467	TEST_STRING1(OP, "b", "", REP);\
1468	TEST_STRING1(OP, "w", "", REP);\
1469	TEST_STRING1(OP, "l", "", REP);\
1470	X86_64_ONLY(TEST_STRING1(OP, "q", "", REP));\
1471	TEST_STRING1(OP, "b", "std", REP);\
1472	TEST_STRING1(OP, "w", "std", REP);\
1473	TEST_STRING1(OP, "l", "std", REP);\
1474	X86_64_ONLY(TEST_STRING1(OP, "q", "std", REP))
1475
1476	void test_string(void)
1477	{
1478	int i;
1479	for(i = 0;i < sizeof(str_buffer); i++)
1480	str_buffer[i] = i + 0x56;
1481	TEST_STRING(stos, "");
1482	TEST_STRING(stos, "rep ");
1483	TEST_STRING(lods, ""); /* to verify stos */
1484	TEST_STRING(lods, "rep ");
1485	TEST_STRING(movs, "");
1486	TEST_STRING(movs, "rep ");
1487	TEST_STRING(lods, ""); /* to verify stos */
1488
1489	/* XXX: better tests */
1490	TEST_STRING(scas, "");
1491	TEST_STRING(scas, "repz ");
1492	TEST_STRING(scas, "repnz ");
1493	TEST_STRING(cmps, "");
1494	TEST_STRING(cmps, "repz ");
1495	TEST_STRING(cmps, "repnz ");
1496	}
1497
1498	#ifdef TEST_VM86
1499	/* VM86 test */
1500
1501	static inline void set_bit(uint8_t *a, unsigned int bit)
1502	{
1503	a[bit / 8] \|= (1 << (bit % 8));
1504	}
1505
1506	static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg)
1507	{
1508	return (uint8_t *)((seg << 4) + (reg & 0xffff));
1509	}
1510
1511	static inline void pushw(struct vm86_regs *r, int val)
1512	{
1513	r->esp = (r->esp & ~0xffff) \| ((r->esp - 2) & 0xffff);
1514	(uint16_t )seg_to_linear(r->ss, r->esp) = val;
1515	}
1516
1517	#undef __syscall_return
1518	#define __syscall_return(type, res) \
1519	do { \
1520	return (type) (res); \
1521	} while (0)
1522
1523	_syscall2(int, vm86, int, func, struct vm86plus_struct *, v86)
1524
1525	extern char vm86_code_start;
1526	extern char vm86_code_end;
1527
1528	#define VM86_CODE_CS 0x100
1529	#define VM86_CODE_IP 0x100
1530
1531	void test_vm86(void)
1532	{
1533	struct vm86plus_struct ctx;
1534	struct vm86_regs *r;
1535	uint8_t *vm86_mem;
1536	int seg, ret;
1537
1538	vm86_mem = mmap((void *)0x00000000, 0x110000,
1539	PROT_WRITE \| PROT_READ \| PROT_EXEC,
1540	MAP_FIXED \| MAP_ANON \| MAP_PRIVATE, -1, 0);
1541	if (vm86_mem == MAP_FAILED) {
1542	printf("ERROR: could not map vm86 memory");
1543	return;
1544	}
1545	memset(&ctx, 0, sizeof(ctx));
1546
1547	/* init basic registers */
1548	r = &ctx.regs;
1549	r->eip = VM86_CODE_IP;
1550	r->esp = 0xfffe;
1551	seg = VM86_CODE_CS;
1552	r->cs = seg;
1553	r->ss = seg;
1554	r->ds = seg;
1555	r->es = seg;
1556	r->fs = seg;
1557	r->gs = seg;
1558	r->eflags = VIF_MASK;
1559
1560	/* move code to proper address. We use the same layout as a .com
1561	dos program. */
1562	memcpy(vm86_mem + (VM86_CODE_CS << 4) + VM86_CODE_IP,
1563	&vm86_code_start, &vm86_code_end - &vm86_code_start);
1564
1565	/* mark int 0x21 as being emulated */
1566	set_bit((uint8_t *)&ctx.int_revectored, 0x21);
1567
1568	for(;;) {
1569	ret = vm86(VM86_ENTER, &ctx);
1570	switch(VM86_TYPE(ret)) {
1571	case VM86_INTx:
1572	{
1573	int int_num, ah, v;
1574
1575	int_num = VM86_ARG(ret);
1576	if (int_num != 0x21)
1577	goto unknown_int;
1578	ah = (r->eax >> 8) & 0xff;
1579	switch(ah) {
1580	case 0x00: /* exit */
1581	goto the_end;
1582	case 0x02: /* write char */
1583	{
1584	uint8_t c = r->edx;
1585	putchar(c);
1586	}
1587	break;
1588	case 0x09: /* write string */
1589	{
1590	uint8_t c, *ptr;
1591	ptr = seg_to_linear(r->ds, r->edx);
1592	for(;;) {
1593	c = *ptr++;
1594	if (c == '$')
1595	break;
1596	putchar(c);
1597	}
1598	r->eax = (r->eax & ~0xff) \| '$';
1599	}
1600	break;
1601	case 0xff: /* extension: write eflags number in edx */
1602	v = (int)r->edx;
1603	#ifndef LINUX_VM86_IOPL_FIX
1604	v &= ~0x3000;
1605	#endif
1606	printf("%08x\n", v);
1607	break;
1608	default:
1609	unknown_int:
1610	printf("unsupported int 0x%02x\n", int_num);
1611	goto the_end;
1612	}
1613	}
1614	break;
1615	case VM86_SIGNAL:
1616	/* a signal came, we just ignore that */
1617	break;
1618	case VM86_STI:
1619	break;
1620	default:
1621	printf("ERROR: unhandled vm86 return code (0x%x)\n", ret);
1622	goto the_end;
1623	}
1624	}
1625	the_end:
1626	printf("VM86 end\n");
1627	munmap(vm86_mem, 0x110000);
1628	}
1629	#endif
1630
1631	/* exception tests */
1632	#if defined(__i386__) && !defined(REG_EAX)
1633	#define REG_EAX EAX
1634	#define REG_EBX EBX
1635	#define REG_ECX ECX
1636	#define REG_EDX EDX
1637	#define REG_ESI ESI
1638	#define REG_EDI EDI
1639	#define REG_EBP EBP
1640	#define REG_ESP ESP
1641	#define REG_EIP EIP
1642	#define REG_EFL EFL
1643	#define REG_TRAPNO TRAPNO
1644	#define REG_ERR ERR
1645	#endif
1646
1647	#if defined(__x86_64__)
1648	#define REG_EIP REG_RIP
1649	#endif
1650
1651	jmp_buf jmp_env;
1652	int v1;
1653	int tab[2];
1654
1655	void sig_handler(int sig, siginfo_t info, void puc)
1656	{
1657	struct ucontext *uc = puc;
1658
1659	printf("si_signo=%d si_errno=%d si_code=%d",
1660	info->si_signo, info->si_errno, info->si_code);
1661	printf(" si_addr=0x%08lx",
1662	(unsigned long)info->si_addr);
1663	printf("\n");
1664
1665	printf("trapno=" FMTLX " err=" FMTLX,
1666	(long)uc->uc_mcontext.gregs[REG_TRAPNO],
1667	(long)uc->uc_mcontext.gregs[REG_ERR]);
1668	printf(" EIP=" FMTLX, (long)uc->uc_mcontext.gregs[REG_EIP]);
1669	printf("\n");
1670	longjmp(jmp_env, 1);
1671	}
1672
1673	void test_exceptions(void)
1674	{
1675	struct sigaction act;
1676	volatile int val;
1677
1678	act.sa_sigaction = sig_handler;
1679	sigemptyset(&act.sa_mask);
1680	act.sa_flags = SA_SIGINFO \| SA_NODEFER;
1681	sigaction(SIGFPE, &act, NULL);
1682	sigaction(SIGILL, &act, NULL);
1683	sigaction(SIGSEGV, &act, NULL);
1684	sigaction(SIGBUS, &act, NULL);
1685	sigaction(SIGTRAP, &act, NULL);
1686
1687	/* test division by zero reporting */
1688	printf("DIVZ exception:\n");
1689	if (setjmp(jmp_env) == 0) {
1690	/* now divide by zero */
1691	v1 = 0;
1692	v1 = 2 / v1;
1693	}
1694
1695	#if !defined(__x86_64__)
1696	printf("BOUND exception:\n");
1697	if (setjmp(jmp_env) == 0) {
1698	/* bound exception */
1699	tab[0] = 1;
1700	tab[1] = 10;
1701	asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
1702	}
1703	#endif
1704
1705	#ifdef TEST_SEGS
1706	printf("segment exceptions:\n");
1707	if (setjmp(jmp_env) == 0) {
1708	/* load an invalid segment */
1709	asm volatile ("movl %0, %%fs" : : "r" ((0x1234 << 3) \| 1));
1710	}
1711	if (setjmp(jmp_env) == 0) {
1712	/* null data segment is valid */
1713	asm volatile ("movl %0, %%fs" : : "r" (3));
1714	/* null stack segment */
1715	asm volatile ("movl %0, %%ss" : : "r" (3));
1716	}
1717
1718	{
1719	struct modify_ldt_ldt_s ldt;
1720	ldt.entry_number = 1;
1721	ldt.base_addr = (unsigned long)&seg_data1;
1722	ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1723	ldt.seg_32bit = 1;
1724	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1725	ldt.read_exec_only = 0;
1726	ldt.limit_in_pages = 1;
1727	ldt.seg_not_present = 1;
1728	ldt.useable = 1;
1729	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1730
1731	if (setjmp(jmp_env) == 0) {
1732	/* segment not present */
1733	asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1734	}
1735	}
1736	#endif
1737
1738	/* test SEGV reporting */
1739	printf("PF exception:\n");
1740	if (setjmp(jmp_env) == 0) {
1741	val = 1;
1742	/* we add a nop to test a weird PC retrieval case */
1743	asm volatile ("nop");
1744	/* now store in an invalid address */
1745	(char )0x1234 = 1;
1746	}
1747
1748	/* test SEGV reporting */
1749	printf("PF exception:\n");
1750	if (setjmp(jmp_env) == 0) {
1751	val = 1;
1752	/* read from an invalid address */
1753	v1 = (char )0x1234;
1754	}
1755
1756	/* test illegal instruction reporting */
1757	printf("UD2 exception:\n");
1758	if (setjmp(jmp_env) == 0) {
1759	/* now execute an invalid instruction */
1760	asm volatile("ud2");
1761	}
1762	printf("lock nop exception:\n");
1763	if (setjmp(jmp_env) == 0) {
1764	/* now execute an invalid instruction */
1765	asm volatile("lock nop");
1766	}
1767
1768	printf("INT exception:\n");
1769	if (setjmp(jmp_env) == 0) {
1770	asm volatile ("int $0xfd");
1771	}
1772	if (setjmp(jmp_env) == 0) {
1773	asm volatile ("int $0x01");
1774	}
1775	if (setjmp(jmp_env) == 0) {
1776	asm volatile (".byte 0xcd, 0x03");
1777	}
1778	if (setjmp(jmp_env) == 0) {
1779	asm volatile ("int $0x04");
1780	}
1781	if (setjmp(jmp_env) == 0) {
1782	asm volatile ("int $0x05");
1783	}
1784
1785	printf("INT3 exception:\n");
1786	if (setjmp(jmp_env) == 0) {
1787	asm volatile ("int3");
1788	}
1789
1790	printf("CLI exception:\n");
1791	if (setjmp(jmp_env) == 0) {
1792	asm volatile ("cli");
1793	}
1794
1795	printf("STI exception:\n");
1796	if (setjmp(jmp_env) == 0) {
1797	asm volatile ("cli");
1798	}
1799
1800	#if !defined(__x86_64__)
1801	printf("INTO exception:\n");
1802	if (setjmp(jmp_env) == 0) {
1803	/* overflow exception */
1804	asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
1805	}
1806	#endif
1807
1808	printf("OUTB exception:\n");
1809	if (setjmp(jmp_env) == 0) {
1810	asm volatile ("outb %%al, %%dx" : : "d" (0x4321), "a" (0));
1811	}
1812
1813	printf("INB exception:\n");
1814	if (setjmp(jmp_env) == 0) {
1815	asm volatile ("inb %%dx, %%al" : "=a" (val) : "d" (0x4321));
1816	}
1817
1818	printf("REP OUTSB exception:\n");
1819	if (setjmp(jmp_env) == 0) {
1820	asm volatile ("rep outsb" : : "d" (0x4321), "S" (tab), "c" (1));
1821	}
1822
1823	printf("REP INSB exception:\n");
1824	if (setjmp(jmp_env) == 0) {
1825	asm volatile ("rep insb" : : "d" (0x4321), "D" (tab), "c" (1));
1826	}
1827
1828	printf("HLT exception:\n");
1829	if (setjmp(jmp_env) == 0) {
1830	asm volatile ("hlt");
1831	}
1832
1833	printf("single step exception:\n");
1834	val = 0;
1835	if (setjmp(jmp_env) == 0) {
1836	asm volatile ("pushf\n"
1837	"orl $0x00100, (%%esp)\n"
1838	"popf\n"
1839	"movl $0xabcd, %0\n"
1840	"movl $0x0, %0\n" : "=m" (val) : : "cc", "memory");
1841	}
1842	printf("val=0x%x\n", val);
1843	}
1844
1845	#if !defined(__x86_64__)
1846	/* specific precise single step test */
1847	void sig_trap_handler(int sig, siginfo_t info, void puc)
1848	{
1849	struct ucontext *uc = puc;
1850	printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]);
1851	}
1852
1853	const uint8_t sstep_buf1[4] = { 1, 2, 3, 4};
1854	uint8_t sstep_buf2[4];
1855
1856	void test_single_step(void)
1857	{
1858	struct sigaction act;
1859	volatile int val;
1860	int i;
1861
1862	val = 0;
1863	act.sa_sigaction = sig_trap_handler;
1864	sigemptyset(&act.sa_mask);
1865	act.sa_flags = SA_SIGINFO;
1866	sigaction(SIGTRAP, &act, NULL);
1867	asm volatile ("pushf\n"
1868	"orl $0x00100, (%%esp)\n"
1869	"popf\n"
1870	"movl $0xabcd, %0\n"
1871
1872	/* jmp test */
1873	"movl $3, %%ecx\n"
1874	"1:\n"
1875	"addl $1, %0\n"
1876	"decl %%ecx\n"
1877	"jnz 1b\n"
1878
1879	/* movsb: the single step should stop at each movsb iteration */
1880	"movl $sstep_buf1, %%esi\n"
1881	"movl $sstep_buf2, %%edi\n"
1882	"movl $0, %%ecx\n"
1883	"rep movsb\n"
1884	"movl $3, %%ecx\n"
1885	"rep movsb\n"
1886	"movl $1, %%ecx\n"
1887	"rep movsb\n"
1888
1889	/* cmpsb: the single step should stop at each cmpsb iteration */
1890	"movl $sstep_buf1, %%esi\n"
1891	"movl $sstep_buf2, %%edi\n"
1892	"movl $0, %%ecx\n"
1893	"rep cmpsb\n"
1894	"movl $4, %%ecx\n"
1895	"rep cmpsb\n"
1896
1897	/* getpid() syscall: single step should skip one
1898	instruction */
1899	"movl $20, %%eax\n"
1900	"int $0x80\n"
1901	"movl $0, %%eax\n"
1902
1903	/* when modifying SS, trace is not done on the next
1904	instruction */
1905	"movl %%ss, %%ecx\n"
1906	"movl %%ecx, %%ss\n"
1907	"addl $1, %0\n"
1908	"movl $1, %%eax\n"
1909	"movl %%ecx, %%ss\n"
1910	"jmp 1f\n"
1911	"addl $1, %0\n"
1912	"1:\n"
1913	"movl $1, %%eax\n"
1914	"pushl %%ecx\n"
1915	"popl %%ss\n"
1916	"addl $1, %0\n"
1917	"movl $1, %%eax\n"
1918
1919	"pushf\n"
1920	"andl $~0x00100, (%%esp)\n"
1921	"popf\n"
1922	: "=m" (val)
1923	:
1924	: "cc", "memory", "eax", "ecx", "esi", "edi");
1925	printf("val=%d\n", val);
1926	for(i = 0; i < 4; i++)
1927	printf("sstep_buf2[%d] = %d\n", i, sstep_buf2[i]);
1928	}
1929
1930	/* self modifying code test */
1931	uint8_t code[] = {
1932	0xb8, 0x1, 0x00, 0x00, 0x00, /* movl $1, %eax */
1933	0xc3, /* ret */
1934	};
1935
1936	asm("smc_code2:\n"
1937	"movl 4(%esp), %eax\n"
1938	"movl %eax, smc_patch_addr2 + 1\n"
1939	"nop\n"
1940	"nop\n"
1941	"nop\n"
1942	"nop\n"
1943	"nop\n"
1944	"nop\n"
1945	"nop\n"
1946	"nop\n"
1947	"smc_patch_addr2:\n"
1948	"movl $1, %eax\n"
1949	"ret\n");
1950
1951	typedef int FuncType(void);
1952	extern int smc_code2(int);
1953	void test_self_modifying_code(void)
1954	{
1955	int i;
1956
1957	printf("self modifying code:\n");
1958	printf("func1 = 0x%x\n", ((FuncType *)code)());
1959	for(i = 2; i <= 4; i++) {
1960	code[1] = i;
1961	printf("func%d = 0x%x\n", i, ((FuncType *)code)());
1962	}
1963
1964	/* more difficult test : the modified code is just after the
1965	modifying instruction. It is forbidden in Intel specs, but it
1966	is used by old DOS programs */
1967	for(i = 2; i <= 4; i++) {
1968	printf("smc_code2(%d) = %d\n", i, smc_code2(i));
1969	}
1970	}
1971	#endif
1972
1973	long enter_stack[4096];
1974
1975	#if defined(__x86_64__)
1976	#define RSP "%%rsp"
1977	#define RBP "%%rbp"
1978	#else
1979	#define RSP "%%esp"
1980	#define RBP "%%ebp"
1981	#endif
1982
1983	#define TEST_ENTER(size, stack_type, level)\
1984	{\
1985	long esp_save, esp_val, ebp_val, ebp_save, i;\
1986	stack_type ptr, stack_end, *stack_ptr;\
1987	memset(enter_stack, 0, sizeof(enter_stack));\
1988	stack_end = stack_ptr = (stack_type *)(enter_stack + 4096);\
1989	ebp_val = (long)stack_ptr;\
1990	for(i=1;i<=32;i++)\
1991	*--stack_ptr = i;\
1992	esp_val = (long)stack_ptr;\
1993	asm("mov " RSP ", %[esp_save]\n"\
1994	"mov " RBP ", %[ebp_save]\n"\
1995	"mov %[esp_val], " RSP "\n"\
1996	"mov %[ebp_val], " RBP "\n"\
1997	"enter" size " $8, $" #level "\n"\
1998	"mov " RSP ", %[esp_val]\n"\
1999	"mov " RBP ", %[ebp_val]\n"\
2000	"mov %[esp_save], " RSP "\n"\
2001	"mov %[ebp_save], " RBP "\n"\
2002	: [esp_save] "=r" (esp_save),\
2003	[ebp_save] "=r" (ebp_save),\
2004	[esp_val] "=r" (esp_val),\
2005	[ebp_val] "=r" (ebp_val)\
2006	: "[esp_val]" (esp_val),\
2007	"[ebp_val]" (ebp_val));\
2008	printf("level=%d:\n", level);\
2009	printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
2010	printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
2011	for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
2012	printf(FMTLX "\n", (long)ptr[0]);\
2013	}
2014
2015	static void test_enter(void)
2016	{
2017	#if defined(__x86_64__)
2018	TEST_ENTER("q", uint64_t, 0);
2019	TEST_ENTER("q", uint64_t, 1);
2020	TEST_ENTER("q", uint64_t, 2);
2021	TEST_ENTER("q", uint64_t, 31);
2022	#else
2023	TEST_ENTER("l", uint32_t, 0);
2024	TEST_ENTER("l", uint32_t, 1);
2025	TEST_ENTER("l", uint32_t, 2);
2026	TEST_ENTER("l", uint32_t, 31);
2027	#endif
2028
2029	TEST_ENTER("w", uint16_t, 0);
2030	TEST_ENTER("w", uint16_t, 1);
2031	TEST_ENTER("w", uint16_t, 2);
2032	TEST_ENTER("w", uint16_t, 31);
2033	}
2034
2035	#ifdef TEST_SSE
2036
2037	typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
2038	typedef int __m128 __attribute__ ((__mode__(__V4SF__)));
2039
2040	typedef union {
2041	double d[2];
2042	float s[4];
2043	uint32_t l[4];
2044	uint64_t q[2];
2045	__m128 dq;
2046	} XMMReg;
2047
2048	static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
2049	{ 0x456723c698694873, 0xdc515cff944a58ec },
2050	{ 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
2051	{ 0x007c62c2085427f8, 0x231be9e8cde7438d },
2052	{ 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
2053	};
2054
2055	#define SSE_OP(op)\
2056	{\
2057	asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2058	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2059	#op,\
2060	a.q[1], a.q[0],\
2061	b.q[1], b.q[0],\
2062	r.q[1], r.q[0]);\
2063	}
2064
2065	#define SSE_OP2(op)\
2066	{\
2067	int i;\
2068	for(i=0;i<2;i++) {\
2069	a.q[0] = test_values[2*i][0];\
2070	a.q[1] = test_values[2*i][1];\
2071	b.q[0] = test_values[2*i+1][0];\
2072	b.q[1] = test_values[2*i+1][1];\
2073	SSE_OP(op);\
2074	}\
2075	}
2076
2077	#define MMX_OP2(op)\
2078	{\
2079	int i;\
2080	for(i=0;i<2;i++) {\
2081	a.q[0] = test_values[2*i][0];\
2082	b.q[0] = test_values[2*i+1][0];\
2083	asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
2084	printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
2085	#op,\
2086	a.q[0],\
2087	b.q[0],\
2088	r.q[0]);\
2089	}\
2090	SSE_OP2(op);\
2091	}
2092
2093	#define SHUF_OP(op, ib)\
2094	{\
2095	a.q[0] = test_values[0][0];\
2096	a.q[1] = test_values[0][1];\
2097	b.q[0] = test_values[1][0];\
2098	b.q[1] = test_values[1][1];\
2099	asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2100	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2101	#op,\
2102	a.q[1], a.q[0],\
2103	b.q[1], b.q[0],\
2104	ib,\
2105	r.q[1], r.q[0]);\
2106	}
2107
2108	#define PSHUF_OP(op, ib)\
2109	{\
2110	int i;\
2111	for(i=0;i<2;i++) {\
2112	a.q[0] = test_values[2*i][0];\
2113	a.q[1] = test_values[2*i][1];\
2114	asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2115	printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2116	#op,\
2117	a.q[1], a.q[0],\
2118	ib,\
2119	r.q[1], r.q[0]);\
2120	}\
2121	}
2122
2123	#define SHIFT_IM(op, ib)\
2124	{\
2125	int i;\
2126	for(i=0;i<2;i++) {\
2127	a.q[0] = test_values[2*i][0];\
2128	a.q[1] = test_values[2*i][1];\
2129	asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
2130	printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2131	#op,\
2132	a.q[1], a.q[0],\
2133	ib,\
2134	r.q[1], r.q[0]);\
2135	}\
2136	}
2137
2138	#define SHIFT_OP(op, ib)\
2139	{\
2140	int i;\
2141	SHIFT_IM(op, ib);\
2142	for(i=0;i<2;i++) {\
2143	a.q[0] = test_values[2*i][0];\
2144	a.q[1] = test_values[2*i][1];\
2145	b.q[0] = ib;\
2146	b.q[1] = 0;\
2147	asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2148	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2149	#op,\
2150	a.q[1], a.q[0],\
2151	b.q[1], b.q[0],\
2152	r.q[1], r.q[0]);\
2153	}\
2154	}
2155
2156	#define MOVMSK(op)\
2157	{\
2158	int i, reg;\
2159	for(i=0;i<2;i++) {\
2160	a.q[0] = test_values[2*i][0];\
2161	a.q[1] = test_values[2*i][1];\
2162	asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
2163	printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2164	#op,\
2165	a.q[1], a.q[0],\
2166	reg);\
2167	}\
2168	}
2169
2170	#define SSE_OPS(a) \
2171	SSE_OP(a ## ps);\
2172	SSE_OP(a ## ss);
2173
2174	#define SSE_OPD(a) \
2175	SSE_OP(a ## pd);\
2176	SSE_OP(a ## sd);
2177
2178	#define SSE_COMI(op, field)\
2179	{\
2180	unsigned int eflags;\
2181	XMMReg a, b;\
2182	a.field[0] = a1;\
2183	b.field[0] = b1;\
2184	asm volatile (#op " %2, %1\n"\
2185	"pushf\n"\
2186	"pop %0\n"\
2187	: "=m" (eflags)\
2188	: "x" (a.dq), "x" (b.dq));\
2189	printf("%-9s: a=%f b=%f cc=%04x\n",\
2190	#op, a1, b1,\
2191	eflags & (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));\
2192	}
2193
2194	void test_sse_comi(double a1, double b1)
2195	{
2196	SSE_COMI(ucomiss, s);
2197	SSE_COMI(ucomisd, d);
2198	SSE_COMI(comiss, s);
2199	SSE_COMI(comisd, d);
2200	}
2201
2202	#define CVT_OP_XMM(op)\
2203	{\
2204	asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2205	printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2206	#op,\
2207	a.q[1], a.q[0],\
2208	r.q[1], r.q[0]);\
2209	}
2210
2211	/* Force %xmm0 usage to avoid the case where both register index are 0
2212	to test intruction decoding more extensively */
2213	#define CVT_OP_XMM2MMX(op)\
2214	{\
2215	asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
2216	: "%xmm0");\
2217	printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
2218	#op,\
2219	a.q[1], a.q[0],\
2220	r.q[0]);\
2221	}
2222
2223	#define CVT_OP_MMX2XMM(op)\
2224	{\
2225	asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
2226	printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
2227	#op,\
2228	a.q[0],\
2229	r.q[1], r.q[0]);\
2230	}
2231
2232	#define CVT_OP_REG2XMM(op)\
2233	{\
2234	asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
2235	printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
2236	#op,\
2237	a.l[0],\
2238	r.q[1], r.q[0]);\
2239	}
2240
2241	#define CVT_OP_XMM2REG(op)\
2242	{\
2243	asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
2244	printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2245	#op,\
2246	a.q[1], a.q[0],\
2247	r.l[0]);\
2248	}
2249
2250	struct fpxstate {
2251	uint16_t fpuc;
2252	uint16_t fpus;
2253	uint16_t fptag;
2254	uint16_t fop;
2255	uint32_t fpuip;
2256	uint16_t cs_sel;
2257	uint16_t dummy0;
2258	uint32_t fpudp;
2259	uint16_t ds_sel;
2260	uint16_t dummy1;
2261	uint32_t mxcsr;
2262	uint32_t mxcsr_mask;
2263	uint8_t fpregs1[8 * 16];
2264	uint8_t xmm_regs[8 * 16];
2265	uint8_t dummy2[224];
2266	};
2267
2268	static struct fpxstate fpx_state __attribute__((aligned(16)));
2269	static struct fpxstate fpx_state2 __attribute__((aligned(16)));
2270
2271	void test_fxsave(void)
2272	{
2273	struct fpxstate *fp = &fpx_state;
2274	struct fpxstate *fp2 = &fpx_state2;
2275	int i, nb_xmm;
2276	XMMReg a, b;
2277	a.q[0] = test_values[0][0];
2278	a.q[1] = test_values[0][1];
2279	b.q[0] = test_values[1][0];
2280	b.q[1] = test_values[1][1];
2281
2282	asm("movdqa %2, %%xmm0\n"
2283	"movdqa %3, %%xmm7\n"
2284	#if defined(__x86_64__)
2285	"movdqa %2, %%xmm15\n"
2286	#endif
2287	" fld1\n"
2288	" fldpi\n"
2289	" fldln2\n"
2290	" fxsave %0\n"
2291	" fxrstor %0\n"
2292	" fxsave %1\n"
2293	" fninit\n"
2294	: "=m" ((uint32_t )fp2), "=m" ((uint32_t )fp)
2295	: "m" (a), "m" (b));
2296	printf("fpuc=%04x\n", fp->fpuc);
2297	printf("fpus=%04x\n", fp->fpus);
2298	printf("fptag=%04x\n", fp->fptag);
2299	for(i = 0; i < 3; i++) {
2300	printf("ST%d: " FMT64X " %04x\n",
2301	i,
2302	(uint64_t )&fp->fpregs1[i * 16],
2303	(uint16_t )&fp->fpregs1[i * 16 + 8]);
2304	}
2305	printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
2306	#if defined(__x86_64__)
2307	nb_xmm = 16;
2308	#else
2309	nb_xmm = 8;
2310	#endif
2311	for(i = 0; i < nb_xmm; i++) {
2312	printf("xmm%d: " FMT64X "" FMT64X "\n",
2313	i,
2314	(uint64_t )&fp->xmm_regs[i * 16],
2315	(uint64_t )&fp->xmm_regs[i * 16 + 8]);
2316	}
2317	}
2318
2319	void test_sse(void)
2320	{
2321	XMMReg r, a, b;
2322	int i;
2323
2324	MMX_OP2(punpcklbw);
2325	MMX_OP2(punpcklwd);
2326	MMX_OP2(punpckldq);
2327	MMX_OP2(packsswb);
2328	MMX_OP2(pcmpgtb);
2329	MMX_OP2(pcmpgtw);
2330	MMX_OP2(pcmpgtd);
2331	MMX_OP2(packuswb);
2332	MMX_OP2(punpckhbw);
2333	MMX_OP2(punpckhwd);
2334	MMX_OP2(punpckhdq);
2335	MMX_OP2(packssdw);
2336	MMX_OP2(pcmpeqb);
2337	MMX_OP2(pcmpeqw);
2338	MMX_OP2(pcmpeqd);
2339
2340	MMX_OP2(paddq);
2341	MMX_OP2(pmullw);
2342	MMX_OP2(psubusb);
2343	MMX_OP2(psubusw);
2344	MMX_OP2(pminub);
2345	MMX_OP2(pand);
2346	MMX_OP2(paddusb);
2347	MMX_OP2(paddusw);
2348	MMX_OP2(pmaxub);
2349	MMX_OP2(pandn);
2350
2351	MMX_OP2(pmulhuw);
2352	MMX_OP2(pmulhw);
2353
2354	MMX_OP2(psubsb);
2355	MMX_OP2(psubsw);
2356	MMX_OP2(pminsw);
2357	MMX_OP2(por);
2358	MMX_OP2(paddsb);
2359	MMX_OP2(paddsw);
2360	MMX_OP2(pmaxsw);
2361	MMX_OP2(pxor);
2362	MMX_OP2(pmuludq);
2363	MMX_OP2(pmaddwd);
2364	MMX_OP2(psadbw);
2365	MMX_OP2(psubb);
2366	MMX_OP2(psubw);
2367	MMX_OP2(psubd);
2368	MMX_OP2(psubq);
2369	MMX_OP2(paddb);
2370	MMX_OP2(paddw);
2371	MMX_OP2(paddd);
2372
2373	MMX_OP2(pavgb);
2374	MMX_OP2(pavgw);
2375
2376	asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
2377	printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
2378
2379	asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
2380	printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
2381
2382	a.q[0] = test_values[0][0];
2383	a.q[1] = test_values[0][1];
2384	asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2385	printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2386
2387	asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2388	printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2389
2390	asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2391	printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2392
2393	asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2394	printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2395
2396	{
2397	r.q[0] = -1;
2398	r.q[1] = -1;
2399
2400	a.q[0] = test_values[0][0];
2401	a.q[1] = test_values[0][1];
2402	b.q[0] = test_values[1][0];
2403	b.q[1] = test_values[1][1];
2404	asm volatile("maskmovq %1, %0" :
2405	: "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
2406	: "memory");
2407	printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n",
2408	"maskmov",
2409	r.q[0],
2410	a.q[0],
2411	b.q[0]);
2412	asm volatile("maskmovdqu %1, %0" :
2413	: "x" (a.dq), "x" (b.dq), "D" (&r)
2414	: "memory");
2415	printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n",
2416	"maskmov",
2417	r.q[1], r.q[0],
2418	a.q[1], a.q[0],
2419	b.q[1], b.q[0]);
2420	}
2421
2422	asm volatile ("emms");
2423
2424	SSE_OP2(punpcklqdq);
2425	SSE_OP2(punpckhqdq);
2426	SSE_OP2(andps);
2427	SSE_OP2(andpd);
2428	SSE_OP2(andnps);
2429	SSE_OP2(andnpd);
2430	SSE_OP2(orps);
2431	SSE_OP2(orpd);
2432	SSE_OP2(xorps);
2433	SSE_OP2(xorpd);
2434
2435	SSE_OP2(unpcklps);
2436	SSE_OP2(unpcklpd);
2437	SSE_OP2(unpckhps);
2438	SSE_OP2(unpckhpd);
2439
2440	SHUF_OP(shufps, 0x78);
2441	SHUF_OP(shufpd, 0x02);
2442
2443	PSHUF_OP(pshufd, 0x78);
2444	PSHUF_OP(pshuflw, 0x78);
2445	PSHUF_OP(pshufhw, 0x78);
2446
2447	SHIFT_OP(psrlw, 7);
2448	SHIFT_OP(psrlw, 16);
2449	SHIFT_OP(psraw, 7);
2450	SHIFT_OP(psraw, 16);
2451	SHIFT_OP(psllw, 7);
2452	SHIFT_OP(psllw, 16);
2453
2454	SHIFT_OP(psrld, 7);
2455	SHIFT_OP(psrld, 32);
2456	SHIFT_OP(psrad, 7);
2457	SHIFT_OP(psrad, 32);
2458	SHIFT_OP(pslld, 7);
2459	SHIFT_OP(pslld, 32);
2460
2461	SHIFT_OP(psrlq, 7);
2462	SHIFT_OP(psrlq, 32);
2463	SHIFT_OP(psllq, 7);
2464	SHIFT_OP(psllq, 32);
2465
2466	SHIFT_IM(psrldq, 16);
2467	SHIFT_IM(psrldq, 7);
2468	SHIFT_IM(pslldq, 16);
2469	SHIFT_IM(pslldq, 7);
2470
2471	MOVMSK(movmskps);
2472	MOVMSK(movmskpd);
2473
2474	/* FPU specific ops */
2475
2476	{
2477	uint32_t mxcsr;
2478	asm volatile("stmxcsr %0" : "=m" (mxcsr));
2479	printf("mxcsr=%08x\n", mxcsr & 0x1f80);
2480	asm volatile("ldmxcsr %0" : : "m" (mxcsr));
2481	}
2482
2483	test_sse_comi(2, -1);
2484	test_sse_comi(2, 2);
2485	test_sse_comi(2, 3);
2486	test_sse_comi(2, q_nan.d);
2487	test_sse_comi(q_nan.d, -1);
2488
2489	for(i = 0; i < 2; i++) {
2490	a.s[0] = 2.7;
2491	a.s[1] = 3.4;
2492	a.s[2] = 4;
2493	a.s[3] = -6.3;
2494	b.s[0] = 45.7;
2495	b.s[1] = 353.4;
2496	b.s[2] = 4;
2497	b.s[3] = 56.3;
2498	if (i == 1) {
2499	a.s[0] = q_nan.d;
2500	b.s[3] = q_nan.d;
2501	}
2502
2503	SSE_OPS(add);
2504	SSE_OPS(mul);
2505	SSE_OPS(sub);
2506	SSE_OPS(min);
2507	SSE_OPS(div);
2508	SSE_OPS(max);
2509	SSE_OPS(sqrt);
2510	SSE_OPS(cmpeq);
2511	SSE_OPS(cmplt);
2512	SSE_OPS(cmple);
2513	SSE_OPS(cmpunord);
2514	SSE_OPS(cmpneq);
2515	SSE_OPS(cmpnlt);
2516	SSE_OPS(cmpnle);
2517	SSE_OPS(cmpord);
2518
2519
2520	a.d[0] = 2.7;
2521	a.d[1] = -3.4;
2522	b.d[0] = 45.7;
2523	b.d[1] = -53.4;
2524	if (i == 1) {
2525	a.d[0] = q_nan.d;
2526	b.d[1] = q_nan.d;
2527	}
2528	SSE_OPD(add);
2529	SSE_OPD(mul);
2530	SSE_OPD(sub);
2531	SSE_OPD(min);
2532	SSE_OPD(div);
2533	SSE_OPD(max);
2534	SSE_OPD(sqrt);
2535	SSE_OPD(cmpeq);
2536	SSE_OPD(cmplt);
2537	SSE_OPD(cmple);
2538	SSE_OPD(cmpunord);
2539	SSE_OPD(cmpneq);
2540	SSE_OPD(cmpnlt);
2541	SSE_OPD(cmpnle);
2542	SSE_OPD(cmpord);
2543	}
2544
2545	/* float to float/int */
2546	a.s[0] = 2.7;
2547	a.s[1] = 3.4;
2548	a.s[2] = 4;
2549	a.s[3] = -6.3;
2550	CVT_OP_XMM(cvtps2pd);
2551	CVT_OP_XMM(cvtss2sd);
2552	CVT_OP_XMM2MMX(cvtps2pi);
2553	CVT_OP_XMM2MMX(cvttps2pi);
2554	CVT_OP_XMM2REG(cvtss2si);
2555	CVT_OP_XMM2REG(cvttss2si);
2556	CVT_OP_XMM(cvtps2dq);
2557	CVT_OP_XMM(cvttps2dq);
2558
2559	a.d[0] = 2.6;
2560	a.d[1] = -3.4;
2561	CVT_OP_XMM(cvtpd2ps);
2562	CVT_OP_XMM(cvtsd2ss);
2563	CVT_OP_XMM2MMX(cvtpd2pi);
2564	CVT_OP_XMM2MMX(cvttpd2pi);
2565	CVT_OP_XMM2REG(cvtsd2si);
2566	CVT_OP_XMM2REG(cvttsd2si);
2567	CVT_OP_XMM(cvtpd2dq);
2568	CVT_OP_XMM(cvttpd2dq);
2569
2570	/* sse/mmx moves */
2571	CVT_OP_XMM2MMX(movdq2q);
2572	CVT_OP_MMX2XMM(movq2dq);
2573
2574	/* int to float */
2575	a.l[0] = -6;
2576	a.l[1] = 2;
2577	a.l[2] = 100;
2578	a.l[3] = -60000;
2579	CVT_OP_MMX2XMM(cvtpi2ps);
2580	CVT_OP_MMX2XMM(cvtpi2pd);
2581	CVT_OP_REG2XMM(cvtsi2ss);
2582	CVT_OP_REG2XMM(cvtsi2sd);
2583	CVT_OP_XMM(cvtdq2ps);
2584	CVT_OP_XMM(cvtdq2pd);
2585
2586	/* XXX: test PNI insns */
2587	#if 0
2588	SSE_OP2(movshdup);
2589	#endif
2590	asm volatile ("emms");
2591	}
2592
2593	#endif
2594
2595	extern void *__start_initcall;
2596	extern void *__stop_initcall;
2597
2598
2599	int main(int argc, char **argv)
2600	{
2601	void **ptr;
2602	void (*func)(void);
2603
2604	ptr = &__start_initcall;
2605	while (ptr != &__stop_initcall) {
2606	func = *ptr++;
2607	func();
2608	}
2609	test_bsx();
2610	test_mul();
2611	test_jcc();
2612	test_floats();
2613	#if !defined(__x86_64__)
2614	test_bcd();
2615	#endif
2616	test_xchg();
2617	test_string();
2618	test_misc();
2619	test_lea();
2620	#ifdef TEST_SEGS
2621	test_segs();
2622	test_code16();
2623	#endif
2624	#ifdef TEST_VM86
2625	test_vm86();
2626	#endif
2627	test_exceptions();
2628	#if !defined(__x86_64__)
2629	test_self_modifying_code();
2630	test_single_step();
2631	#endif
2632	test_enter();
2633	#ifdef TEST_SSE
2634	test_sse();
2635	test_fxsave();
2636	#endif
2637	return 0;
2638	}

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source: vbox/trunk/src/recompiler/tests/test-i386.c@ 25722

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