| 1 | /*
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| 2 | * common defines for all CPUs
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| 3 | *
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| 4 | * Copyright (c) 2003 Fabrice Bellard
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with this library; if not, write to the Free Software
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| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 19 | */
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| 20 |
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| 21 | /*
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| 22 | * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 23 | * other than GPL or LGPL is available it will apply instead, Sun elects to use only
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| 24 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 25 | * a choice of LGPL license versions is made available with the language indicating
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| 26 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 27 | * of the LGPL is applied is otherwise unspecified.
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| 28 | */
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| 29 | #ifndef CPU_DEFS_H
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| 30 | #define CPU_DEFS_H
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| 31 |
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| 32 | #include "config.h"
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| 33 | #include <setjmp.h>
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| 34 | #include <inttypes.h>
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| 35 | #include "osdep.h"
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| 36 |
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| 37 | #ifndef TARGET_LONG_BITS
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| 38 | #error TARGET_LONG_BITS must be defined before including this header
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| 39 | #endif
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| 40 |
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| 41 | #ifndef TARGET_PHYS_ADDR_BITS
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| 42 | #if TARGET_LONG_BITS >= HOST_LONG_BITS
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| 43 | #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
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| 44 | #else
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| 45 | #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
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| 46 | #endif
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| 47 | #endif
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| 48 |
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| 49 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
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| 50 |
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| 51 | /* target_ulong is the type of a virtual address */
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| 52 | #if TARGET_LONG_SIZE == 4
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| 53 | typedef int32_t target_long;
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| 54 | typedef uint32_t target_ulong;
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| 55 | #define TARGET_FMT_lx "%08x"
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| 56 | #define TARGET_FMT_ld "%d"
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| 57 | #define TARGET_FMT_lu "%u"
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| 58 | #elif TARGET_LONG_SIZE == 8
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| 59 | typedef int64_t target_long;
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| 60 | typedef uint64_t target_ulong;
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| 61 | #define TARGET_FMT_lx "%016" PRIx64
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| 62 | #define TARGET_FMT_ld "%" PRId64
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| 63 | #define TARGET_FMT_lu "%" PRIu64
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| 64 | #else
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| 65 | #error TARGET_LONG_SIZE undefined
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| 66 | #endif
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| 67 |
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| 68 | /* target_phys_addr_t is the type of a physical address (its size can
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| 69 | be different from 'target_ulong'). We have sizeof(target_phys_addr)
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| 70 | = max(sizeof(unsigned long),
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| 71 | sizeof(size_of_target_physical_address)) because we must pass a
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| 72 | host pointer to memory operations in some cases */
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| 73 |
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| 74 | #if TARGET_PHYS_ADDR_BITS == 32
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| 75 | typedef uint32_t target_phys_addr_t;
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| 76 | #define TARGET_FMT_plx "%08x"
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| 77 | #elif TARGET_PHYS_ADDR_BITS == 64
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| 78 | typedef uint64_t target_phys_addr_t;
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| 79 | #define TARGET_FMT_plx "%016" PRIx64
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| 80 | #else
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| 81 | #error TARGET_PHYS_ADDR_BITS undefined
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| 82 | #endif
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| 83 |
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| 84 | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
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| 85 |
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| 86 | #define EXCP_INTERRUPT 0x10000 /* async interruption */
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| 87 | #define EXCP_HLT 0x10001 /* hlt instruction reached */
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| 88 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
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| 89 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
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| 90 | #if defined(VBOX)
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| 91 | #define EXCP_EXECUTE_RAW 0x11024 /* execute raw mode. */
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| 92 | #define EXCP_EXECUTE_HWACC 0x11025 /* execute hardware accelerated raw mode. */
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| 93 | #define EXCP_SINGLE_INSTR 0x11026 /* executed single instruction. */
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| 94 | #define EXCP_RC 0x11027 /* a EM rc was raised (VMR3Reset/Suspend/PowerOff). */
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| 95 | #endif /* VBOX */
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| 96 | #define MAX_BREAKPOINTS 32
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| 97 | #define MAX_WATCHPOINTS 32
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| 98 |
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| 99 | #define TB_JMP_CACHE_BITS 12
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| 100 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
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| 101 |
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| 102 | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
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| 103 | addresses on the same page. The top bits are the same. This allows
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| 104 | TLB invalidation to quickly clear a subset of the hash table. */
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| 105 | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
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| 106 | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
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| 107 | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
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| 108 | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
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| 109 |
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| 110 | #define CPU_TLB_BITS 8
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| 111 | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
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| 112 |
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| 113 | #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
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| 114 | #define CPU_TLB_ENTRY_BITS 4
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| 115 | #else
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| 116 | #define CPU_TLB_ENTRY_BITS 5
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| 117 | #endif
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| 118 |
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| 119 | typedef struct CPUTLBEntry {
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| 120 | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
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| 121 | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
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| 122 | go directly to ram.
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| 123 | bit 3 : indicates that the entry is invalid
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| 124 | bit 2..0 : zero
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| 125 | */
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| 126 | target_ulong addr_read;
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| 127 | target_ulong addr_write;
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| 128 | target_ulong addr_code;
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| 129 | /* Addend to virtual address to get physical address. IO accesses
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| 130 | use the correcponding iotlb value. */
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| 131 | #if TARGET_PHYS_ADDR_BITS == 64
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| 132 | /* on i386 Linux make sure it is aligned */
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| 133 | target_phys_addr_t addend __attribute__((aligned(8)));
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| 134 | #else
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| 135 | target_phys_addr_t addend;
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| 136 | #endif
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| 137 | /* padding to get a power of two size */
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| 138 | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
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| 139 | (sizeof(target_ulong) * 3 +
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| 140 | ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
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| 141 | sizeof(target_phys_addr_t))];
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| 142 | } CPUTLBEntry;
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| 143 |
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| 144 | #ifdef WORDS_BIGENDIAN
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| 145 | typedef struct icount_decr_u16 {
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| 146 | uint16_t high;
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| 147 | uint16_t low;
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| 148 | } icount_decr_u16;
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| 149 | #else
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| 150 | typedef struct icount_decr_u16 {
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| 151 | uint16_t low;
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| 152 | uint16_t high;
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| 153 | } icount_decr_u16;
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| 154 | #endif
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| 155 |
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| 156 |
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| 157 | #define CPU_TEMP_BUF_NLONGS 128
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| 158 | #ifdef VBOX
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| 159 | struct TCGContext;
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| 160 |
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| 161 | #define CPU_COMMON \
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| 162 | struct TranslationBlock *current_tb; /* currently executing TB */ \
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| 163 | /* soft mmu support */ \
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| 164 | /* in order to avoid passing too many arguments to the MMIO \
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| 165 | helpers, we store some rarely used information in the CPU \
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| 166 | context) */ \
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| 167 | unsigned long mem_io_pc; /* host pc at which the memory was \
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| 168 | accessed */ \
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| 169 | target_ulong mem_io_vaddr; /* target virtual addr at which the \
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| 170 | memory was accessed */ \
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| 171 | uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
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| 172 | uint32_t interrupt_request; \
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| 173 | /* The meaning of the MMU modes is defined in the target code. */ \
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| 174 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
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| 175 | target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
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| 176 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
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| 177 | /* buffer for temporaries in the code generator */ \
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| 178 | long temp_buf[CPU_TEMP_BUF_NLONGS]; \
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| 179 | \
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| 180 | int64_t icount_extra; /* Instructions until next timer event. */ \
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| 181 | /* Number of cycles left, with interrupt flag in high bit. \
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| 182 | This allows a single read-compare-cbranch-write sequence to test \
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| 183 | for both decrementer underflow and exceptions. */ \
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| 184 | union { \
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| 185 | uint32_t u32; \
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| 186 | icount_decr_u16 u16; \
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| 187 | } icount_decr; \
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| 188 | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
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| 189 | \
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| 190 | /* from this point: preserved by CPU reset */ \
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| 191 | /* ice debug support */ \
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| 192 | target_ulong breakpoints[MAX_BREAKPOINTS]; \
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| 193 | int nb_breakpoints; \
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| 194 | int singlestep_enabled; \
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| 195 | \
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| 196 | struct { \
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| 197 | target_ulong vaddr; \
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| 198 | int type; /* PAGE_READ/PAGE_WRITE */ \
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| 199 | } watchpoint[MAX_WATCHPOINTS]; \
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| 200 | int nb_watchpoints; \
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| 201 | int watchpoint_hit; \
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| 202 | \
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| 203 | /* Core interrupt code */ \
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| 204 | jmp_buf jmp_env; \
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| 205 | int exception_index; \
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| 206 | \
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| 207 | int user_mode_only; \
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| 208 | \
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| 209 | void *next_cpu; /* next CPU sharing TB cache */ \
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| 210 | int cpu_index; /* CPU index (informative) */ \
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| 211 | int running; /* Nonzero if cpu is currently running(usermode). */ \
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| 212 | /* user data */ \
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| 213 | void *opaque; \
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| 214 | \
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| 215 | const char *cpu_model_str; \
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| 216 | /* Codegenerator context */ \
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| 217 | struct TCGContext *tcg_context;
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| 218 | #else
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| 219 |
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| 220 | #define CPU_COMMON \
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| 221 | struct TranslationBlock *current_tb; /* currently executing TB */ \
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| 222 | /* soft mmu support */ \
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| 223 | /* in order to avoid passing too many arguments to the MMIO \
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| 224 | helpers, we store some rarely used information in the CPU \
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| 225 | context) */ \
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| 226 | unsigned long mem_io_pc; /* host pc at which the memory was \
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| 227 | accessed */ \
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| 228 | target_ulong mem_io_vaddr; /* target virtual addr at which the \
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| 229 | memory was accessed */ \
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| 230 | uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
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| 231 | uint32_t interrupt_request; \
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| 232 | /* The meaning of the MMU modes is defined in the target code. */ \
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| 233 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
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| 234 | target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
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| 235 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
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| 236 | /* buffer for temporaries in the code generator */ \
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| 237 | long temp_buf[CPU_TEMP_BUF_NLONGS]; \
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| 238 | \
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| 239 | int64_t icount_extra; /* Instructions until next timer event. */ \
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| 240 | /* Number of cycles left, with interrupt flag in high bit. \
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| 241 | This allows a single read-compare-cbranch-write sequence to test \
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| 242 | for both decrementer underflow and exceptions. */ \
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| 243 | union { \
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| 244 | uint32_t u32; \
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| 245 | icount_decr_u16 u16; \
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| 246 | } icount_decr; \
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| 247 | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
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| 248 | \
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| 249 | /* from this point: preserved by CPU reset */ \
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| 250 | /* ice debug support */ \
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| 251 | target_ulong breakpoints[MAX_BREAKPOINTS]; \
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| 252 | int nb_breakpoints; \
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| 253 | int singlestep_enabled; \
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| 254 | \
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| 255 | struct { \
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| 256 | target_ulong vaddr; \
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| 257 | int type; /* PAGE_READ/PAGE_WRITE */ \
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| 258 | } watchpoint[MAX_WATCHPOINTS]; \
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| 259 | int nb_watchpoints; \
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| 260 | int watchpoint_hit; \
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| 261 | \
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| 262 | /* Core interrupt code */ \
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| 263 | jmp_buf jmp_env; \
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| 264 | int exception_index; \
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| 265 | \
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| 266 | int user_mode_only; \
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| 267 | \
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| 268 | void *next_cpu; /* next CPU sharing TB cache */ \
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| 269 | int cpu_index; /* CPU index (informative) */ \
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| 270 | int running; /* Nonzero if cpu is currently running(usermode). */ \
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| 271 | /* user data */ \
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| 272 | void *opaque; \
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| 273 | \
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| 274 | const char *cpu_model_str;
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| 275 | #endif
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| 276 |
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| 277 | #endif
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