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source: vbox/trunk/src/recompiler_new/exec-all.h@ 13236

最後變更 在這個檔案從13236是 13230,由 vboxsync 提交於 16 年 前

further new recompiler work
  • 屬性 svn:eol-style 設為 native
檔案大小: 18.0 KB
行 
1/*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29
30/* allow to see translation results - the slowdown should be negligible, so we leave it */
31#ifndef VBOX
32#define DEBUG_DISAS
33#endif
34
35#ifdef VBOX
36# include <VBox/tm.h>
37# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
38# ifndef LOG_GROUP
39# define LOG_GROUP LOG_GROUP_REM
40# endif
41# include <VBox/log.h>
42# include "REMInternal.h"
43# include <VBox/vm.h>
44#endif /* VBOX */
45
46#ifndef glue
47#define xglue(x, y) x ## y
48#define glue(x, y) xglue(x, y)
49#define stringify(s) tostring(s)
50#define tostring(s) #s
51#endif
52
53#if __GNUC__ < 3
54#define __builtin_expect(x, n) (x)
55#endif
56
57#ifdef __i386__
58#define REGPARM(n) __attribute((regparm(n)))
59#else
60#define REGPARM(n)
61#endif
62
63/* is_jmp field values */
64#define DISAS_NEXT 0 /* next instruction can be analyzed */
65#define DISAS_JUMP 1 /* only pc was modified dynamically */
66#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
67#define DISAS_TB_JUMP 3 /* only pc was modified statically */
68
69typedef struct TranslationBlock TranslationBlock;
70
71/* XXX: make safe guess about sizes */
72#define MAX_OP_PER_INSTR 64
73/* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
74#define MAX_OPC_PARAM 10
75#define OPC_BUF_SIZE 512
76#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
77
78/* Maximum size a TCG op can expand to. This is complicated because a
79 single op may require several host instructions and regirster reloads.
80 For now take a wild guess at 128 bytes, which should allow at least
81 a couple of fixup instructions per argument. */
82#define TCG_MAX_OP_SIZE 128
83
84#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
85
86extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
87extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
88extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
89extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
90extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
91extern target_ulong gen_opc_jump_pc[2];
92extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
93
94typedef void (GenOpFunc)(void);
95typedef void (GenOpFunc1)(long);
96typedef void (GenOpFunc2)(long, long);
97typedef void (GenOpFunc3)(long, long, long);
98
99#ifndef VBOX
100extern FILE *logfile;
101extern int loglevel;
102#endif
103
104void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
105void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
106void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
107 unsigned long searched_pc, int pc_pos, void *puc);
108
109unsigned long code_gen_max_block_size(void);
110void cpu_gen_init(void);
111int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
112 int *gen_code_size_ptr);
113int cpu_restore_state(struct TranslationBlock *tb,
114 CPUState *env, unsigned long searched_pc,
115 void *puc);
116int cpu_restore_state_copy(struct TranslationBlock *tb,
117 CPUState *env, unsigned long searched_pc,
118 void *puc);
119void cpu_resume_from_signal(CPUState *env1, void *puc);
120void cpu_io_recompile(CPUState *env, void *retaddr);
121TranslationBlock *tb_gen_code(CPUState *env,
122 target_ulong pc, target_ulong cs_base, int flags,
123 int cflags);
124void cpu_exec_init(CPUState *env);
125int page_unprotect(target_ulong address, unsigned long pc, void *puc);
126void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
127 int is_cpu_write_access);
128void tb_invalidate_page_range(target_ulong start, target_ulong end);
129void tlb_flush_page(CPUState *env, target_ulong addr);
130void tlb_flush(CPUState *env, int flush_global);
131int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
132 target_phys_addr_t paddr, int prot,
133 int mmu_idx, int is_softmmu);
134static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
135 target_phys_addr_t paddr, int prot,
136 int mmu_idx, int is_softmmu)
137{
138 if (prot & PAGE_READ)
139 prot |= PAGE_EXEC;
140 return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
141}
142
143#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
144
145#define CODE_GEN_PHYS_HASH_BITS 15
146#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
147
148#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
149
150/* estimated block size for TB allocation */
151/* XXX: use a per code average code fragment size and modulate it
152 according to the host CPU */
153#if defined(CONFIG_SOFTMMU)
154#define CODE_GEN_AVG_BLOCK_SIZE 128
155#else
156#define CODE_GEN_AVG_BLOCK_SIZE 64
157#endif
158
159#if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
160#define USE_DIRECT_JUMP
161#endif
162#if defined(__i386__) && !defined(_WIN32)
163#define USE_DIRECT_JUMP
164#endif
165
166#ifdef VBOX /* bird: not safe in next step because of threading & cpu_interrupt. */
167#undef USE_DIRECT_JUMP
168#endif /* VBOX */
169
170struct TranslationBlock {
171 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
172 target_ulong cs_base; /* CS base for this block */
173 unsigned int flags; /* flags defining in which context the code was generated */
174 uint16_t size; /* size of target code for this block (1 <=
175 size <= TARGET_PAGE_SIZE) */
176 uint16_t cflags; /* compile flags */
177#define CF_COUNT_MASK 0x7fff
178#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
179
180#ifdef VBOX
181#define CF_RAW_MODE 0x0010 /* block was generated in raw mode */
182#endif
183
184 uint8_t *tc_ptr; /* pointer to the translated code */
185 /* next matching tb for physical address. */
186 struct TranslationBlock *phys_hash_next;
187 /* first and second physical page containing code. The lower bit
188 of the pointer tells the index in page_next[] */
189 struct TranslationBlock *page_next[2];
190 target_ulong page_addr[2];
191
192 /* the following data are used to directly call another TB from
193 the code of this one. */
194 uint16_t tb_next_offset[2]; /* offset of original jump target */
195#ifdef USE_DIRECT_JUMP
196 uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
197#else
198# if defined(VBOX) && defined(RT_OS_DARWIN) && defined(RT_ARCH_AMD64)
199# error "First 4GB aren't reachable. jmp dword [tb_next] wont work."
200# endif
201 uint32_t tb_next[2]; /* address of jump generated code */
202#endif
203 /* list of TBs jumping to this one. This is a circular list using
204 the two least significant bits of the pointers to tell what is
205 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
206 jmp_first */
207 struct TranslationBlock *jmp_next[2];
208 struct TranslationBlock *jmp_first;
209 uint32_t icount;
210};
211
212static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
213{
214 target_ulong tmp;
215 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
216 return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
217}
218
219static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
220{
221 target_ulong tmp;
222 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
223 return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
224 (tmp & TB_JMP_ADDR_MASK));
225}
226
227static inline unsigned int tb_phys_hash_func(unsigned long pc)
228{
229 return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
230}
231
232TranslationBlock *tb_alloc(target_ulong pc);
233void tb_free(TranslationBlock *tb);
234void tb_flush(CPUState *env);
235void tb_link_phys(TranslationBlock *tb,
236 target_ulong phys_pc, target_ulong phys_page2);
237void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
238
239extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
240
241extern uint8_t *code_gen_ptr;
242extern int code_gen_max_blocks;
243
244#if defined(USE_DIRECT_JUMP)
245
246#if defined(__powerpc__)
247static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
248{
249 uint32_t val, *ptr;
250
251 /* patch the branch destination */
252 ptr = (uint32_t *)jmp_addr;
253 val = *ptr;
254 val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
255 *ptr = val;
256 /* flush icache */
257 asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
258 asm volatile ("sync" : : : "memory");
259 asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
260 asm volatile ("sync" : : : "memory");
261 asm volatile ("isync" : : : "memory");
262}
263#elif defined(__i386__)
264static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
265{
266 /* patch the branch destination */
267 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
268 /* no need to flush icache explicitely */
269}
270#endif
271
272static inline void tb_set_jmp_target(TranslationBlock *tb,
273 int n, unsigned long addr)
274{
275 unsigned long offset;
276
277 offset = tb->tb_jmp_offset[n];
278 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
279 offset = tb->tb_jmp_offset[n + 2];
280 if (offset != 0xffff)
281 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
282}
283
284#else
285
286/* set the jump target */
287static inline void tb_set_jmp_target(TranslationBlock *tb,
288 int n, unsigned long addr)
289{
290 tb->tb_next[n] = addr;
291}
292
293#endif
294
295static inline void tb_add_jump(TranslationBlock *tb, int n,
296 TranslationBlock *tb_next)
297{
298 /* NOTE: this test is only needed for thread safety */
299 if (!tb->jmp_next[n]) {
300 /* patch the native jump address */
301 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
302
303 /* add in TB jmp circular list */
304 tb->jmp_next[n] = tb_next->jmp_first;
305 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
306 }
307}
308
309TranslationBlock *tb_find_pc(unsigned long pc_ptr);
310
311#ifndef offsetof
312#define offsetof(type, field) ((size_t) &((type *)0)->field)
313#endif
314
315#if defined(_WIN32)
316#define ASM_DATA_SECTION ".section \".data\"\n"
317#define ASM_PREVIOUS_SECTION ".section .text\n"
318#elif defined(__APPLE__)
319#define ASM_DATA_SECTION ".data\n"
320#define ASM_PREVIOUS_SECTION ".text\n"
321#else
322#define ASM_DATA_SECTION ".section \".data\"\n"
323#define ASM_PREVIOUS_SECTION ".previous\n"
324#endif
325
326#define ASM_OP_LABEL_NAME(n, opname) \
327 ASM_NAME(__op_label) #n "." ASM_NAME(opname)
328
329extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
330extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
331extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
332
333#ifdef __powerpc__
334static inline int testandset (int *p)
335{
336 int ret;
337 __asm__ __volatile__ (
338 "0: lwarx %0,0,%1\n"
339 " xor. %0,%3,%0\n"
340 " bne 1f\n"
341 " stwcx. %2,0,%1\n"
342 " bne- 0b\n"
343 "1: "
344 : "=&r" (ret)
345 : "r" (p), "r" (1), "r" (0)
346 : "cr0", "memory");
347 return ret;
348}
349#endif
350
351#ifdef __i386__
352static inline int testandset (int *p)
353{
354 long int readval = 0;
355
356 __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
357 : "+m" (*p), "+a" (readval)
358 : "r" (1)
359 : "cc");
360 return readval;
361}
362#endif
363
364#ifdef __x86_64__
365static inline int testandset (int *p)
366{
367 long int readval = 0;
368
369 __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
370 : "+m" (*p), "+a" (readval)
371 : "r" (1)
372 : "cc");
373 return readval;
374}
375#endif
376
377#ifdef __s390__
378static inline int testandset (int *p)
379{
380 int ret;
381
382 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
383 " jl 0b"
384 : "=&d" (ret)
385 : "r" (1), "a" (p), "0" (*p)
386 : "cc", "memory" );
387 return ret;
388}
389#endif
390
391#ifdef __alpha__
392static inline int testandset (int *p)
393{
394 int ret;
395 unsigned long one;
396
397 __asm__ __volatile__ ("0: mov 1,%2\n"
398 " ldl_l %0,%1\n"
399 " stl_c %2,%1\n"
400 " beq %2,1f\n"
401 ".subsection 2\n"
402 "1: br 0b\n"
403 ".previous"
404 : "=r" (ret), "=m" (*p), "=r" (one)
405 : "m" (*p));
406 return ret;
407}
408#endif
409
410#ifdef __sparc__
411static inline int testandset (int *p)
412{
413 int ret;
414
415 __asm__ __volatile__("ldstub [%1], %0"
416 : "=r" (ret)
417 : "r" (p)
418 : "memory");
419
420 return (ret ? 1 : 0);
421}
422#endif
423
424#ifdef __arm__
425static inline int testandset (int *spinlock)
426{
427 register unsigned int ret;
428 __asm__ __volatile__("swp %0, %1, [%2]"
429 : "=r"(ret)
430 : "0"(1), "r"(spinlock));
431
432 return ret;
433}
434#endif
435
436#ifdef __mc68000
437static inline int testandset (int *p)
438{
439 char ret;
440 __asm__ __volatile__("tas %1; sne %0"
441 : "=r" (ret)
442 : "m" (p)
443 : "cc","memory");
444 return ret;
445}
446#endif
447
448#ifdef __ia64
449#include <ia64intrin.h>
450
451static inline int testandset (int *p)
452{
453 return __sync_lock_test_and_set (p, 1);
454}
455#endif
456
457typedef int spinlock_t;
458
459#define SPIN_LOCK_UNLOCKED 0
460
461#if defined(CONFIG_USER_ONLY)
462static inline void spin_lock(spinlock_t *lock)
463{
464 while (testandset(lock));
465}
466
467static inline void spin_unlock(spinlock_t *lock)
468{
469 *lock = 0;
470}
471
472static inline int spin_trylock(spinlock_t *lock)
473{
474 return !testandset(lock);
475}
476#else
477static inline void spin_lock(spinlock_t *lock)
478{
479}
480
481static inline void spin_unlock(spinlock_t *lock)
482{
483}
484
485static inline int spin_trylock(spinlock_t *lock)
486{
487 return 1;
488}
489#endif
490
491extern spinlock_t tb_lock;
492
493extern int tb_invalidated_flag;
494
495#if !defined(CONFIG_USER_ONLY)
496
497void tlb_fill(target_ulong addr, int is_write, int is_user,
498 void *retaddr);
499
500#define ACCESS_TYPE (NB_MMU_MODES + 1)
501#define MEMSUFFIX _code
502#define env cpu_single_env
503
504#define DATA_SIZE 1
505#include "softmmu_header.h"
506
507#define DATA_SIZE 2
508#include "softmmu_header.h"
509
510#define DATA_SIZE 4
511#include "softmmu_header.h"
512
513#define DATA_SIZE 8
514#include "softmmu_header.h"
515
516#undef ACCESS_TYPE
517#undef MEMSUFFIX
518#undef env
519
520#endif
521
522#if defined(CONFIG_USER_ONLY)
523static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
524{
525 return addr;
526}
527#else
528# ifdef VBOX
529target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry);
530# if !defined(REM_PHYS_ADDR_IN_TLB)
531target_ulong remR3HCVirt2GCPhys(void *env, void *addr);
532# endif
533# endif
534/* NOTE: this function can trigger an exception */
535/* NOTE2: the returned address is not exactly the physical address: it
536 is the offset relative to phys_ram_base */
537static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
538{
539 int is_user, index, pd;
540
541 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
542#if defined(TARGET_I386)
543 is_user = ((env->hflags & HF_CPL_MASK) == 3);
544#elif defined (TARGET_PPC)
545 is_user = msr_pr;
546#elif defined (TARGET_MIPS)
547 is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
548#elif defined (TARGET_SPARC)
549 is_user = (env->psrs == 0);
550#elif defined (TARGET_ARM)
551 is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
552#elif defined (TARGET_SH4)
553 is_user = ((env->sr & SR_MD) == 0);
554#else
555#error unimplemented CPU
556#endif
557 if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
558 (addr & TARGET_PAGE_MASK), 0)) {
559 ldub_code(addr);
560 }
561 pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
562 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
563# ifdef VBOX
564 /* deal with non-MMIO access handlers. */
565 return remR3PhysGetPhysicalAddressCode(env, addr, &env->tlb_table[is_user][index]);
566# else
567 cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
568# endif
569 }
570# if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
571 return addr + env->tlb_table[is_user][index].addend;
572# elif defined(VBOX)
573 return remR3HCVirt2GCPhys(env, (void *)(addr + env->tlb_table[is_user][index].addend));
574# else
575 return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
576# endif
577}
578
579
580/* Deterministic execution requires that IO only be performed on the last
581 instruction of a TB so that interrupts take effect immediately. */
582static inline int can_do_io(CPUState *env)
583{
584 if (!use_icount)
585 return 1;
586
587 /* If not executing code then assume we are ok. */
588 if (!env->current_tb)
589 return 1;
590
591 return env->can_do_io != 0;
592}
593#endif
594
595
596#ifdef USE_KQEMU
597#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
598
599int kqemu_init(CPUState *env);
600int kqemu_cpu_exec(CPUState *env);
601void kqemu_flush_page(CPUState *env, target_ulong addr);
602void kqemu_flush(CPUState *env, int global);
603void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
604void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
605void kqemu_cpu_interrupt(CPUState *env);
606void kqemu_record_dump(void);
607
608static inline int kqemu_is_ok(CPUState *env)
609{
610 return(env->kqemu_enabled &&
611 (env->cr[0] & CR0_PE_MASK) &&
612 !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
613 (env->eflags & IF_MASK) &&
614 !(env->eflags & VM_MASK) &&
615 (env->kqemu_enabled == 2 ||
616 ((env->hflags & HF_CPL_MASK) == 3 &&
617 (env->eflags & IOPL_MASK) != IOPL_MASK)));
618}
619
620#endif
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