| 1 | /*
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| 2 | * internal execution defines for qemu
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| 3 | *
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| 4 | * Copyright (c) 2003 Fabrice Bellard
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with this library; if not, write to the Free Software
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| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 19 | */
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| 20 |
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| 21 | /*
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| 22 | * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 23 | * other than GPL or LGPL is available it will apply instead, Sun elects to use only
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| 24 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 25 | * a choice of LGPL license versions is made available with the language indicating
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| 26 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 27 | * of the LGPL is applied is otherwise unspecified.
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| 28 | */
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| 29 |
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| 30 | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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| 31 | #ifndef VBOX
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| 32 | #define DEBUG_DISAS
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| 33 | #endif
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| 34 |
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| 35 | #ifdef VBOX
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| 36 | # include <VBox/tm.h>
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| 37 | # include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
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| 38 | # ifndef LOG_GROUP
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| 39 | # define LOG_GROUP LOG_GROUP_REM
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| 40 | # endif
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| 41 | # include <VBox/log.h>
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| 42 | # include "REMInternal.h"
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| 43 | # include <VBox/vm.h>
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| 44 | #endif /* VBOX */
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| 45 |
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| 46 | /* is_jmp field values */
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| 47 | #define DISAS_NEXT 0 /* next instruction can be analyzed */
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| 48 | #define DISAS_JUMP 1 /* only pc was modified dynamically */
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| 49 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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| 50 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */
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| 51 |
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| 52 | typedef struct TranslationBlock TranslationBlock;
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| 53 |
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| 54 | /* XXX: make safe guess about sizes */
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| 55 | #define MAX_OP_PER_INSTR 64
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| 56 | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
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| 57 | #define MAX_OPC_PARAM 10
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| 58 | #define OPC_BUF_SIZE 512
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| 59 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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| 60 |
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| 61 | /* Maximum size a TCG op can expand to. This is complicated because a
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| 62 | single op may require several host instructions and regirster reloads.
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| 63 | For now take a wild guess at 128 bytes, which should allow at least
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| 64 | a couple of fixup instructions per argument. */
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| 65 | #define TCG_MAX_OP_SIZE 128
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| 66 |
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| 67 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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| 68 |
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| 69 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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| 70 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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| 71 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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| 72 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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| 73 | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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| 74 | extern target_ulong gen_opc_jump_pc[2];
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| 75 | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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| 76 |
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| 77 | typedef void (GenOpFunc)(void);
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| 78 | typedef void (GenOpFunc1)(long);
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| 79 | typedef void (GenOpFunc2)(long, long);
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| 80 | typedef void (GenOpFunc3)(long, long, long);
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| 81 |
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| 82 | #include "qemu-log.h"
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| 83 |
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| 84 | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
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| 85 | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
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| 86 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
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| 87 | unsigned long searched_pc, int pc_pos, void *puc);
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| 88 |
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| 89 | unsigned long code_gen_max_block_size(void);
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| 90 | void cpu_gen_init(void);
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| 91 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
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| 92 | int *gen_code_size_ptr);
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| 93 | int cpu_restore_state(struct TranslationBlock *tb,
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| 94 | CPUState *env, unsigned long searched_pc,
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| 95 | void *puc);
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| 96 | int cpu_restore_state_copy(struct TranslationBlock *tb,
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| 97 | CPUState *env, unsigned long searched_pc,
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| 98 | void *puc);
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| 99 | void cpu_resume_from_signal(CPUState *env1, void *puc);
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| 100 | void cpu_io_recompile(CPUState *env, void *retaddr);
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| 101 | TranslationBlock *tb_gen_code(CPUState *env,
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| 102 | target_ulong pc, target_ulong cs_base, int flags,
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| 103 | int cflags);
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| 104 | void cpu_exec_init(CPUState *env);
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| 105 | int page_unprotect(target_ulong address, unsigned long pc, void *puc);
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| 106 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
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| 107 | int is_cpu_write_access);
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| 108 | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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| 109 | void tlb_flush_page(CPUState *env, target_ulong addr);
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| 110 | void tlb_flush(CPUState *env, int flush_global);
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| 111 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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| 112 | target_phys_addr_t paddr, int prot,
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| 113 | int mmu_idx, int is_softmmu);
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| 114 | #ifndef VBOX
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| 115 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
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| 116 | target_phys_addr_t paddr, int prot,
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| 117 | int mmu_idx, int is_softmmu)
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| 118 | #else
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| 119 | DECLINLINE(int) tlb_set_page(CPUState *env1, target_ulong vaddr,
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| 120 | target_phys_addr_t paddr, int prot,
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| 121 | int mmu_idx, int is_softmmu)
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| 122 | #endif
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| 123 | {
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| 124 | if (prot & PAGE_READ)
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| 125 | prot |= PAGE_EXEC;
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| 126 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
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| 127 | }
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| 128 |
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| 129 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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| 130 |
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| 131 | #define CODE_GEN_PHYS_HASH_BITS 15
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| 132 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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| 133 |
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| 134 | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
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| 135 |
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| 136 | /* estimated block size for TB allocation */
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| 137 | /* XXX: use a per code average code fragment size and modulate it
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| 138 | according to the host CPU */
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| 139 | #if defined(CONFIG_SOFTMMU)
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| 140 | #define CODE_GEN_AVG_BLOCK_SIZE 128
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| 141 | #else
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| 142 | #define CODE_GEN_AVG_BLOCK_SIZE 64
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| 143 | #endif
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| 144 |
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| 145 | #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
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| 146 | #define USE_DIRECT_JUMP
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| 147 | #endif
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| 148 | #if defined(__i386__) && !defined(_WIN32)
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| 149 | #define USE_DIRECT_JUMP
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| 150 | #endif
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| 151 |
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| 152 | #ifdef VBOX /* bird: not safe in next step because of threading & cpu_interrupt. */
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| 153 | #undef USE_DIRECT_JUMP
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| 154 | #endif /* VBOX */
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| 155 |
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| 156 | struct TranslationBlock {
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| 157 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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| 158 | target_ulong cs_base; /* CS base for this block */
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| 159 | uint64_t flags; /* flags defining in which context the code was generated */
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| 160 | uint16_t size; /* size of target code for this block (1 <=
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| 161 | size <= TARGET_PAGE_SIZE) */
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| 162 | uint16_t cflags; /* compile flags */
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| 163 | #define CF_COUNT_MASK 0x7fff
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| 164 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
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| 165 |
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| 166 | #ifdef VBOX
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| 167 | #define CF_RAW_MODE 0x0010 /* block was generated in raw mode */
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| 168 | #endif
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| 169 |
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| 170 | uint8_t *tc_ptr; /* pointer to the translated code */
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| 171 | /* next matching tb for physical address. */
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| 172 | struct TranslationBlock *phys_hash_next;
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| 173 | /* first and second physical page containing code. The lower bit
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| 174 | of the pointer tells the index in page_next[] */
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| 175 | struct TranslationBlock *page_next[2];
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| 176 | target_ulong page_addr[2];
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| 177 |
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| 178 | /* the following data are used to directly call another TB from
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| 179 | the code of this one. */
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| 180 | uint16_t tb_next_offset[2]; /* offset of original jump target */
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| 181 | #ifdef USE_DIRECT_JUMP
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| 182 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
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| 183 | #else
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| 184 | # if defined(VBOX) && defined(RT_OS_DARWIN) && defined(RT_ARCH_AMD64)
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| 185 | # error "First 4GB aren't reachable. jmp dword [tb_next] wont work."
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| 186 | # endif
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| 187 | unsigned long tb_next[2]; /* address of jump generated code */
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| 188 | #endif
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| 189 | /* list of TBs jumping to this one. This is a circular list using
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| 190 | the two least significant bits of the pointers to tell what is
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| 191 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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| 192 | jmp_first */
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| 193 | struct TranslationBlock *jmp_next[2];
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| 194 | struct TranslationBlock *jmp_first;
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| 195 | uint32_t icount;
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| 196 | };
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| 197 |
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| 198 | #ifndef VBOX
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| 199 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
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| 200 | #else
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| 201 | DECLINLINE(unsigned int) tb_jmp_cache_hash_page(target_ulong pc)
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| 202 | #endif
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| 203 | {
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| 204 | target_ulong tmp;
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| 205 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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| 206 | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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| 207 | }
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| 208 |
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| 209 | #ifndef VBOX
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| 210 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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| 211 | #else
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| 212 | DECLINLINE(unsigned int) tb_jmp_cache_hash_func(target_ulong pc)
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| 213 | #endif
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| 214 |
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| 215 | {
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| 216 | target_ulong tmp;
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| 217 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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| 218 | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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| 219 | (tmp & TB_JMP_ADDR_MASK));
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| 220 | }
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| 221 |
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| 222 | #ifndef VBOX
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| 223 | static inline unsigned int tb_phys_hash_func(unsigned long pc)
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| 224 | #else
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| 225 | DECLINLINE(unsigned int) tb_phys_hash_func(unsigned long pc)
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| 226 | #endif
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| 227 | {
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| 228 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
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| 229 | }
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| 230 |
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| 231 | TranslationBlock *tb_alloc(target_ulong pc);
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| 232 | void tb_free(TranslationBlock *tb);
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| 233 | void tb_flush(CPUState *env);
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| 234 | void tb_link_phys(TranslationBlock *tb,
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| 235 | target_ulong phys_pc, target_ulong phys_page2);
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| 236 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
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| 237 |
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| 238 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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| 239 |
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| 240 | extern uint8_t *code_gen_ptr;
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| 241 | extern int code_gen_max_blocks;
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| 242 |
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| 243 | #if defined(USE_DIRECT_JUMP)
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| 244 |
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| 245 | #if defined(__powerpc__)
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| 246 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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| 247 | {
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| 248 | uint32_t val, *ptr;
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| 249 |
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| 250 | /* patch the branch destination */
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| 251 | ptr = (uint32_t *)jmp_addr;
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| 252 | val = *ptr;
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| 253 | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
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| 254 | *ptr = val;
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| 255 | /* flush icache */
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| 256 | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
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| 257 | asm volatile ("sync" : : : "memory");
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| 258 | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
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| 259 | asm volatile ("sync" : : : "memory");
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| 260 | asm volatile ("isync" : : : "memory");
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| 261 | }
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| 262 | #elif defined(__i386__)
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| 263 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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| 264 | {
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| 265 | /* patch the branch destination */
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| 266 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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| 267 | /* no need to flush icache explicitely */
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| 268 | }
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| 269 | #endif
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| 270 |
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| 271 | static inline void tb_set_jmp_target(TranslationBlock *tb,
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| 272 | int n, unsigned long addr)
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| 273 | {
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| 274 | unsigned long offset;
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| 275 |
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| 276 | offset = tb->tb_jmp_offset[n];
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| 277 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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| 278 | offset = tb->tb_jmp_offset[n + 2];
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| 279 | if (offset != 0xffff)
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| 280 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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| 281 | }
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| 282 |
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| 283 | #else
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| 284 |
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| 285 | /* set the jump target */
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| 286 | #ifndef VBOX
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| 287 | static inline void tb_set_jmp_target(TranslationBlock *tb,
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| 288 | int n, unsigned long addr)
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| 289 | #else
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| 290 | DECLINLINE(void) tb_set_jmp_target(TranslationBlock *tb,
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| 291 | int n, unsigned long addr)
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| 292 | #endif
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| 293 | {
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| 294 | tb->tb_next[n] = addr;
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| 295 | }
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| 296 |
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| 297 | #endif
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| 298 |
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| 299 | #ifndef VBOX
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| 300 | static inline void tb_add_jump(TranslationBlock *tb, int n,
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| 301 | TranslationBlock *tb_next)
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| 302 | #else
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| 303 | DECLINLINE(void) tb_add_jump(TranslationBlock *tb, int n,
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| 304 | TranslationBlock *tb_next)
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| 305 | #endif
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| 306 | {
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| 307 | /* NOTE: this test is only needed for thread safety */
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| 308 | if (!tb->jmp_next[n]) {
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| 309 | /* patch the native jump address */
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| 310 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
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| 311 |
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| 312 | /* add in TB jmp circular list */
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| 313 | tb->jmp_next[n] = tb_next->jmp_first;
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| 314 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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| 315 | }
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| 316 | }
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| 317 |
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| 318 | TranslationBlock *tb_find_pc(unsigned long pc_ptr);
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| 319 |
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| 320 | #ifndef offsetof
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| 321 | #define offsetof(type, field) ((size_t) &((type *)0)->field)
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| 322 | #endif
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| 323 |
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| 324 | #if defined(_WIN32)
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| 325 | #define ASM_DATA_SECTION ".section \".data\"\n"
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| 326 | #define ASM_PREVIOUS_SECTION ".section .text\n"
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| 327 | #elif defined(__APPLE__)
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| 328 | #define ASM_DATA_SECTION ".data\n"
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| 329 | #define ASM_PREVIOUS_SECTION ".text\n"
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| 330 | #else
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| 331 | #define ASM_DATA_SECTION ".section \".data\"\n"
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| 332 | #define ASM_PREVIOUS_SECTION ".previous\n"
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| 333 | #endif
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| 334 |
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| 335 | #define ASM_OP_LABEL_NAME(n, opname) \
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| 336 | ASM_NAME(__op_label) #n "." ASM_NAME(opname)
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| 337 |
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| 338 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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| 339 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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| 340 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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| 341 |
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| 342 | #include "qemu-lock.h"
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| 343 |
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| 344 | extern spinlock_t tb_lock;
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| 345 |
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| 346 | extern int tb_invalidated_flag;
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| 347 |
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| 348 | #if !defined(CONFIG_USER_ONLY)
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| 349 |
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| 350 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
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| 351 | void *retaddr);
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| 352 |
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| 353 | #include "softmmu_defs.h"
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| 354 |
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| 355 | #define ACCESS_TYPE (NB_MMU_MODES + 1)
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| 356 | #define MEMSUFFIX _code
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| 357 | #define env cpu_single_env
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| 358 |
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| 359 | #define DATA_SIZE 1
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| 360 | #include "softmmu_header.h"
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| 361 |
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| 362 | #define DATA_SIZE 2
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| 363 | #include "softmmu_header.h"
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| 364 |
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| 365 | #define DATA_SIZE 4
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| 366 | #include "softmmu_header.h"
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| 367 |
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| 368 | #define DATA_SIZE 8
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| 369 | #include "softmmu_header.h"
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| 370 |
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| 371 | #undef ACCESS_TYPE
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| 372 | #undef MEMSUFFIX
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| 373 | #undef env
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| 374 |
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| 375 | #endif
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| 376 |
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| 377 | #if defined(CONFIG_USER_ONLY)
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| 378 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
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| 379 | {
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| 380 | return addr;
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| 381 | }
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| 382 | #else
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| 383 | # ifdef VBOX
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| 384 | target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry);
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| 385 | # if !defined(REM_PHYS_ADDR_IN_TLB)
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| 386 | target_ulong remR3HCVirt2GCPhys(CPUState *env1, void *addr);
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| 387 | # endif
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| 388 | # endif
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| 389 | /* NOTE: this function can trigger an exception */
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| 390 | /* NOTE2: the returned address is not exactly the physical address: it
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| 391 | is the offset relative to phys_ram_base */
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| 392 | #ifndef VBOX
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| 393 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
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| 394 | #else
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| 395 | DECLINLINE(target_ulong) get_phys_addr_code(CPUState *env1, target_ulong addr)
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| 396 | #endif
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| 397 | {
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| 398 | int mmu_idx, page_index, pd;
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| 399 |
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| 400 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 401 | mmu_idx = cpu_mmu_index(env1);
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| 402 | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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| 403 | (addr & TARGET_PAGE_MASK))) {
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| 404 | ldub_code(addr);
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| 405 | }
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| 406 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
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| 407 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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| 408 | # ifdef VBOX
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| 409 | /* deal with non-MMIO access handlers. */
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| 410 | return remR3PhysGetPhysicalAddressCode(env1, addr, &env1->tlb_table[mmu_idx][page_index]);
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| 411 | # elif defined(TARGET_SPARC) || defined(TARGET_MIPS)
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| 412 | do_unassigned_access(addr, 0, 1, 0, 4);
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| 413 | #else
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| 414 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
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| 415 | #endif
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| 416 | }
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| 417 |
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| 418 | # if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
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| 419 | return addr + env1->tlb_table[mmu_idx][page_index].addend;
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| 420 | # elif defined(VBOX)
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| 421 | return remR3HCVirt2GCPhys(env1, (void *)(addr + env1->tlb_table[mmu_idx][page_index].addend));
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| 422 | # else
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| 423 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
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| 424 | # endif
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| 425 | }
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| 426 |
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| 427 |
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| 428 | /* Deterministic execution requires that IO only be performed on the last
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| 429 | instruction of a TB so that interrupts take effect immediately. */
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| 430 | #ifndef VBOX
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| 431 | static inline int can_do_io(CPUState *env)
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| 432 | #else
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| 433 | DECLINLINE(int) can_do_io(CPUState *env)
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| 434 | #endif
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| 435 | {
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| 436 | if (!use_icount)
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| 437 | return 1;
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| 438 |
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| 439 | /* If not executing code then assume we are ok. */
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| 440 | if (!env->current_tb)
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| 441 | return 1;
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| 442 |
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| 443 | return env->can_do_io != 0;
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| 444 | }
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| 445 | #endif
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| 446 |
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| 447 |
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| 448 | #ifdef USE_KQEMU
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| 449 | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
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| 450 |
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| 451 | int kqemu_init(CPUState *env);
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| 452 | int kqemu_cpu_exec(CPUState *env);
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| 453 | void kqemu_flush_page(CPUState *env, target_ulong addr);
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| 454 | void kqemu_flush(CPUState *env, int global);
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| 455 | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
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| 456 | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
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| 457 | void kqemu_cpu_interrupt(CPUState *env);
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| 458 | void kqemu_record_dump(void);
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| 459 |
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| 460 | static inline int kqemu_is_ok(CPUState *env)
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| 461 | {
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| 462 | return(env->kqemu_enabled &&
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| 463 | (env->cr[0] & CR0_PE_MASK) &&
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| 464 | !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
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| 465 | (env->eflags & IF_MASK) &&
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| 466 | !(env->eflags & VM_MASK) &&
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|---|
| 467 | (env->kqemu_enabled == 2 ||
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| 468 | ((env->hflags & HF_CPL_MASK) == 3 &&
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| 469 | (env->eflags & IOPL_MASK) != IOPL_MASK)));
|
|---|
| 470 | }
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|---|
| 471 |
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|---|
| 472 | #endif
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