儲存庫 vbox 的更動 105862

時間撮記:

2024-8-26 上午10:27:35 (3 月 以前)

作者:

vboxsync

訊息:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]hsubps (W.I.P)

檔案:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (修改) (2 筆差異)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -5715 +5715 @@
               /*256:out  */ X86_MXCSR_IM,
               /*xcpt?    */ false, false },
-#if 0
-          { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_INF(1), FP32_0(0),   FP32_0(0)   } },
-            { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
-            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0)   } },
+          { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1),  FP32_0(0),    FP32_0(0)   } },
+            { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0),  FP32_INF(0),  FP32_INF(0) } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0)   } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_INF(0),  FP32_INF(1), FP32_INF(0),  FP32_INF(1),  FP32_INF(1),  FP32_INF(1), FP32_0(0),   FP32_0(0)   } },
-            { /*src1     */ { FP32_INF(1),  FP32_INF(0), FP32_0(0),    FP32_0(0),    FP32_INF(1),  FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
-            { /* =>      */ { FP32_QNAN(1), FP32_0(0),   FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0)   } },
+          { { /*src2     */ { FP32_INF(0),  FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1),  FP32_0(0),    FP32_0(0)   } },
+            { /*src1     */ { FP32_INF(1),  FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_INF(1), FP32_INF(0),  FP32_INF(0),  FP32_INF(0) } },
+            { /* =>      */ { FP32_INF(1), FP32_0(0),    FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0)   } },
               /*mxcsr:in */ X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
-              /*xcpt?    */ true, true },
-          { { /*src2     */ { FP32_INF(1),  FP32_INF(1), FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0)   } },
-            { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
-            { /* =>      */ { FP32_INF(0),  FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_INF(1), FP32_INF(0) } },
-              /*mxcsr:in */ 0,
-              /*128:out  */ 0,
-              /*256:out  */ 0,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_INF(0),  FP32_QNAN(1), FP32_INF(1),  FP32_QNAN(0), FP32_INF(1),  FP32_INF(1),  FP32_0(0),   FP32_0(0)   } },
-            { /*src1     */ { FP32_INF(0),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } },
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0),  FP32_INF(1), FP32_0(0)   } },
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0)   } },
+            { /*src1     */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
+            { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_INF(1), FP32_INF(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP32_INF(0),  FP32_QNAN(1), FP32_INF(1),  FP32_QNAN(0), FP32_INF(1),  FP32_INF(1),  FP32_0(0),    FP32_0(0)   } },
+            { /*src1     */ { FP32_INF(0),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(1), FP32_INF(0),  FP32_INF(0) } },
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0)   } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*xcpt?    */ false, false },
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+#if 0
     /*
      * Overflow, Precision.
@@ -7876 +7876 @@
         { "[v]subss",       bs3CpuInstr4_v_subss,  0 },
         { "[v]subsd",       bs3CpuInstr4_v_subsd,  0 },
-#if 0
         { "[v]hsubps",      bs3CpuInstr4_v_hsubps, 0 },
-#endif
         { "[v]mulps",       bs3CpuInstr4_v_mulps,  0 },
         { "[v]mulpd",       bs3CpuInstr4_v_mulpd,  0 },