VirtualBox

儲存庫 vbox 的更動 13991


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時間撮記:
2008-11-10 上午10:36:38 (16 年 以前)
作者:
vboxsync
訊息:

#1865: More PGM cleanup.

位置:
trunk
檔案:
修改 10 筆資料

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  • trunk/include/VBox/pgm.h

    r13970 r13991  
    327327VMMDECL(int)        PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
    328328VMMDECL(int)        PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
    329 VMMDECL(int)        PGMShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
    330 VMMDECL(int)        PGMShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
    331 VMMDECL(int)        PGMShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
    332 VMMDECL(int)        PGMShwSyncPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
    333 VMMDECL(int)        PGMShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
    334329VMMDECL(int)        PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
    335330VMMDECL(bool)       PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr);

  • trunk/src/VBox/VMM/PGM.cpp

    r13937 r13991  
    14201420    pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
    14211421    AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
    1422     pVM->pgm.s.pHCPaePDPT    = (PX86PDPT)MMR3PageAllocLow(pVM);
    1423     pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
     1422    pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
     1423//#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     1424//    pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
     1425//#endif
     1426    pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
     1427#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     1428    pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
     1429#endif
    14241430
    14251431    if (    !pVM->pgm.s.pHC32BitPD
    … …  
    14291435        ||  !pVM->pgm.s.apHCPaePDs[3]
    14301436        ||  !pVM->pgm.s.pHCPaePDPT
    1431         ||  !pVM->pgm.s.pHCNestedRoot)
     1437        ||  !pVM->pgm.s.pShwNestedRootR3)
    14321438    {
    14331439        AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
    … …  
    14431449    pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
    14441450    pVM->pgm.s.HCPhysPaePDPT    = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
    1445     pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
     1451    pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
    14461452
    14471453    /*
    … …  
    14501456    ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
    14511457    ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
    1452     ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
     1458    ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
    14531459    for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
    14541460    {

  • trunk/src/VBox/VMM/PGMInternal.h

    r13969 r13991  
    20872087    RTRCPTR                         alignment5; /**< structure size alignment. */
    20882088#endif
    2089     /** The Page Map Level 4 table - HC Ptr. */
    2090 #if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
    2091     R3PTRTYPE(PX86PML4)             pHCPaePML4;
    2092 #else
    2093     R3R0PTRTYPE(PX86PML4)           pHCPaePML4;
     2089    /** The Page Map Level 4 table - R3 Ptr. */
     2090    R3PTRTYPE(PX86PML4)             pShwPaePml4R3;
     2091#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     2092    /** The Page Map Level 4 table - R0 Ptr. */
     2093    R0PTRTYPE(PX86PML4)             pShwPaePml4R0;
    20942094#endif
    20952095    /** The Physical Address (HC) of the Page Map Level 4 table. */
    … …  
    21012101    R3R0PTRTYPE(PPGMPOOLPAGE)       pHCShwAmd64CR3;
    21022102#endif
    2103 
    21042103    /** @}*/
    21052104
    21062105    /** @name Nested Shadow Paging
    21072106     * @{ */
    2108     /** Root table; format depends on the host paging mode (AMD-V) or EPT */
    2109 #if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
    2110     R3PTRTYPE(void *)               pHCNestedRoot;
    2111 #else
    2112     R3R0PTRTYPE(void *)             pHCNestedRoot;
     2107    /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
     2108    RTR3PTR                         pShwNestedRootR3;
     2109#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     2110    /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
     2111    RTR0PTR                         pShwNestedRootR0;
    21132112#endif
    21142113    /** The Physical Address (HC) of the nested paging root. */
    21152114    RTHCPHYS                        HCPhysNestedRoot;
     2115    /** @}  */
    21162116
    21172117    /** @name Function pointers for Shadow paging.
    … …  
    35823582 * @returns Pointer to the PML4 entry.
    35833583 * @param   pPGM        Pointer to the PGM instance data.
    3584  * @param   iPml4e      The index.
    3585  */
    3586 DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4e)
     3584 * @param   iPml4       The index.
     3585 */
     3586DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
    35873587{
    35883588#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    … …  
    35903590    int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
    35913591    AssertRCReturn(rc, NULL);
    3592     return &pGuestPml4->a[iPml4e];
     3592    return &pGuestPml4->a[iPml4];
    35933593#else
    35943594    Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
    3595     return &pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4e];
     3595    return &pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4];
    35963596#endif
    35973597}
    … …  
    36033603 * @returns The PML4 entry.
    36043604 * @param   pPGM        Pointer to the PGM instance data.
    3605  * @param   iPml4e      The index.
    3606  */
    3607 DECLINLINE(X86PGPAEUINT) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4e)
     3605 * @param   iPml4       The index.
     3606 */
     3607DECLINLINE(X86PGPAEUINT) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
    36083608{
    36093609#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    … …  
    36113611    int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
    36123612    AssertRCReturn(rc, 0);
    3613     return pGuestPml4->a[iPml4e].u;
     3613    return pGuestPml4->a[iPml4].u;
    36143614#else
    36153615    Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
    3616     return pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4e].u;
     3616    return pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4].u;
    36173617#endif
    36183618}
    … …  
    36313631{
    36323632    PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
    3633     const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3634     PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4e];
     3633    const unsigned  iPml4  = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3634    PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
    36353635    if (pPml4e->n.u1Present)
    36363636    {
    … …  
    36593659{
    36603660    PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
    3661     const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3662     PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4e];
     3661    const unsigned  iPml4  = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3662    PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
    36633663    if (pPml4e->n.u1Present)
    36643664    {
    … …  
    36943694{
    36953695    PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
    3696     const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3697     if (pGuestPml4->a[iPml4e].n.u1Present)
     3696    const unsigned  iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3697    if (pGuestPml4->a[iPml4].n.u1Present)
    36983698    {
    36993699        PCX86PDPT   pPdptTemp;
    3700         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
     3700        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
    37013701        AssertRCReturn(rc, 0);
    37023702
    … …  
    37273727{
    37283728    PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
    3729     const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3730     if (pGuestPml4->a[iPml4e].n.u1Present)
     3729    const unsigned  iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3730    if (pGuestPml4->a[iPml4].n.u1Present)
    37313731    {
    37323732        PCX86PDPT   pPdptTemp;
    3733         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
     3733        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
    37343734        AssertRCReturn(rc, NULL);
    37353735
    … …  
    37633763{
    37643764    PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
    3765     const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3766     PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4e];
     3765    const unsigned  iPml4  = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3766    PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
    37673767    if (pPml4e->n.u1Present)
    37683768    {
    … …  
    37863786}
    37873787
     3788#ifndef IN_RC
     3789
     3790
     3791/**
     3792 * Gets the shadow page map level-4 pointer.
     3793 *
     3794 * @returns Pointer to the shadow PML4.
     3795 * @param   pPGM        Pointer to the PGM instance data.
     3796 */
     3797DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
     3798{
     3799#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_R0
     3800    PX86PML4 pShwPml4;
     3801    Assert(pPGM->HCPhysPaePML4 != 0 && pPGM->HCPhysPaePML4 != NIL_RTHCPHYS);
     3802    int rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysPaePML4, &pShwPml4);
     3803    AssertRCReturn(rc, 0);
     3804    return pShwPml4;
     3805#else
     3806    Assert(pPGM->CTX_SUFF(pShwPaePml4));
     3807    return pPGM->CTX_SUFF(pShwPaePml4);
     3808#endif
     3809}
     3810
     3811
     3812/**
     3813 * Gets the shadow page map level-4 entry for the specified address.
     3814 *
     3815 * @returns The entry.
     3816 * @param   pPGM        Pointer to the PGM instance data.
     3817 * @param   GCPtr       The address.
     3818 */
     3819DECLINLINE(X86PGPAEUINT) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
     3820{
     3821    const unsigned  iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3822# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_R0
     3823    PCX86PML4       pShwPml4;
     3824    Assert(pPGM->HCPhysPaePML4 != 0 && pPGM->HCPhysPaePML4 != NIL_RTHCPHYS);
     3825    int rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysPaePML4, &pShwPml4);
     3826    AssertRCReturn(rc, 0);
     3827    return pShwPml4->a[iPml4].u;
     3828# else
     3829    Assert(pPGM->CTX_SUFF(pShwPaePml4));
     3830    return pPGM->CTX_SUFF(pShwPaePml4)->a[iPml4].u;
     3831# endif
     3832}
     3833
     3834
     3835/**
     3836 * Gets the pointer to the specified shadow page map level-4 entry.
     3837 *
     3838 * @returns The entry.
     3839 * @param   pPGM        Pointer to the PGM instance data.
     3840 * @param   iPml4       The PML4 index.
     3841 */
     3842DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
     3843{
     3844# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_R0
     3845    PX86PML4        pShwPml4;
     3846    Assert(pPGM->HCPhysPaePML4 != 0 && pPGM->HCPhysPaePML4 != NIL_RTHCPHYS);
     3847    int rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysPaePML4, &pShwPml4);
     3848    AssertRCReturn(rc, 0);
     3849    return &pShwPml4->a[iPml4];
     3850# else
     3851    Assert(pPGM->CTX_SUFF(pShwPaePml4));
     3852    return &pPGM->CTX_SUFF(pShwPaePml4)->a[iPml4];
     3853# endif
     3854}
     3855
     3856#endif /* IN_RC */
    37883857
    37893858/**
    … …  
    37993868{
    38003869    PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
    3801     const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3802     if (pGuestPml4->a[iPml4e].n.u1Present)
     3870    const unsigned  iPml4  = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3871    if (pGuestPml4->a[iPml4].n.u1Present)
    38033872    {
    38043873        PCX86PDPT   pPdptTemp;
    3805         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
     3874        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
    38063875        AssertRCReturn(rc, NULL);
    38073876

  • trunk/src/VBox/VMM/PGMPool.cpp

    r13824 r13991  
    286286    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].Core.Key  = NIL_RTHCPHYS;
    287287    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].GCPhys    = NIL_RTGCPHYS;
    288     pPool->aPages[PGMPOOL_IDX_AMD64_CR3].pvPageR3  = pVM->pgm.s.pHCPaePDPT;     /* not used */
     288    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].pvPageR3  = pVM->pgm.s.pHCPaePDPT;     /* not used - isn't it wrong as well? */
    289289    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].enmKind   = PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4;
    290290    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].idx       = PGMPOOL_IDX_AMD64_CR3;
    … …  
    293293    pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].Core.Key  = NIL_RTHCPHYS;
    294294    pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].GCPhys    = NIL_RTGCPHYS;
    295     pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].pvPageR3  = pVM->pgm.s.pHCNestedRoot;
     295    pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].pvPageR3  = pVM->pgm.s.pShwNestedRootR3;
    296296    pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].enmKind   = PGMPOOLKIND_ROOT_NESTED;
    297297    pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].idx       = PGMPOOL_IDX_NESTED_ROOT;

  • trunk/src/VBox/VMM/PGMShw.h

    r13936 r13991  
    141141    Assert(HWACCMIsNestedPagingActive(pVM));
    142142
    143     Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVM->pgm.s.pHCNestedRoot, pVM->pgm.s.HCPhysNestedRoot));
     143    Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVM->pgm.s.pShwNestedRootR3, pVM->pgm.s.HCPhysNestedRoot));
    144144    /* In non-nested mode we allocate the PML4 page on-demand; in nested mode we just use our fixed nested paging root. */
    145     pVM->pgm.s.pHCPaePML4    = (PX86PML4)pVM->pgm.s.pHCNestedRoot;
     145    pVM->pgm.s.pShwPaePml4R3 = (R3PTRTYPE(PX86PML4))pVM->pgm.s.pShwNestedRootR3;
     146# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     147    pVM->pgm.s.pShwPaePml4R0 = (R0PTRTYPE(PX86PML4))pVM->pgm.s.pShwNestedRootR0;
     148# endif
    146149    pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.HCPhysNestedRoot;
    147150#endif
    … …  
    174177#if PGM_SHW_TYPE == PGM_TYPE_NESTED
    175178    Assert(HWACCMIsNestedPagingActive(pVM));
    176     pVM->pgm.s.pHCPaePML4    = 0;
     179    pVM->pgm.s.pShwPaePml4R3 = 0;
     180# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     181    pVM->pgm.s.pShwPaePml4R0 = 0;
     182# endif
    177183    pVM->pgm.s.HCPhysPaePML4 = 0;
    178184    Log(("Leave nested shadow paging mode\n"));

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r13969 r13991  
    6969*   Internal Functions                                                         *
    7070*******************************************************************************/
     71DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
     72DECLINLINE(int) pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
     73DECLINLINE(int) pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
     74DECLINLINE(int) pgmShwSyncPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
     75DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
     76
    7177
    7278/*
    … …  
    808814 * @param   pGstPdpe    Guest PDPT entry
    809815 * @param   ppPD        Receives address of page directory
    810  */
    811 VMMDECL(int) PGMShwSyncPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
     816 * @remarks Unused.
     817 */
     818DECLINLINE(int) pgmShwSyncPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
    812819{
    813820    PPGM           pPGM   = &pVM->pgm.s;
    … …  
    845852    }
    846853    /* The PD was cached or created; hook it up now. */
    847     pPdpe->u |=    pShwPage->Core.Key
    848                 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
     854    pPdpe->u |= pShwPage->Core.Key
     855             | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
    849856
    850857    *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
    … …  
    861868 * @param   ppPdpt      Receives address of pdpt
    862869 * @param   ppPD        Receives address of page directory
    863  */
    864 VMMDECL(int) PGMShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
     870 * @remarks Unused.
     871 */
     872DECLINLINE(int) pgmShwGetPAEPDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
    865873{
    866874    PPGM           pPGM   = &pVM->pgm.s;
    … …  
    902910 * @param   ppPD        Receives address of page directory
    903911 */
    904 VMMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
    905 {
    906     PPGM           pPGM   = &pVM->pgm.s;
    907     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    908     PPGMPOOL       pPool  = pPGM->CTX_SUFF(pPool);
    909     PX86PML4E      pPml4e;
     912DECLINLINE(int) pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
     913{
     914    PPGM           pPGM          = &pVM->pgm.s;
     915    PPGMPOOL       pPool         = pPGM->CTX_SUFF(pPool);
     916    const unsigned iPml4         = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     917    PX86PML4E      pPml4e        = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
     918    bool           fNestedPaging = HWACCMIsNestedPagingActive(pVM);
    910919    PPGMPOOLPAGE   pShwPage;
    911920    X86PML4E       Pml4eGst;
    912921    int            rc;
    913     bool           fNestedPaging = HWACCMIsNestedPagingActive(pVM);
    914 
    915     Assert(pVM->pgm.s.pHCPaePML4);
    916922
    917923    /* Allocate page directory pointer table if not present. */
    918     pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
    919924    if (    !pPml4e->n.u1Present
    920925        &&  !(pPml4e->u & X86_PML4E_PG_MASK))
    921926    {
    922927        Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
    923 
    924928        if (!fNestedPaging)
    925929        {
    … …  
    928932             *        are fine.) */
    929933            Assert(pVM->pgm.s.pHCShwAmd64CR3);
    930             Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4e);
     934            Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4);
    931935
    932936            rc = pgmPoolAlloc(pVM, Pml4eGst.u & X86_PML4E_PG_MASK,
    933                               PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
     937                              PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4, &pShwPage);
    934938        }
    935939        else
    936940            rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */,
    937                               PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
     941                              PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
    938942
    939943        if (rc == VERR_PGM_POOL_FLUSHED)
    … …  
    967971            /** @todo why are we looking up the guest PDPTE here?  Isn't pGstPdpe
    968972             *        trustworthy? */
    969             Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4e);
     973            Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4);
    970974            PX86PDPT pPdptGst;
    971975            rc = PGM_GCPHYS_2_PTR(pVM, Pml4eGst.u & X86_PML4E_PG_MASK, &pPdptGst);
    … …  
    10031007
    10041008/**
    1005  * Gets the SHADOW page directory pointer for the specified address.
     1009 * Gets the SHADOW page directory pointer for the specified address (long mode).
    10061010 *
    10071011 * @returns VBox status.
    … …  
    10111015 * @param   ppPD        Receives address of page directory
    10121016 */
    1013 VMMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
    1014 {
    1015     PPGM           pPGM   = &pVM->pgm.s;
    1016     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    1017     PPGMPOOL       pPool  = pPGM->CTX_SUFF(pPool);
    1018     PX86PML4E      pPml4e;
    1019     PPGMPOOLPAGE   pShwPage;
    1020 
    1021     AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
    1022 
    1023     pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
     1017DECLINLINE(int) pgmShwGetLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
     1018{
     1019    PPGM            pPGM = &pVM->pgm.s;
     1020    const unsigned  iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     1021    PCX86PML4E      pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
     1022    AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
     1023    if (ppPml4e)
     1024        *ppPml4e = (PX86PML4E)pPml4e;
    10241025    if (!pPml4e->n.u1Present)
    10251026        return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
    10261027
    1027     pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
     1028    PPGMPOOL        pPool = pPGM->CTX_SUFF(pPool);
     1029    PPGMPOOLPAGE    pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
    10281030    AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
    10291031
    1030     const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    1031     PX86PDPT  pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
    1032     PX86PDPE  pPdpe = &pPdpt->a[iPdPt];
    1033 
    1034     *ppPdpt = pPdpt;
    1035     if (!pPdpe->n.u1Present)
     1032    const unsigned  iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     1033    PCX86PDPT       pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
     1034    if (!pPdpt->a[iPdPt].n.u1Present)
    10361035        return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
    10371036
    1038     pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
     1037    pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
    10391038    AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
    10401039
    … …  
    10541053 * @param   ppPD        Receives address of page directory
    10551054 */
    1056 VMMDECL(int) PGMShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
    1057 {
    1058     PPGM           pPGM   = &pVM->pgm.s;
    1059     const unsigned iPml4e = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
    1060     PPGMPOOL       pPool  = pPGM->CTX_SUFF(pPool);
    1061     PEPTPML4       pPml4  = (PEPTPML4)pPGM->pHCNestedRoot;
     1055DECLINLINE(int) pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
     1056{
     1057    PPGM           pPGM  = &pVM->pgm.s;
     1058    const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
     1059    PPGMPOOL       pPool = pPGM->CTX_SUFF(pPool);
     1060    PEPTPML4       pPml4;
    10621061    PEPTPML4E      pPml4e;
    10631062    PPGMPOOLPAGE   pShwPage;
    … …  
    10651064
    10661065    Assert(HWACCMIsNestedPagingActive(pVM));
     1066
     1067# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_R0
     1068    rc = PGM_HCPHYS_2_PTR(pVM, pPGM->HCPhysNestedRoot, &pPml4);
     1069    AssertRCReturn(rc);
     1070# else
     1071    pPml4 = (PEPTPML4)pPGM->CTX_SUFF(pShwNestedRoot);
     1072# endif
    10671073    Assert(pPml4);
    10681074
    10691075    /* Allocate page directory pointer table if not present. */
    1070     pPml4e = &pPml4->a[iPml4e];
     1076    pPml4e = &pPml4->a[iPml4];
    10711077    if (    !pPml4e->n.u1Present
    10721078        &&  !(pPml4e->u & EPT_PML4E_PG_MASK))
    … …  
    10741080        Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
    10751081
    1076         rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PML4E_PG_MASK) + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
     1082        rc = pgmPoolAlloc(pVM, (GCPtr & EPT_PML4E_PG_MASK) + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
    10771083        if (rc == VERR_PGM_POOL_FLUSHED)
    10781084        {

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r13937 r13991  
    170170#   endif
    171171
    172     rc = PGMShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
     172    rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
    173173    if (rc != VINF_SUCCESS)
    174174    {
    … …  
    182182    PEPTPD          pPDDst;
    183183
    184     rc = PGMShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
     184    rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
    185185    if (rc != VINF_SUCCESS)
    186186    {
    … …  
    910910# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
    911911    /* PML4 */
    912     AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
    913 
    914     const unsigned  iPml4e    = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
     912    AssertReturn(pVM->pgm.s.pShwPaePml4R3, VERR_INTERNAL_ERROR);
     913
     914    const unsigned  iPml4     = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
    915915    const unsigned  iPdpte    = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    916916    const unsigned  iPDDst    = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
    917917    PX86PDPAE       pPDDst;
    918918    PX86PDPT        pPdptDst;
    919     PX86PML4E       pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
    920     rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
     919    PX86PML4E       pPml4eDst;
     920    rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
    921921    if (rc != VINF_SUCCESS)
    922922    {
    … …  
    10211021        LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    10221022                 GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    1023         pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
     1023        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4);
    10241024        pPml4eDst->u = 0;
    10251025        STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
    … …  
    10351035        LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    10361036                 GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    1037         pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
     1037        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4);
    10381038        pPml4eDst->u = 0;
    10391039        STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
    … …  
    10471047        LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    10481048                 GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    1049         pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
     1049        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4);
    10501050        pPml4eDst->u = 0;
    10511051        STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
    … …  
    16021602    PX86PDPT        pPdptDst;
    16031603
    1604     int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
     1604    int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
    16051605    AssertRCSuccessReturn(rc, rc);
    16061606    Assert(pPDDst && pPdptDst);
    … …  
    18671867    PX86PDPT        pPdptDst;
    18681868
    1869     int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
     1869    int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
    18701870    AssertRCSuccessReturn(rc, rc);
    18711871    Assert(pPDDst && pPdptDst);
    … …  
    18761876    EPTPDE          PdeDst;
    18771877
    1878     int rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
     1878    int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
    18791879    if (rc != VINF_SUCCESS)
    18801880    {
    … …  
    23232323    PX86PDPAE       pPDDst;
    23242324    PX86PDPT        pPdptDst;
    2325     rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
     2325    rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
    23262326    AssertRCSuccessReturn(rc, rc);
    23272327    Assert(pPDDst);
    … …  
    27082708    PX86PDPAE       pPDDst;
    27092709    PX86PDPT        pPdptDst;
    2710     rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
     2710    rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
    27112711    AssertRCSuccessReturn(rc, rc);
    27122712    Assert(pPDDst);
    … …  
    27212721    PEPTPDPT        pPdptDst;
    27222722
    2723     rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
     2723    rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
    27242724    if (rc != VINF_SUCCESS)
    27252725    {
    … …  
    28632863#  endif
    28642864
    2865         int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
     2865        int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
    28662866        if (rc != VINF_SUCCESS)
    28672867        {
    … …  
    29832983#  endif
    29842984
    2985     rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
     2985    rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
    29862986    if (rc != VINF_SUCCESS)
    29872987    {
    … …  
    31893189    }
    31903190#  if PGM_GST_TYPE == PGM_TYPE_AMD64
    3191     for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
     3191    for (uint64_t iPml4 = 0; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
    31923192    {
    31933193        PPGMPOOLPAGE pShwPdpt = NULL;
    … …  
    31953195        RTGCPHYS     GCPhysPdptSrc;
    31963196
    3197         pPml4eSrc     = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
    3198         pPml4eDst     = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
     3197        pPml4eSrc     = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4];
     3198        pPml4eDst     = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4];
    31993199
    32003200        /* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
    … …  
    32113211            /* Free it. */
    32123212            LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%RX64 %RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
    3213                      (uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    3214             pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
     3213                     (uint64_t)iPml4 << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
     3214            pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4);
    32153215            pPml4eDst->u = 0;
    32163216            continue;
    … …  
    32653265            PX86PDPAE       pPDDst;
    32663266            PX86PDEPAE      pPDEDst;
    3267             RTGCPTR         GCPtr   = (iPml4e << X86_PML4_SHIFT) || (iPdpte << X86_PDPT_SHIFT);
     3267            RTGCPTR         GCPtr   = (iPml4 << X86_PML4_SHIFT) || (iPdpte << X86_PDPT_SHIFT);
    32683268            PGSTPD          pPDSrc  = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
    32693269
    3270             int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
     3270            int rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
    32713271            if (rc != VINF_SUCCESS)
    32723272            {
    … …  
    32963296                /* Free it. */
    32973297                LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%RX64 %RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
    3298                         ((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
     3298                        ((uint64_t)iPml4 << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
    32993299
    33003300                /* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
    … …  
    37003700
    37013701# if PGM_GST_TYPE == PGM_TYPE_AMD64
    3702     unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3703 
    3704     for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
     3702    unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3703
     3704    for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
    37053705    {
    37063706        PPGMPOOLPAGE    pShwPdpt = NULL;
    … …  
    37093709        RTGCPHYS        GCPhysPdptSrc;
    37103710
    3711         pPml4eSrc     = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4e);
    3712         pPml4eDst     = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
     3711        pPml4eSrc     = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
     3712        pPml4eDst     = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
    37133713
    37143714        /* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
    … …  
    37363736        if (GCPhysPdptSrc != pShwPdpt->GCPhys)
    37373737        {
    3738             AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
     3738            AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
    37393739            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
    37403740            cErrors++;
    … …  
    37793779            PGSTPD          pPDSrc    = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
    37803780
    3781             rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
     3781            rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
    37823782            if (rc != VINF_SUCCESS)
    37833783            {
    … …  
    38123812            {
    38133813#  if PGM_GST_TYPE == PGM_TYPE_AMD64
    3814                 AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
     3814                AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
    38153815#  else
    38163816                AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));

  • trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

    r13937 r13991  
    520520                        pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
    521521                    pVM->pgm.s.pHCShwAmd64CR3 = 0;
    522                     pVM->pgm.s.pHCPaePML4     = 0;
     522                    pVM->pgm.s.pShwPaePml4R3  = 0;
     523#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     524                    pVM->pgm.s.pShwPaePml4R0  = 0;
     525#  endif
    523526                    pVM->pgm.s.HCPhysPaePML4  = 0;
    524527                }
    … …  
    535538                    goto l_try_again;
    536539                }
    537                 pVM->pgm.s.pHCPaePML4    = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
     540                pVM->pgm.s.pShwPaePml4R3 = (R3PTRTYPE(PX86PML4))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
     541#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     542                pVM->pgm.s.pShwPaePml4R0 = (R0PTRTYPE(PX86PML4))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
     543#  endif
    538544                pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.pHCShwAmd64CR3->Core.Key;
    539545            }
    … …  
    595601    if (!HWACCMIsNestedPagingActive(pVM))
    596602    {
    597         pVM->pgm.s.pHCPaePML4    = 0;
     603        pVM->pgm.s.pShwPaePml4R3 = 0;
     604# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     605        pVM->pgm.s.pShwPaePml4R0 = 0;
     606# endif
    598607        pVM->pgm.s.HCPhysPaePML4 = 0;
    599608        if (pVM->pgm.s.pHCShwAmd64CR3)

  • trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

    r13823 r13991  
    149149
    150150    /* PML4 */
    151     const unsigned  iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    152     X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
     151    X86PML4E        Pml4e;
     152    Pml4e.u = pgmShwGetLongModePML4E(&pVM->pgm.s, GCPtr);
    153153    if (!Pml4e.n.u1Present)
    154154        return VERR_PAGE_TABLE_NOT_PRESENT;
    … …  
    189189    EPTPDE          Pde;
    190190
    191     int rc = PGMShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
     191    int rc = pgmShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
    192192    if (rc != VINF_SUCCESS)
    193193    {
    … …  
    296296        X86PDEPAE       Pde;
    297297        /* PML4 */
    298         const unsigned  iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    299         X86PML4E        Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
     298        X86PML4E        Pml4e;
     299        Pml4e.u = pgmShwGetLongModePML4E(&pVM->pgm.s, GCPtr);
    300300        if (!Pml4e.n.u1Present)
    301301            return VERR_PAGE_TABLE_NOT_PRESENT;
    … …  
    329329        EPTPDE          Pde;
    330330
    331         rc = PGMShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
     331        rc = pgmShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
    332332        if (rc != VINF_SUCCESS)
    333333        {

  • trunk/src/VBox/VMM/testcase/tstVMStructGC.cpp

    r13933 r13991  
    422422    GEN_CHECK_OFF(PGM, pGCPaePDPT);
    423423    GEN_CHECK_OFF(PGM, HCPhysPaePDPT);
    424     GEN_CHECK_OFF(PGM, pHCPaePML4);
     424    GEN_CHECK_OFF(PGM, pShwPaePml4R3);
     425#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     426    GEN_CHECK_OFF(PGM, pShwPaePml4R0);
     427#endif
    425428    GEN_CHECK_OFF(PGM, HCPhysPaePML4);
    426429    GEN_CHECK_OFF(PGM, pfnR3ShwRelocate);
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