VirtualBox

儲存庫 vbox 的更動 42174


忽略:
時間撮記:
2012-7-17 上午11:03:40 (12 年 以前)
作者:
vboxsync
訊息:

VMM/HWSVMR0: cosmetics.

位置:
trunk
檔案:
修改 2 筆資料

圖例:

未更動
新增
刪除

  • trunk/include/VBox/vmm/hwacc_svm.h

    r41277 r42174  
    285285 * @{
    286286 */
    287 /** 0 Intercept INTR (physical maskable interrupt) */
     287/** 0 Intercept INTR (physical maskable interrupt). */
    288288#define SVM_CTRL1_INTERCEPT_INTR              RT_BIT(0)
    289 /** 1 Intercept NMI */
     289/** 1 Intercept NMI. */
    290290#define SVM_CTRL1_INTERCEPT_NMI               RT_BIT(1)
    291 /** 2 Intercept SMI */
     291/** 2 Intercept SMI. */
    292292#define SVM_CTRL1_INTERCEPT_SMI               RT_BIT(2)
    293 /** 3 Intercept INIT */
     293/** 3 Intercept INIT. */
    294294#define SVM_CTRL1_INTERCEPT_INIT              RT_BIT(3)
    295 /** 4 Intercept VINTR (virtual maskable interrupt) */
     295/** 4 Intercept VINTR (virtual maskable interrupt). */
    296296#define SVM_CTRL1_INTERCEPT_VINTR             RT_BIT(4)
    297297/** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
    298298#define SVM_CTRL1_INTERCEPT_CR0               RT_BIT(5)
    299 /** 6 Intercept reads of IDTR */
     299/** 6 Intercept reads of IDTR. */
    300300#define SVM_CTRL1_INTERCEPT_IDTR_READS        RT_BIT(6)
    301 /** 7 Intercept reads of GDTR */
     301/** 7 Intercept reads of GDTR. */
    302302#define SVM_CTRL1_INTERCEPT_GDTR_READS        RT_BIT(7)
    303 /** 8 Intercept reads of LDTR */
     303/** 8 Intercept reads of LDTR. */
    304304#define SVM_CTRL1_INTERCEPT_LDTR_READS        RT_BIT(8)
    305 /** 9 Intercept reads of TR */
     305/** 9 Intercept reads of TR. */
    306306#define SVM_CTRL1_INTERCEPT_TR_READS          RT_BIT(9)
    307 /** 10 Intercept writes of IDTR */
     307/** 10 Intercept writes of IDTR. */
    308308#define SVM_CTRL1_INTERCEPT_IDTR_WRITES       RT_BIT(10)
    309 /** 11 Intercept writes of GDTR */
     309/** 11 Intercept writes of GDTR. */
    310310#define SVM_CTRL1_INTERCEPT_GDTR_WRITES       RT_BIT(11)
    311 /** 12 Intercept writes of LDTR */
     311/** 12 Intercept writes of LDTR. */
    312312#define SVM_CTRL1_INTERCEPT_LDTR_WRITES       RT_BIT(12)
    313 /** 13 Intercept writes of TR */
     313/** 13 Intercept writes of TR. */
    314314#define SVM_CTRL1_INTERCEPT_TR_WRITES         RT_BIT(13)
    315 /** 14 Intercept RDTSC instruction */
     315/** 14 Intercept RDTSC instruction. */
    316316#define SVM_CTRL1_INTERCEPT_RDTSC             RT_BIT(14)
    317 /** 15 Intercept RDPMC instruction */
     317/** 15 Intercept RDPMC instruction. */
    318318#define SVM_CTRL1_INTERCEPT_RDPMC             RT_BIT(15)
    319 /** 16 Intercept PUSHF instruction */
     319/** 16 Intercept PUSHF instruction. */
    320320#define SVM_CTRL1_INTERCEPT_PUSHF             RT_BIT(16)
    321 /** 17 Intercept POPF instruction */
     321/** 17 Intercept POPF instruction. */
    322322#define SVM_CTRL1_INTERCEPT_POPF              RT_BIT(17)
    323 /** 18 Intercept CPUID instruction */
     323/** 18 Intercept CPUID instruction. */
    324324#define SVM_CTRL1_INTERCEPT_CPUID             RT_BIT(18)
    325 /** 19 Intercept RSM instruction */
     325/** 19 Intercept RSM instruction. */
    326326#define SVM_CTRL1_INTERCEPT_RSM               RT_BIT(19)
    327 /** 20 Intercept IRET instruction */
     327/** 20 Intercept IRET instruction. */
    328328#define SVM_CTRL1_INTERCEPT_IRET              RT_BIT(20)
    329 /** 21 Intercept INTn instruction */
     329/** 21 Intercept INTn instruction. */
    330330#define SVM_CTRL1_INTERCEPT_INTN              RT_BIT(21)
    331 /** 22 Intercept INVD instruction */
     331/** 22 Intercept INVD instruction. */
    332332#define SVM_CTRL1_INTERCEPT_INVD              RT_BIT(22)
    333 /** 23 Intercept PAUSE instruction */
     333/** 23 Intercept PAUSE instruction. */
    334334#define SVM_CTRL1_INTERCEPT_PAUSE             RT_BIT(23)
    335 /** 24 Intercept HLT instruction */
     335/** 24 Intercept HLT instruction. */
    336336#define SVM_CTRL1_INTERCEPT_HLT               RT_BIT(24)
    337 /** 25 Intercept INVLPG instruction */
     337/** 25 Intercept INVLPG instruction. */
    338338#define SVM_CTRL1_INTERCEPT_INVLPG            RT_BIT(25)
    339 /** 26 Intercept INVLPGA instruction */
     339/** 26 Intercept INVLPGA instruction. */
    340340#define SVM_CTRL1_INTERCEPT_INVLPGA           RT_BIT(26)
    341341/** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
    … …  
    355355 * @{
    356356 */
    357 /** 0 Intercept VMRUN instruction */
     357/** 0 Intercept VMRUN instruction. */
    358358#define SVM_CTRL2_INTERCEPT_VMRUN             RT_BIT(0)
    359 /** 1 Intercept VMMCALL instruction */
     359/** 1 Intercept VMMCALL instruction. */
    360360#define SVM_CTRL2_INTERCEPT_VMMCALL           RT_BIT(1)
    361 /** 2 Intercept VMLOAD instruction */
     361/** 2 Intercept VMLOAD instruction. */
    362362#define SVM_CTRL2_INTERCEPT_VMLOAD            RT_BIT(2)
    363 /** 3 Intercept VMSAVE instruction */
     363/** 3 Intercept VMSAVE instruction. */
    364364#define SVM_CTRL2_INTERCEPT_VMSAVE            RT_BIT(3)
    365 /** 4 Intercept STGI instruction */
     365/** 4 Intercept STGI instruction. */
    366366#define SVM_CTRL2_INTERCEPT_STGI              RT_BIT(4)
    367 /** 5 Intercept CLGI instruction */
     367/** 5 Intercept CLGI instruction. */
    368368#define SVM_CTRL2_INTERCEPT_CLGI              RT_BIT(5)
    369 /** 6 Intercept SKINIT instruction */
     369/** 6 Intercept SKINIT instruction. */
    370370#define SVM_CTRL2_INTERCEPT_SKINIT            RT_BIT(6)
    371 /** 7 Intercept RDTSCP instruction */
     371/** 7 Intercept RDTSCP instruction. */
    372372#define SVM_CTRL2_INTERCEPT_RDTSCP            RT_BIT(7)
    373 /** 8 Intercept ICEBP instruction */
     373/** 8 Intercept ICEBP instruction. */
    374374#define SVM_CTRL2_INTERCEPT_ICEBP             RT_BIT(8)
    375 /** 9 Intercept WBINVD instruction */
     375/** 9 Intercept WBINVD instruction. */
    376376#define SVM_CTRL2_INTERCEPT_WBINVD            RT_BIT(9)
    377 /** 10 Intercept MONITOR instruction */
     377/** 10 Intercept MONITOR instruction. */
    378378#define SVM_CTRL2_INTERCEPT_MONITOR           RT_BIT(10)
    379 /** 11 Intercept MWAIT instruction unconditionally */
     379/** 11 Intercept MWAIT instruction unconditionally. */
    380380#define SVM_CTRL2_INTERCEPT_MWAIT_UNCOND      RT_BIT(11)
    381 /** 12 Intercept MWAIT instruction when armed */
     381/** 12 Intercept MWAIT instruction when armed. */
    382382#define SVM_CTRL2_INTERCEPT_MWAIT_ARMED       RT_BIT(12)
    383383/** @} */
    … …  
    425425
    426426/**
    427  * SVM Selector type; includes hidden parts
     427 * SVM Selector type; includes hidden parts.
    428428 */
    429429#pragma pack(1)
    … …  
    438438
    439439/**
    440  * SVM GDTR/IDTR type
     440 * SVM GDTR/IDTR type.
    441441 */
    442442#pragma pack(1)
    … …  
    453453
    454454/**
    455  * SVM Event injection structure
     455 * SVM Event injection structure.
    456456 */
    457457#pragma pack(1)
    … …  
    473473
    474474/**
    475  * SVM Interrupt control structure
     475 * SVM Interrupt control structure.
    476476 */
    477477#pragma pack(1)
    … …  
    497497
    498498/**
    499  * SVM TLB control structure
     499 * SVM TLB control structure.
    500500 */
    501501#pragma pack(1)
    … …  
    514514
    515515/**
    516  * SVM IOIO exit structure
     516 * SVM IOIO exit structure.
    517517 */
    518518#pragma pack(1)
    … …  
    539539
    540540/**
    541  * SVM nested paging structure
     541 * SVM nested paging structure.
    542542 */
    543543#pragma pack(1)

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r42086 r42174  
    24242424                    Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
    24252425                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
    2426                     rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, uIOSize);
     2426                    rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
     2427                                            (DISCPUMODE)pDis->uAddrMode, uIOSize);
    24272428                }
    24282429                else
    … …  
    24302431                    Log2(("IOMInterpretINSEx  %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
    24312432                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
    2432                     rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, uIOSize);
     2433                    rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
     2434                                           (DISCPUMODE)pDis->uAddrMode, uIOSize);
    24332435                }
    24342436            }
注意: 瀏覽 TracChangeset 來幫助您使用更動檢視器

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette