儲存庫 vbox 的更動 46415

時間撮記:

2013-6-6 下午02:07:35 (11 年 以前)

作者:

vboxsync

訊息:

VMM/HMVMXR0: Fix invalidating EPT-tagged TLB-entries when VPID+EPT is in use.

檔案:

• trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (修改) (13 筆差異)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -1160 +1160 @@
      * We cannot flush a page by guest-physical address. invvpid takes only a linear address while invept only flushes
      * by EPT not individual addresses. We update the force flag here and flush before the next VM-entry in hmR0VmxFlushTLB*().
-     * This function might be called in a loop.
+     * This function might be called in a loop. This should cause a flush-by-EPT if EPT is in use. See @bugref{6568}.
      */
     VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
@@ -1224 +1224 @@
      */
     bool fNewASID = false;
-    if (   pVCpu->hm.s.idLastCpu != pCpu->idCpu
+    if (   pVCpu->hm.s.idLastCpu   != pCpu->idCpu
         || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
     {
@@ -1260 +1260 @@
         else
         {
-            if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
-                hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_SINGLE_CONTEXT, 0 /* GCPtr */);
-            else
-                hmR0VmxFlushEpt(pVM, pVCpu, pVM->hm.s.vmx.enmFlushEpt);
+            /*
+             * Changes to the EPT paging structure by VMM requires flushing by EPT as the CPU creates
+             * guest-physical (only EPT-tagged) mappings while traversing the EPT tables when EPT is in use.
+             * Flushing by VPID will only flush linear (only VPID-tagged) and combined (EPT+VPID tagged) mappings
+             * but not guest-physical mappings.
+             * See Intel spec. 28.3.2 "Creating and Using Cached Translation Information". See @bugref{6568}.
+             */
+            hmR0VmxFlushEpt(pVM, pVCpu, pVM->hm.s.vmx.enmFlushEpt);
         }
 
@@ -1338 +1342 @@
      * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
      */
-    if (   pVCpu->hm.s.idLastCpu != pCpu->idCpu
+    if (   pVCpu->hm.s.idLastCpu   != pCpu->idCpu
         || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
     {
@@ -1404 +1408 @@
      * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
      */
-    if (   pVCpu->hm.s.idLastCpu != pCpu->idCpu
+    if (   pVCpu->hm.s.idLastCpu   != pCpu->idCpu
         || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
     {
@@ -8174 +8178 @@
     /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
     AssertRCReturn(rc, rc);
+
     Log4(("CS:RIP=%04x:%#RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
 
@@ -8196 +8201 @@
         PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
         /** @todo for now manually disassemble later optimize by getting the fields from
-         *        the VMCS. */
-        /** @todo VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR contains the flat pointer
+         *        the VMCS. VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR contains the flat pointer
          *        operand of the instruction. VMX_VMCS32_RO_EXIT_INSTR_INFO contains
          *        segment prefix info. */
@@ -8347 +8351 @@
         {
             uint32_t uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
+
             /* Software interrupts and exceptions will be regenerated when the recompiler restarts the instruction. */
             if (   uIntType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT
@@ -8370 +8375 @@
                     pVCpu->hm.s.Event.GCPtrFaultAddress = pMixedCtx->cr2;
                 }
+
                 Log4(("Pending event on TaskSwitch uIntType=%#x uVector=%#x\n", uIntType, uVector));
             }
         }
     }
+
     /** @todo Emulate task switch someday, currently just going back to ring-3 for
      *        emulation. */
@@ -8864 +8871 @@
         {
             case OP_CLI:
+            {
                 pMixedCtx->eflags.Bits.u1IF = 0;
                 pMixedCtx->rip += pDis->cbInstr;
@@ -8869 +8877 @@
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
                 break;
+            }
 
             case OP_STI:
+            {
                 pMixedCtx->eflags.Bits.u1IF = 1;
                 pMixedCtx->rip += pDis->cbInstr;
@@ -8878 +8888 @@
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
                 break;
+            }
 
             case OP_HLT:
+            {
                 rc = VINF_EM_HALT;
                 pMixedCtx->rip += pDis->cbInstr;
@@ -8885 +8897 @@
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
                 break;
+            }
 
             case OP_POPF: